JPH03258134A - Serial signal transmission circuit - Google Patents

Abstract

PURPOSE:To transmit a serial signal SS only for two consecutive frame transmis sion end signals FE are inputted through the reception of a timing signal and to reduce the cost by generating a 1-frame transmission end signal FE for each frame end of a serial signal SS-generated continuously. CONSTITUTION:A serial signal transmission section 11 sends a continuous serial signal SS and a 1-frame transmission end signal FE for each end of frame based on an output of an oscillator 10. Upon the receipt of a timing signal from a timing generating circuit 12, a control circuit 13 generates a control pulse for a period of 1-frame inputted by a succeeding FE from the point of time of the input of the signal FE from the transmission section 11 just after the input of the timing signal. A gate circuit 14 extracts the signal SS, for one frame period only for the received control pulse period and sends the extracted signal. Thus, even when the timing signal and the signal SS are a synchronous, the signal SS is extracted without use of a CPU, the cost of software is reduced and simple and small sized circuit constitution is attained.

Description

[Detailed Description of the Invention] (Summary) The purpose of this invention is to reduce the degree of software intervention for transmission control regarding a circuit that extracts and transmits an arbitrary frame of serial signals from a serial signal string that is continuously generated. a serial signal transmitter that continuously generates a serial signal and generates a one-frame transmission end signal at the end of each frame of the serial signal; a timing generation circuit that generates an arbitrary timing signal; a control circuit that receives the one-frame transmission end signal from the unit and the timing signal from the timing generation circuit, and generates a control pulse while two successive one-frame transmission end signals are input based on the timing signal; and a gate circuit that passes through and transmits only the serial signal that is input during the input period of the control pulse among the serial signals that are continuously sent out from the serial signal sending section.

[Industrial application field]

The present invention relates to a serial signal transmitting circuit, and more particularly to a circuit that extracts and transmits an arbitrary frame of serial signals from a serial signal string that is continuously generated.

In serial data transmission, as shown in FIG.
A serial signal in a frame format with a stop bit SO added to the end is transmitted frame by frame, and on the receiving side, the bit divisions of this serial signal are identified by the start bit SA and stop bit SO.

In such serial data transmission, the transmitting side selects any one of the output serial signal strings of the serial signal generator, which continuously generates serial signals with the same data content.
When a frame is extracted and transmitted, it is desirable to implement a circuit section for extracting any one frame with a simple and small-scale circuit configuration with less software intervention.

[Prior Art] FIG. 7 shows a configuration diagram of an example of a conventional serial signal transmission circuit. In the figure, 1 is a central processing unit (CPU), which continuously generates serial signals with the same data content frame by frame through its software processing. 2 is an LSIC large-scale integrated circuit for serial signals, and the above input One frame is extracted from the serial signal string based on control from the CPU 1 and transmitted.

Therefore, according to this conventional circuit, the number of frames to be transmitted and the transmission timing (arbitrary or periodic interval) can be arbitrarily determined by software processing of the CPU 1.

[Problem to be solved by the invention]

However, in the above conventional circuit, the serial signal transmission LS
Since the transmission control by I2 is performed by software processing of CPLJl, and the transmission IIJ1[l is made to be able to handle various transmission timings and numbers of transmission frames, it takes a great deal of time and money to develop the software. Moreover, the scale of the software increases. In particular, if the transmission/reception sequence is simple, such as transmitting only one frame at arbitrary or periodic intervals, software has little advantage.

The present invention has been made in view of the above points, and an object of the present invention is to provide a serial signal transmission circuit that can reduce the degree of software intervention for transmission control.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. In the same figure, 11
1 is a serial signal sending section which continuously generates a serial signal and also generates a one frame transmission end signal at the end of each frame of the serial signal.

12 is a timing generation circuit that generates an arbitrary timing signal. Reference numeral 13 denotes a control circuit that generates a control pulse while two consecutive one-frame transmission end signals are input based on the timing signal.

Reference numeral 14 denotes a gate circuit which passes through and transmits only the serial signal input during the input period of the control pulse described above.

[Effect]

In the present invention, from the timing generation circuit 12, as shown in FIG.
When the timing signal shown in is input to the control circuit 13,
Immediately after that, the period control circuit 13 for one frame generates a control pulse as shown in FIG. 2(E) from the time of input of the one-frame transmission end signal shown in FIG. 2(C) taken out from the serial signal sending unit 11.

As a result, the gate circuit 14 passes the serial signal train shown in FIG. In order to do this, the gate circuit 14 extracts and transmits one frame of serial signals immediately after the timing signal is input, as schematically shown in FIG. 2(B).

In this way, in the present invention, even if the timing signal and the serial signal are completely asynchronous, the one frame transmission end signal is used as the control pulse generation trigger without using the CPU, so one frame can be reliably generated without using CPLI. The serial signal can be extracted.

〔Example〕

FIG. 3 shows a circuit diagram of one embodiment of the present invention. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In FIG. 3, the serial signal sending unit 11 is
It is composed of PU111 and LS1112. L.S.
1112 is a well-known large-scale integrated circuit with the model name MB653642, for example, which receives the clock input from the oscillator 10 and C
Based on the data (2 bytes) from the PU 111, the serial signal a is continuously generated as shown in FIG.
One frame transmission end signal @ (EOP) as shown in Figure (B)
) generate b. The pulse width of this one-frame transmission end signal matches the bit rate of the serial signal a, and therefore the clock rate supplied to the timing generation circuit 12 and IIJ control circuit 13, which will be described later, is adjusted to this.

The timing generation circuit 12 is composed of a programmable frequency division counter 121, and a pulse obtained by dividing the output pulse of the oscillator 10 by m by an m frequency divider 20 is supplied as a clock, and the pulse is divided by a desired frequency division ratio. The frequency is divided and a pulse C is outputted from the carry output terminal at a period as shown in FIG. . This pulse C is flipped 70 to J- as a timing signal.
It is input to one terminal of the knob 131.

The flip-flop 131 is connected to this J- by an AND circuit 132.
, 133 and J- constitute a control circuit 13 together with a flip-flop 134, and a flip-flop 1 is connected to J-.
A pulse from the m frequency divider 20 is applied to each clock terminal 31 and 134. Flip-flop 131 to J-
When the timing signal C input to one terminal of becomes high level, the flip-flop 131 is set to J-,
The Q output signal d becomes high level as shown in FIG. 4(D), and the σ output signal becomes low level.

As a result, the AND circuit 132 becomes in the gate "open" state, and the AND circuit 133 becomes in the gate "closed" state. Therefore, after the timing signal C becomes high level,
The first frame transmission end signal (EOP) b is input to the terminal of the flip 70 knob 134 through the AND circuit 132.

At this time, since the gate of the AND circuit 133 is in the "closed" state, it prevents the one frame transmission end signal from passing through.
The signal f applied from the AND circuit 133 to the 5th terminal of the flip-flop 134 is at a low level as shown in FIG.

Therefore, FIG. 4 (E
), the 0 output signal Q of the jK flip-flop 134 changes to a high level as shown in FIG. 4(G). This σ output signal @Q is input as a control pulse to an AND circuit 141 (described later), and is also applied to the terminal of the flip 70 knob 131 at J-, so that the set state (window opening ready) of the flip 70 knob 131 is applied to J-. status).

As a result, the Q output signal d becomes low level, and this time the AND circuit 132 is brought into the gate "closed" state, and the AN
Since the D circuit 133 is placed in the gate "side" state, the next one-frame transmission end signal that is input passes through only one of the AND circuits 132 and 133 and is sent to one terminal of the flip-flop 134 to J-. applied and flips to J-7
The 0 knob 134 is placed in a reset state. As a result, the control pulse Q changes from high level to low level as shown in the fourth factor (G).

The control pulse Q is the one frame transmission end signal immediately after the timing signal W'tC is input, and the next one.
It is at a high level only during one frame period until the frame transmission end signal is reached, and only during this one frame period the AND circuit 14
1 is in the gate "open" state, the continuous serial signal a is taken out from the AND circuit 141 only during this one frame period as shown by h in FIG. is transmitted as a serial extracted signal.

In this way, according to this embodiment, only one frame can be reliably extracted. Furthermore, in this embodiment, there is a CPU 111 in the serial signal sending section 11, but this CPU 111 merely generates data for continuously generating serial signals, and has no relation to serial signal extraction and transmission control. Therefore, the software can be significantly simplified compared to conventional methods.

Next, other embodiments of the present invention will be described. FIG. 5 shows a configuration diagram of main parts of another embodiment of the present invention.

This example is shown in Fig. 3 and has the same configuration as $1112.
Using four SIs as shown in 31 to 34, their TR
AND circuit 14 of gate circuit 14 by combining the X output terminals
This is a packet configuration connected to one input terminal of 1, and the other configuration is the same as that in FIG. 3.

In this embodiment, 1 from the terminal EOP of the fourth LSr34.
Since only the frame transmission end signal is supplied to the control circuit 13, from the time of input of the one frame transmission end signal immediately after the timing signal input in the continuous serial signal train, four
During the frame period, the control pulse is at a high level, and the serial signal can be extracted and transmitted during this four frame period.

It should be noted that the present invention is not limited to the above-described embodiments; for example, by using the timing generation circuit 12 in FIG. 3 as a register directly connected to the CPU, it is possible to extract and transmit one frame of serial data at any timing. can.

[Effects of the Invention] As described above, according to the present invention, CPLI can be extracted from serial signal I! Since the serial signal is extracted using only the hardware configuration without using it in IIIa, the cost and time for developing CPU software can be significantly reduced compared to the conventional method, and all digital circuits are used. Because of this configuration, it has features such as being able to have a simple and compact circuit configuration.

In the figure, 11 is a serial signal sending unit; 12 is a timing generation circuit; 13 is a control circuit; 14 is a gate circuit shows.

Claims (1)

[Claims] A serial signal transmitter (11) that continuously generates a serial signal and generates a one-frame transmission end signal at the end of each frame of the serial signal, and a timing generator that generates an arbitrary timing signal. The circuit (12) receives the one-frame transmission end signal from the serial signal sending unit (11) and the timing signal from the timing generation circuit (12), and generates two consecutive frames based on the timing signal. A control circuit (13) that generates a control pulse while a frame transmission end signal is input, and a control circuit (13) that generates a control pulse during the input period of the control pulse of the serial signal that is continuously transmitted from the serial signal transmitter (11). A serial signal transmitting circuit comprising: a gate circuit (14) that passes through and transmits only an input serial signal;