JPH03258022A - Dual loop type pll circuit - Google Patents

Abstract

PURPOSE:To attain smooth clock switching without a large fluctuation in the oscillating frequency by implementing the switching of self-running and subsequent state of a dual loop type PLL circuit based on raw information representing the clock input interruption after the lapse of a proper time. CONSTITUTION:When the state of the presence of a data input is switched to the state of the absence thereof, in the case of sets of sharpness Q1, Q2 of 1st and 2nd clock intermediate frequency circuits 1, 2 being in the state of Q1>Q2, the relation of times T1, T2 from the data input interruption till the loss of the clock is T1>T2. On the other hand, when the relation of T2+T3<=T1 is satisfied, where T3 is a delay time when clock interruption is detected by a clock input interruption detection circuit 4 and till the output of a selector 7 is switched into an output of a reference voltage generating circuit 5, the input voltage to a voltage controlled oscillator 14 in a dual loop type PLL(Phase Locked Loop) circuit 6 is largely fluctuated. The self-running state is transited smoothly without largely fluctuating the oscillating frequency.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a double loop type PL for digital transmission.
The present invention relates to a Phase Lock@d Loop (L) circuit, and particularly to a double-loop PLL circuit having a function of switching to a free-running clock when clock input is interrupted.

[Conventional technology]

Conventionally, this type of double-loop PLL circuit has a basic configuration as shown in FIG. 2, which includes two frequency divider circuits 8 and S, and a constant term and a proportional term that compare the phases of the divided outputs of these circuits. It consists of a phase comparison circuit 10.11, a constant term and proportional term low pass filter 12.13 that smoothes each comparison output and converts it into a DC voltage, and a voltage controlled oscillator 14 that uses each voltage output as a control input voltage. 1. By inputting the oscillation output, the input data of the transmission line, and the extracted clock to each frequency dividing circuit 8.9, the voltage controlled oscillator 14
It is designed to output an oscillation frequency output corresponding to the input clock from the input clock.

[Problem to be solved by the invention]

However, the conventional double-loop PLL circuit described above is
Since the output of the constant term phase comparison circuit W&100 is fixed to the power supply voltage box or ground level when data input is interrupted, the oscillation frequency of the voltage controlled oscillator 14 is fixed to the upper limit or lower limit of the variable limit, and varies from the center oscillation frequency. There is a problem in that there is a large shift in the housing.

[Means to solve the problem]

In order to solve such problems, the present invention includes a fourth clock identification circuit for extracting a clock from input data and inputting the clock to a double-loop PLL circuit, and a fourth clock identification circuit for extracting a clock from the input data. a second clock identification circuit; a clock input disconnection detection circuit that determines whether or not a clock input is present in the clock extracted from the second clock identification circuit; and a reference voltage generation circuit that generates a predetermined voltage; a selector that selects the DC voltage output from the PLL circuit and the voltage of the reference voltage generation circuit based on the detection output of the clock input disconnection detection circuit, and supplies the selected DC voltage and the voltage of the reference voltage generation circuit as input voltages to the voltage controlled oscillator in the PLL circuit; The reference voltage generation circuit performs free-running oscillation in accordance with the voltage supplied from the reference voltage generation circuit when the clock input is interrupted.

[Effect]

According to the present invention, it is possible to smoothly switch to a free-running clock when clock input is interrupted.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a double loop type PLL circuit according to the present invention. In the figure, 1 is a first clock identification circuit that extracts a clock from input data 3 of the transmission line and inputs the clock to a double-loop PLL@line 6 similar to that in FIG. 2, and 2 is the same input. This is a second clock identification circuit for extracting a clock from data 3. Further, 4 is a clock input disconnection detection circuit that determines the presence or absence of a clock input based on the clock output from the second clock identification circuit 2, 5 is a reference voltage generation circuit that generates a predetermined voltage, and 7 is a clock input circuit. Selecting the Di current voltage output from the double loop type PLL circuit 6 and the voltage of the reference voltage generation circuit 5 based on the detection output of the disconnection detection circuit 4,
The voltage controlled oscillator 14 (second
It is a selector that is supplied as an input terminal to
The PLL circuit 6 is free-running in accordance with the voltage supplied from the reference voltage generation circuit 5 when the clock input is cut off.

Next, the operation of the configuration of the above embodiment will be explained in three different states depending on the data input state.

(1) When data is input The input data 3 is connected to the first clock identification circuit 1 having a resonant circuit with a sharpness of Q1 and a sharpness of Q! The clock is extracted by the second clock identification circuit 2 having a resonant circuit, and the clock extracted by the first clock identification circuit 1 is sent to the double-loop type PLL circuit 6 and then to the second clock identification circuit 6. The clock extracted at step 2 is supplied to a clock input disconnection detection circuit 4. At this time, when the clock input disconnection detection circuit 4 is in the clock detection state, the selector T is of the double loop type P.
By selecting the input voltage to the output voltage controlled oscillator 14 from the LL circuit 6, this double loop type PLL circuit 6
Now, as in the conventional case, the own output and clock identification circuit 1
The clocks supplied from each are divided and their phases are compared.

(2) In the case of switching from data input 1 to no data input When switching from a state with data input to a state without data input, the sharpness k Q 1 of the first clock identification circuit 1 and the second clock identification circuit 2 Q! If we make it so that
For snow, Tt>T.

On the other hand, when the clock input disconnection detection circuit 4 detects a complete clock disconnection and the delay time in the case for switching the output of the selector 7 to the output side of the reference voltage generation circuit 5 is T3, Tl+T3≦TI
If the following relationship is satisfied, it is possible to change the input voltage to the voltage controlled oscillator 14 in the double-loop PLL circuit 6 to a free-running state without greatly changing the oscillation frequency. After shifting to the free-running state, it continues to oscillate in accordance with the voltage supplied from the reference voltage generation circuit 5.

(3) When switching from no data input to data input When switching from no data input to data input, when the time constant of the constant term low-pass filter 12 in the double-loop PLL circuit 6 is T4, the clock input When the disconnection detection circuit 4 detects the presence of input and outputs all information indicating the presence of input, T4<T.
Output is prohibited for a time Ts that satisfies I. For this reason,
During this period of time 15, the input voltage of the voltage controlled oscillator 14 settles to the steady value when there is an input, and the input voltage of the voltage controlled oscillator 140 changes greatly, and the oscillation frequency changes from the free-running state to the dependent state. can be migrated.

As explained above in (1) to (3) t, it is possible to smoothly switch to the free-running clock when data input is interrupted.

〔Effect of the invention〕

As described above, the present invention allows a double-loop PLL circuit to switch between free-running and dependent states after an appropriate period of time from raw information of clock input disconnection, thereby ensuring a smooth transition that does not cause large fluctuations in the oscillation frequency. Switching the lock (the effect that can be achieved is increased).

[Brief explanation of drawings]

FIG. 1 is a block 11 diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram of a conventional double-loop PLL circuit. 1...First clock identification circuit, 2...Second clock identification circuit, 3...Input data, 4...
Clock input disconnection detection circuit, 5... reference voltage generation circuit, 6... double loop type PLL time M, 7... selector.

Claims (1)

[Claims] In a double-loop PLL circuit, a first clock identification circuit extracts a clock from input data and inputs the clock to the PLL circuit, and a second clock identification circuit extracts a clock from the input data. a clock input disconnection detection circuit that determines the presence or absence of a clock input based on the clock output from the second clock identification circuit; a reference voltage generation circuit that generates a predetermined voltage; and a detection circuit for detecting the clock input disconnection detection circuit. Based on the output of the PLL
It is equipped with a selector that selects the DC voltage output from the circuit and the voltage of the reference voltage generation circuit and supplies it as an input voltage to the voltage controlled oscillator in the PLL circuit, and when the clock input is cut off, the voltage is supplied from the reference voltage generation circuit. 1. A double-loop type PLL circuit, characterized in that it performs free-running oscillation according to the voltage applied to it.