JPH03257681A - Picture processor - Google Patents

Abstract

PURPOSE:To extract picture element signals at equal interval positions concerning the both directions of a matrix for a picture by setting a matrix-shaped mask area to the picture for each field to be generated by a picture signal in jump scanning, and extracting the picture element signal for every two picture elements concerning the picture element for each horizontal scanning area in the mask area. CONSTITUTION:A matrix-shaped mask area 34 is set to a picture B for each field to be generated by the picture signal in jump scanning, and the picture element signal is extracted for every two picture elements concerning the picture element for each horizontal scanning line in the mask area 34. Thus, the picture element signals can be extracted at the equal interval positions concerning the both directions of the matrix of the picture. Therefore, it is not necessary to synthesize the picture for one frame by the picture signal for two fields while using a scan comparator, and the simplification of configuration and the improvement of responsiveness in the processing to the picture input can be realized.

Description

[Detailed Description of the Invention] <Industrial Application Field> This invention sets a matrix-like mask area for a human image, scans it, extracts a pixel signal for each pixel in the mask area, and performs processing such as differentiation. The present invention relates to an image processing device that executes.

<Prior Art> FIG. 6 shows an example of a conventional image processing apparatus l of this type. This image processing device l has an imaging device 2 that images an object and outputs an image signal by interlaced scanning.
The analog image signal from the imaging device 2 is converted into a digital signal by the A/D converter 3. The scan converter 4 synthesizes the odd field image signal and the even field image signal and outputs an image signal for l frames. This image signal is input to the processing circuit 5, subjected to differential processing, and converted into an edge image from which edges are extracted. This edge image is stored in the image memory 6, and the contents of the image memory 6 are converted into an analog image signal by the D/A converter 7 and output to the display device 8. Note that the CPU 14 sequentially controls the entire operation of the image processing device 1.

FIG. 7 shows an example of the configuration of the processing circuit 5. The local memory 9 in the illustrated example, which includes a local memory 9 and an arithmetic circuit 10, stores predetermined pixel data of one frame's worth of digital image signals. Nine registers lla~ to store
It is equipped with lli. First stage registers lla to llc
A digital image signal is given from the scan converter 4, and pixel data for three pixels is sequentially shifted and stored in synchronization with each pixel. 2nd stage register lid~l
In lf, the image signal applied to the first stage registers 1la to 11c is delayed by l horizontal scanning period by the delay circuit 12, and each pixel data is sequentially shifted and stored. Further, the image signal outputted from the delay circuit 12 is input to the third stage registers l1g to lli after being delayed by l horizontal scanning period by the delay circuit 13, and each pixel data is similarly shifted and stored in sequence. The arithmetic circuit 10 inputs the pixel data output from each of the registers lla to lli, performs a differential operation, extracts the edges of the image, and outputs them to the image memory 6.

By the way, as shown in FIG. 8(1), the image signal by interlaced scanning consists of an image signal VD' applied to odd-numbered horizontal scanning lines and an image signal VD' applied to even-numbered horizontal scanning lines. These image signals VD', VD'' which appear alternately are synthesized by the scan converter 4 to form an image signal VO for one frame (shown in FIG. 8(2)).

FIG. 9(1) shows the concept of interlaced scanning, in which odd-numbered horizontal scanning lines are shown as solid lines and even-numbered horizontal scanning lines are shown as broken lines.

Further, FIG. 9(2) shows the concept of sequential scanning, and solid lines indicate each horizontal scanning line involved in sequential scanning. The image signal output from the scan converter 4 corresponds to the signal resulting from this sequential scanning.

Returning to FIG. 7, the local memory 9 is
This is for setting and scanning a mask area 15 including pixels of 3 rows x 3 columns for a frame of image A. Each pixel in this mask area 15 is denoted by reference numerals a-i. The arithmetic circuit 10 calculates the differential value of the center pixel e of the mask area 15 from the pixel data of the surrounding pixels a-d, fxi, and calculates the edge of the image. Extract.

FIG. 11 (1) shows the letters 'A'', rB'', and rC.

This shows a grayscale image, and noise 16 and shading 17 occur in this grayscale image.

When this grayscale image is differentially processed by the processing circuit 5,
An edge image with extracted edges as shown in FIG. 11(2) is obtained. At this time, the shading 17 is removed because it does not have a clear outline, but the noise 16 remains as noise 18 from which edges have been extracted.

This edge image is scanned by setting a template 19 as shown in FIG. 11(3), and character recognition is performed by counting the number of matching pixels between the edge image and the template 19. According to such a recognition processing method, character recognition can be performed without any problem even if shading 17 and noise 16 are present.

<Problems to be Solved by the Invention> In the image processing apparatus having the above configuration, if an image signal by interlaced scanning is directly input to the processing circuit 5, if the mask area is set for this input image, , each pixel data of three consecutive pixels is extracted in the row direction, and 3ii! of every other pixel is extracted in the column direction. Each element's pixel data is extracted and differential processing is performed. Therefore, the configuration is such that the scan converter 4 is used to extract each pixel data of three consecutive pixels in any direction of the matrix, but this requires the scan converter 4, making the structure complicated. The manufacturing cost of the device is also high.

In addition, since image signals for two fields are accumulated and output in the scan converter 4, a delay time Tl corresponding to one field period occurs as shown in FIG. 8 (2), and this delay time The operation time T2 (eighth) by the processing circuit 5 is added to T1
A delay of the time TI+72 (shown in FIG. 3) is unavoidable, and there is a problem that the responsiveness of processing to the image input from the imaging and copying device W2 is poor.

The present invention is intended to solve the above-mentioned technical problems, and aims to provide an image processing apparatus that has a simplified configuration and improved processing responsiveness to human image processing.

<Means for Solving the Problems> The present invention is an image processing device having an image signal generating means and a mask scanning means, in which the image signal generating means generates an image signal by interlaced scanning, and the mask scanning means generates an image signal by interlaced scanning. A matrix-shaped mask area spanning a plurality of horizontal scanning lines is set and scanned for each field image generated by the image signal. The mask scanning means is provided with means for extracting pixel signals every other pixel for each horizontal scanning line within the mask area.

<Operation> A matrix mask area is set for each field image generated by an image signal by interlaced scanning, and pixel signals are extracted every other pixel for each horizontal scanning line within the mask area. , pixel signals at equally spaced positions in both directions of the image matrix can be extracted. Therefore, it is no longer necessary to use a scan converter to convert one frame of image to two fields of image signals, thereby simplifying the configuration and improving the responsiveness of processing to image input.

<Embodiment> FIG. 1 shows an image processing device 2 according to an embodiment of the present invention.
It shows the authority of 1.

The device f21 in the illustrated example includes an imaging device 22 that images an object and outputs an image signal by interlaced scanning, as well as an A/D converter 23. Processing circuit 242 Image memory 25, D/A conversion converter 2 1 FIG. 2 shows an example of the configuration of the processing circuit 24, which includes a local memory 29 and an arithmetic circuit 30. The local memory 29 includes 15 registers 31a to 31o for storing predetermined pixel data of a digital image signal during one field period. 1st stage register 31
A to 31e are given digital image signals from the A/D converter 23, and pixel data of five pixels is sequentially shifted and stored in synchronization with each pixel.

The image signals stored in the first stage registers 31a to 31e are input to the second stage registers 31f to 31j after being delayed by l horizontal scanning period by the delay circuit 32, and each pixel data is sequentially shifted and stored. Ru. In addition, the image signal output from the delay circuit 32 is inputted to the third stage register 31 to 31o after being delayed by one horizontal scanning period by the delay circuit 33, and similarly, each pixel data is sequentially shifted and stored. .

The arithmetic circuit 30 receives the outputs of registers 31a, 31c, 31e from the first register row, and registers 31f, 31h, . The output of 31i is sent to register 3 1 k,
3 1m, 31.

The outputs of are given respectively. The arithmetic circuit 30 is
The pixel data output from each of the registers is inputted, differential operations are performed, edges of the image are extracted, and the edges are output to the image memory 25.

FIG. 3 (1) shows an image signal by interlaced scanning, and VD
' is the image signal applied to the odd horizontal scanning line, V
D'' indicates an image signal applied to an even-numbered horizontal scanning line. Also, Fl and F2 are each field period,
The processing circuit 24 outputs an edge image signal (shown in FIG. 3(2)) with a delay of processing time Δt required for differential processing.

Returning to FIG. 2, the local memory 29 stores the image B for one field shown in FIG. 4 and the enlarged view (FIG. 5).
This is for setting and scanning a mask area 34 including 3 rows (horizontal scanning lines by interlaced scanning) x 5 columns of pixels. Among the pixels included in this mask area 34, pixel data for every other pixel at the position indicated by reference symbol a=j is extracted and taken into the arithmetic circuit 30.

The calculation circuit 30 calculates the differential value of the center pixel e of the mask area 34 from the pixel data of the surrounding pixels a to d, f=i, and extracts the edges of the image. That is, each pixel a =
The pixel data of i is expressed as D (a) to D (i),
If the differential value is expressed as dD(a) to dD(i), the differential value dD(e) of the center pixel e of the mask area 34 is dD(e)=1Δx−D(e)l+lΔV−D(e)・
...... Indicated by ■. Here, Δx−D(e)=D(i)+2 D(f)+D(
c)-(D(g)+2 D(a)+D(a))-...■
Δy−D(e)=D(i)+2 DCh)+D(g
) − (D (C) + 2 D (b) + D (a)) ・−
...■. In this way, the arithmetic circuit 30 performs the differential calculations according to the above formulas 1 to 3 in real time based on the pixel data D (a) to D (i) of each pixel a-i, and calculates the edge of the image. Extract.

<Effects of the Invention> As described above, the present invention sets a matrix-like mask area for each field image generated by an image signal by interlaced scanning, and sets one pixel for each horizontal scanning line within the mask area. Since pixel signals are extracted every other pixel, pixel signals at equally spaced positions can be extracted in both directions of the image matrix. Therefore, it is no longer necessary to use a scan converter to convert one frame of image to two fields' worth of image signals, and it is possible to simplify the configuration and improve the responsiveness of processing to human image processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a processing circuit, FIG. 3 is a waveform diagram of an image signal appearing in this embodiment, and FIG.
The figure is an explanatory diagram showing the setting state of the mask area, Fig. 5 is an enlarged view thereof, Fig. 6 is a block diagram of a conventional image processing device, Fig. 7 is a block diagram showing an example of the configuration of a processing circuit, and Fig. 8 9 is an explanatory diagram showing the concept of interlaced scanning and sequential scanning. FIG. 10 is an explanatory diagram showing the setting state of the mask area 15 in the conventional example. FIG. It is an explanatory diagram to explain. 21...Image processing device 24...Processing circuit 30...Arithmetic circuits 32, 33...Delay circuit 22...Imaging device 29...Local memories 31a to 31o... ··register

Claims (1)

[Scope of Claims] An image signal generating means for generating an image signal by interlaced scanning, and setting a matrix-like mask area spanning a plurality of horizontal scanning lines for each field image generated by the image signal. An image processing apparatus comprising: a mask scanning means for scanning, the mask scanning means comprising means for extracting a pixel signal every other pixel for each pixel of each horizontal scanning line in a mask area.