JPH03256477A - Picture signal reproducing device - Google Patents

Abstract

PURPOSE:To exactly and stably reproduce an arbitrary still picture signal by detecting whether the frequency of a pilot signal is superimposed onto that of a picture signal recorded to a video floppy or not. CONSTITUTION:It is detected whether the pilot signal is recorded or not together with the picture signal to a track on a video floppy 2 to which magnetic heads 3-1 and 3-2 are abutted. Namely, according to whether the pilot signal is added to the picture signal to be reproduced from the recording medium or not, it is discriminated whether the picture signal is reproduced from the track recording high fidelity still picture signals for one picture or reproduced from the track recording still picture signals for one field or one frame. Thus, the arbitrary still picture signal can exactly and stably be reproduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal reproducing device for reproducing image signals recorded on a recording medium.

[Conventional technology] Conventionally, CCD (Charge (:upled)
An electronic still video camera (hereinafter referred to as a floppy camera) has already been commercialized as a system for recording an image signal obtained from an image sensor such as a device as a still image signal on a disc-shaped magnetic recording medium (video floppy).

Images recorded with this floppy camera do not require a developing process like silver halide photography, so they can be viewed immediately by displaying them on a TV monitor or making hard copies with a video printer. be.

By the way, the image quality of images taken with such a floppy camera is based on the current television system such as NTSC or PAL, so the vertical resolution is about 500 lines and the horizontal resolution is CCD. Since the number of pixels is limited, even if it is made into a hard copy, the image quality (particularly resolution) is insufficient compared to a silver halide photograph.

Therefore, a still image for one screen is composed of four field images, and the field image signal corresponding to each field image is recorded in the conventional recording format, that is, the FM carrier frequency and recording track pattern when FM modulating the moderation signal. etc. are recorded using the four tracks on the video floppy without any changes, and the four field image signals reproduced from the four tracks on the video floppy are reconstructed using the image memory, and the conventional Comparatively horizontal.

A system is being considered that converts the image into a still image signal with almost double the vertical resolution and displays it on a monitor or hard copy it using a video printer.

That is, in the above system, for example, the number of pixels is 500 pixels (vertical direction) x 120 pixels as shown in FIG.
Using a two-root system floppy camera in which CCD1 and CCD2 with 0 pixels (horizontal direction) are arranged with vertical pixel shifts relative to the subject, pixel information at the positions marked with ○ in Fig. 4 can be obtained. Sunblink, CCD 1 and CC
Odd fields of D2 (1, 3, 5... and 1
' , 3'5'...) and even field (2
, 4, 6... and 2', 4', 6'...
) are simultaneously read out and recorded on a video floppy in a pattern as shown in FIG.

Also, during recording, when storing the reproduced image signal in the image memory during reproduction, a pilot signal (f) is used to form a sampling clock having a jitter component equal to that of the image signal reproduced from the video floppy. Multiplex and record the lower wave side of the signal.

On a floppy disk recorded by the system described above, the image signals for two fields output from one CCD are recorded on two tracks on a conventional video floppy, so the two fields are It is also possible to form an image signal for one frame using image signals for two fields recorded on the track.

Now, the playback device in the system as described above is the sixth
It is configured as shown in the figure.

First, in Fig. 6, the motor l is set at 3600 rpm.
As mentioned above, there is a t on the video floppy 2 that is rotating.
A recording pattern as shown in FIG. The magnetic head 3 is brought into contact with the A track of the recording pattern shown in FIG.
The reproduction signal reproduced by -1 is amplified to an appropriate level by reproduction amplifier 5-1, and then sent to FM demodulation circuit 6.
The de-emphasis circuit 7 suppresses noise components generated during recording and reproduction, and outputs from the eight terminals 23 as an image signal compliant with the NTSC system.

Further, a synchronization signal is separated from the image signal output from the de-emphasis circuit 7 by a synchronization separation circuit 9, and after being subjected to amplitude correction, two-phase correction, etc. in a vase 8 such as a transmission line, an A/
The signal is input to the D converter 18. Further, the synchronization signal separated by the synchronization separation circuit 9 is input to the memory controller 17, and the memory controller 17 forms a vertical address reset signal and a horizontal address reset signal in the image memory.

On the other hand, the pilot signal recorded on the video floppy 2 along with the image signal is separated from the reproduced signal by the BPFIO, amplified to an appropriate level by the amplifier 11, and then input to the phase comparator 12. On the other hand, the other input of the 1-phase comparator 12 is supplied with a sampling clock generated from a voltage controlled oscillator (VCO) 14 or a frequency divided by a frequency divider 15 to have the same frequency as the pilot signal. . 13 is P L L (Phase Locke
Loop) is a loop filter that determines the response characteristics of the loop. That is, when the switch S2 is connected to the a side in the figure, the sampling clock generated from the VCO 14 is controlled to be phase synchronized with the pilot signal.

Further, the sampling clock outputted from the VCO 14 is phase-shifted by a phase shifter 16 to an accurate re-sampling point of the image signal, and then inputted to an A/D converter 18 and a memory controller 17. The image signal digitized by 18 is stored in image memory 19.

Hereinafter, similarly, recording patterns B and C recorded on the video floppy shown in FIG.

The image signal is reproduced from the D track, stored in the image memory 19, a still image is reconstructed on the image memory as shown in FIG. A still image signal is formed on the image memory 19 which replaces the signal of the indicated pixel with an interpolation signal.

In this way, the still image signal formed on the image memory 19 is generated by changing the clock rate of the read clock output from the read clock generator 22 to, for example, HD (H
The digital still image signal stored in the image memory 19 is read out by the memory controller 17 in synchronization with the readout clock, and the digital still image signal is further read out in synchronization with the readout clock. By converting the digital still image signal into an analog signal using the A converter 20, a still image signal that can be displayed on an HDTV compatible monitor device is outputted from the output terminal 24.

By the way, P composed of the phase comparator 12 to frequency divider 15
When the LL circuit reproduces a video floppy with an empty track, no pilot signal is obtained even if the empty track is reproduced, so the phase synchronization state of the PLL circuit is disturbed.

In addition, in the reproducing apparatus shown in FIG.
(Radio Frequency) signal level is detected, and the tracking control circuit 36 controls the head feeding mechanism 4 so that the level of the RF signal detected by the RF signal detection circuit 35 is the highest, and the magnetic head or video It controls the tracks on the floppy to be accurately traced.

Therefore, in the reproducing apparatus shown in FIG. 6, the connection of the switch S2 is controlled based on the detection result of the RF signal detection circuit 35, and when the magnetic head comes into contact with an empty track on the video floppy, the RF signal is detected. If the detection circuit 35 detects that there is no RF multiplied signal at a predetermined level or higher in the signal reproduced from the magnetic head, the switch S2 is connected to the a side in the figure to keep the oscillation frequency of the VCO 14 constant. When a constant voltage output from constant voltage source 2 is supplied to the VCO 14 in the same way, and a magnetic head comes into contact with a recorded track on the video floppy, that is, RF@
When the signal detection circuit 35 detects that the RF multiplied signal is at a predetermined level or higher in the signal reproduced by the magnetic head, the switch S2 is connected to the a side in the figure.
The sampling clock phase synchronized with the pilot signal separated from the signal reproduced from the video floppy is V
It is output from CO14 and prevents the phase synchronization state in the PLL circuit from being disturbed.

[Problem B to be Solved by the Invention] However, in the playback device shown in FIG. Based on the four tracks recorded in accordance with the above-mentioned recording format for recording one screen worth of high-definition still image signals on a floppy disk, and the recording format of a conventional still video system, An inconvenience occurs when one track on which still image signals for one field (one frame) are recorded or two tracks on which still image signals for two fields (one frame) are recorded coexist.

For example, first, image signals are reproduced from four tracks on which high-definition image signals for one screen are recorded and stored in the image memory, and then the number of image signals recorded based on the conventional recording format is When playing back a track of a book and then playing back the image signal from the four tracks on which one screen worth of high-definition still image signals is recorded and storing it in the image memory, the RF signal detection circuit always detects the signal from the magnetic head. Since the presence of the RF signal in the reproduced signal is detected, the switch S2 continues to be connected to the a side. However, during the period in which image signals recorded in the conventional recording format are being played back on several tracks in the middle of playback of eight tracks on which high-definition still image signals for two screens are recorded, the image Since the pilot signal is not recorded along with the signal, it is no longer possible to obtain the pilot signal.

Therefore, even if the magnetic head comes into contact with the first track during playback of four tracks on which high-definition still image signals are recorded and a pilot signal is obtained, the PL
The L circuit has the disadvantage that it does not immediately synchronize in phase with the pilot signal separated from the reproduced signal, and cannot perform accurate storage operations in the image memory.

This invention was made to solve this problem, and includes a track in which a high-definition still image signal for one screen is recorded, and a track in which a still image signal for one field or one frame is recorded. It is an object of the present invention to provide an image signal reproducing device capable of accurately and stably reproducing any still image signal from a recording medium formed in a mixed manner such as tracks.

[Means for Solving the Problem] In order to achieve the above object, the image signal reproducing device of the present invention generates a first image signal to which a pilot signal is added and a second image to which the pilot signal is not added. A device for reproducing an image signal from a recording medium in which either one of the signals is recorded, comprising a storage means for storing a first image signal to be reproduced from the recording medium, and a storage means for reproducing the first image signal from the recording medium. storage synchronization signal forming means for forming a storage synchronization signal for storing a first image signal to be stored in the storage means; If the image signal to be reproduced from the recording medium is the first image signal, the pilot signal to which the first image signal C is added is supplied to the storage synchronization signal forming means, and the image signal is reproduced from the recording medium. and signal supply means for supplying a predetermined voltage signal to the storage synchronization signal forming means when the image signal to be generated is a second image signal.

[Operation] According to the present invention, depending on whether or not a pilot signal is added to the image signal reproduced from the recording medium, the image signal reproduced from the track on which one screen worth of high-definition still image signal is recorded is determined. , it is possible to accurately and stably reproduce any still image signal by determining whether it is a still image signal for one field or one frame or an image signal reproduced from a recorded track.

[Embodiment] FIG. 1 is a block diagram showing a schematic configuration of an image signal reproducing apparatus which is an embodiment of the present invention. Components that are the same or have the same functions as those in FIG. 6 are given the same numbers, and detailed explanations will be omitted.

In FIG. 1, 1 is a spindle motor for rotating a video floppy 2 at a predetermined rotational speed, 2 is a video floppy, 3-1.3-2 is a magnetic head, 4 is a head feeding mechanism, and s-i.

5-2 is a reproduction amplifier, 6 is an FM demodulation circuit, 7 is a de-emphasis circuit, 8 is a waveform generator for amplitude correction, phase correction, etc., 9 is a synchronization separation circuit, 10 is a pilot signal (19
5f H# 3.07 MHz: However, fH is a band pass filter (BP) for extracting horizontal scanning frequency).
F), 11 is an amplifier that amplifies the pilot signal separated by BPFl 0 to an appropriate level, and 12 is a phase comparator (PF) consisting of a multiplier, a low-pass filter (LPF), etc.
C), 13 is a roof filter that determines the loop characteristics of the PLL circuit, 14 is 6 f sc (21, 48 MHz
) generates a frequency signal in the vicinity of vco, is 177
A PLL loop is composed of a frequency divider that divides the frequency, that is, a phase comparator 12 to a 1/2 frequency divider 15. 16 is VCO14
17 is a memory controller, 18 is an A/D converter, and 19 is an image memory. , 2o is a D/A transformer, 21 is an interpolation processing circuit, 22
is a readout clock generator, 23 is a still image signal output terminal, 24 is a high-definition still image signal output terminal, 25 is a pilot signal detection circuit, 27 is a comparator, 28 is an ID signal detection circuit, and 29 is a skew compensation during field reproduction. %H delay line 30 is a system controller that controls the entire system.

Next, 4 tracks were recorded in accordance with a recording format that records high-definition still image signals for one screen on four tracks.
Based on the book track and the recording format of the conventional still video system, one track with one field's worth of still image signals recorded, or two fields (1 frame) of still image signals recorded. This section describes the playback operation of a video floppy that has two tracks mixed together.

Here, as shown in FIG. 2, on the video floppy 2, high-definition still image signals are recorded with pilot signals multiplexed on the first to fourth tracks and the eighth to 11th tracks in the figure. A still image signal for one field is on the fifth track, and a still image signal for one field is on the fifth track. It is assumed that a still image signal for one frame is recorded on the seventh track.

First, when the system controller 3o is instructed to play the first track by operating a track command switch (not shown), the system controller 30 outputs a track movement control signal to the head feeding mechanism 4, and the magnetic head 3-1 il) is controlled so that it is brought into contact with the rack.

At this time, depending on the RF signal level detected in the reproduced signal by the RF signal detection circuit (not shown), the magnetic head 3-1 is placed at the position where the RF signal is the largest by the ATF control circuit (also not shown). will be moved.

Also, at this time, switch 8 is connected to the a side. Since the pilot signal of 195fH is multiplexed and recorded on the first track, the pilot signal detection circuit 25
detects the amplified pilot signal of 195f,
A DC voltage corresponding to this detected pilot signal is output. As a result, when a voltage greater than the reference voltage v1, which is a threshold voltage, is input to the comparator 27, the comparator 27 outputs the control signal P and connects the switch s2 to the a side. Therefore, the PLL loop is closed, and the VCO 14 outputs a sampling clock 6 f sc whose phase is synchronized with the pilot signal. At this time, the control signal P from the comparator 27 is also input to the system controller 30C.
determines that the signal recorded on the track in contact with the magnetic head 3-1 is a high-definition still image signal, controls the memory controller 17, reproduces it from the first track, and
The image signal converted into a digital signal by the /D converter 18 is stored at a predetermined address on the image memory 19 designated by the memory controller 17. and,
When the storage of the image signal reproduced from the first track in the image memory 19 is completed, the switch S□ is kept connected to the side a in the figure, and the head feeding mechanism is moved so that the magnetic head 3-1 comes into contact with the second track. Control 4. Thereafter, the same operation is repeated until the image signal recorded on the fourth track is reproduced and stored in the image memory 19.

After the image signals reproduced from the first to fourth tracks have been stored in the image memory 19 as described above, the read clock generator 22 generates a read clock at a rate compatible with the HDTV system. The image signal stored in the image memory 19 is read by the memory controller 17 based on the readout clock, and further converted into an analog signal by the D/A converter 20, and outputted from the terminal 24 to an HDTV compatible monitor device, etc. .

Next, the magnetic head 31 is brought into contact with the fifth track on the video floppy 2 by the head feeding mechanism 4, and the image signal recorded on the fifth track is reproduced.

However, in this embodiment, it is detected whether or not a pilot signal is recorded together with an image signal on a track on the video floppy 2 that the magnetic head is in contact with. That is, B from the signal reproduced by the magnetic head.
A signal in the frequency band on which the pilot signal is multiplexed by PFlo is extracted, and the signal output from the BPFIO is amplified by the amplifier 11, and then the signal output from the amplifier 11 is compared with the reference voltage V in the comparator 27. , when the output signal of the amplifier 11 is smaller than the reference voltage vI, a low level detection signal P is output to the system controller 30, and the system controller 30 receives the detection signal supplied from the comparator 27. When P is at a high level, it is determined that a pilot signal is recorded along with an image signal on the track that the magnetic head is in contact with, and switch S2 is connected to all in the figure, and the detection signal P is at a low level. In this case, it is determined that the pilot signal is not recorded together with the image signal on the track that the magnetic head is in contact with, and the switch S2 is connected to the b side in the figure.

Therefore, when the signal reproduced from the fifth track on the video floppy 2 is supplied to the BPF 10 as described above, since the pilot signal is not recorded together with the image signal on the fifth track, the signal from the comparator 27 is The low level detection signal P is supplied to the system controller 30, and the switch S2 is connected to the b side in the figure.

The VCO 14 is approximately 6 f on the b side of the switch S2 in the figure.
V from a voltage source so as to generate a signal with a frequency of sc.
. Since a voltage of 6 f sc is being applied and the switch S2 is connected to the b side by the system controller 30 as described above, a signal with a frequency of 6 f sc is generated from the VCO 14.

As mentioned above, the fact that the pilot signal is not recorded along with the image signal on the track on the video disk 2 that the magnetic head is in contact with indicates that the level of the detection signal P output from the comparator 27 is low. is detected by the system controller 30, the system controller 3o determines that the fifth track is a still image recorded for one field or one frame based on the recording format of a conventional still video system, and further records the image. By decoding the ID signal recorded together with the signal, it is determined whether the still image signal for one field or one frame is recorded.

In the video floppy of this embodiment, field playback is performed to reproduce a still image using only the still image signal recorded on each track or the still image signal for one field recorded on that track. The still image signal for one field recorded on the track and the still image signal for one field recorded on the track adjacent to the track are used. The field/frame discrimination information for determining whether the data was recorded for frame playback to reproduce a still image is DPSK using a signal with a frequency (13fH) 13 times the horizontal synchronization frequency f as a carrier signal. (Different
ial Phase 5hift Keying) is modulated to form an ID signal and is recorded together with the image signal.The ID signal detection circuit 28 detects the ID signal from the signal reproduced by the magnetic head from the track on the video floppy 2. , and supplies field/frame discrimination information data to the system controller 30 by demodulating it.

Then, the system controller 30 decodes the field/frame discrimination information data supplied from the ID signal detection circuit 28, and when it is determined that field reproduction is to be performed, the switch S3 is switched between the a side and the b side in the figure for each l field period. %H delay line 29 by switching alternately.
By alternately outputting an image signal delayed by an H period and an image signal not delayed from the output terminal 23, a skew-compensated still image signal is output from the output terminal 23.

Furthermore, the magnetic head 3-1 is moved onto the sixth track on the video floppy 2 by the head feeding mechanism 4, and first, the presence or absence of a pilot signal is determined in the same manner as described above.

T! As shown in Figure s2, since no pilot signal is recorded on the sixth track, the system controller 30 connects the switch S2 to the b side in the figure.

Next, field/frame discrimination information data outputted from the ID signal detection circuit 28 in response to the ID signal multiplexed on the signal reproduced from the sixth track is decoded.

In this case, the system controller 30 determines that frame playback is to be performed by decoding the field/frame discrimination information data supplied from the ID signal detection circuit 28, and switches the switch S□ as shown in the figure for each field period. a
The switch S3 is connected to the b side in the figure, and the image signals recorded on the 6th and 7th tracks on the video floppy 2 are Frame reproduction is performed by alternately reproducing the frames, and the still image signal reproduced by the frame reproduction operation is output from the output terminal 23.

Next, the magnetic head 3-1 is controlled by the head feeding mechanism 4 so as to come into contact with the eighth track on the video floppy 2. In each of the 8th to 11th tracks, an image signal for forming a high-definition still image is recorded together with a pilot signal. ,
The same sequence as the reproduction operation of the first to fourth tracks described above is performed, and the switch S2 is switched from the b side to the a side in the figure, but before the switch S2 is switched to the a side, Since the VCO 14 generates a signal with a frequency of 6 f gc, which has almost the same frequency as the pilot signal, the switch S2 switches from the b side to the a side in the figure, and the VC
Even if the phase error voltage that is the output of the phase comparator 12 is supplied to O14, the PLL circuit quickly becomes phase locked.

FIG. 3 is a block diagram showing a schematic configuration of the main parts of an image signal reproducing apparatus as another embodiment of the present invention. In the embodiment described above, the voltage input to vCO is a constant voltage V when no pilot signal is detected from the signal reproduced from the video floppy. However, the configuration for controlling switching of switch S2 is changed to M3.
It may be configured as shown in the figure.

That is, in FIG. 3, the control voltage of the VCO 14 output from the loop filter 13 shown in FIG. 1 is supplied to the a terminal of the switch S2 and also to the A/D converter 31.

The A/D converter 31 converts the control voltage output from the loop filter 13 into a digital signal in synchronization with the clock signal output from the clock generator 34, and converts the control voltage output from the loop filter 13 into a digital signal.
(flip-flop) 32.

On the other hand, the D-FF 32 outputs the control voltage digitized by the A/D converter 31 from the clock generator 34,
The input is supplied to the D/A converter s33 in synchronization with the clock signal supplied via the switch S4, and the D/A converter 33
Then, the digital control voltage output from the D-FF 32 is converted into an analog signal in synchronization with the clock signal supplied from the clock generator 34, and is supplied to the b terminal of the switch s8.

The connection state of the switches S, , S, is controlled by a switch switching signal output from the system controller 30 shown in FIG. 1s1 in response to the detection of a pilot signal.

That is, when the system controller 30 determines that a pilot signal is recorded along with an image signal on the track that the magnetic head is in contact with in response to the detection signal P output from the comparator 27 in FIG. 1, the switch s is activated.
2 is connected to the a side in the figure, and the switch s4 is turned on, and a control voltage of the same potential is applied to both the a terminal and the b terminal of the switch S2, and the system controller 30M1! When it is determined that the pilot signal is not recorded along with the image signal on the track that the i-type head is in contact with, the D-FF3 is connected by connecting the switch s2 to the b side in the figure and turning the switch s4 off.
2, the supply of the clock signal output from the clock generator 34 is interrupted, so the connection to the b terminal of the switch s2 is changed from the a terminal to the b terminal immediately before the connection of the switch s2 is switched from the a terminal to the b terminal.
The potential of the control voltage supplied to the a terminal from the loop filter 13 is held, and the same effect as the configuration shown in FIG. 1 can be achieved.

As explained above, in this embodiment, it is detected whether or not a pilot signal is frequency multiplexed on an image signal recorded on a video floppy C, and when the reproduced image signal is digitized and stored in the image memory. When the pilot signal is multiplexed, a control voltage corresponding to the phase error between the reference signal and the pilot signal is applied to the VCO in the PLL that forms the sampling clock used for the By applying a constant voltage to the video floppy, the still image signal can be stored on a video floppy disk, which has a mix of tracks on which high-definition still image signals are recorded and tracks on which still image signals are recorded based on the conventional recording format. When reproducing sequentially, the response of phase synchronization in the PLL loop is improved, and smooth reproduction can be performed.

[Effects of the Invention] As explained above, according to the present invention, there is a track in which a high-definition still image signal for one screen is recorded, and a still image signal for one minute or one frame is recorded. It becomes possible to provide an image signal reproducing device that can accurately and stably reproduce any still image signal from a recording medium formed in a mixed manner such as tracks.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image signal reproducing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the operation of the reproducing device shown in FIG. 1. FIG. 3 is a block diagram showing a schematic configuration of the main parts of an image signal reproducing device as another embodiment of the present invention, and FIG. Figure 5 is a diagram showing the arrangement of sample pixels of two CCDs arranged with a % pixel shift in the direction. FIG. 6 is a block diagram showing the schematic configuration of a conventional image signal reproducing device; FIG. 7 is a diagram showing the arrangement of pixels reconstructed on the memory. . In the figure. 2: Video floppy 3-1.3-2: Magnetic head 4: Head feeding mechanism 10: BPF 11: Amplifier 12: Phase comparator 13: Loop filter 14: VCO 18, 31: A/D converter 19: Image memory 20, 33: D/A converter 25, pilot signal detection circuit 27: comparator 28: ID signal detection circuit 30, system controller 32: D-FF

Claims (1)

[Claims] Among the first image signal to which a pilot signal is added and the second image signal to which the pilot signal is not added,
A device for reproducing an image signal from a recording medium in which one of the two is recorded, comprising a storage means for storing a first image signal reproduced from the recording medium, and a first image reproduced from the recording medium. storage synchronization signal forming means for forming a storage synchronization signal for storing a signal in the storage means; determining whether the image signal reproduced from the recording medium is the first image signal or the second image signal; When the image signal to be reproduced from the medium is the first image signal, the pilot signal added to the first image signal is supplied to the storage synchronization signal forming means, and the image signal to be reproduced from the recording medium is An image signal reproducing device comprising: signal supply means for supplying a predetermined voltage signal to the storage synchronization signal forming means in the case of a second image signal.