JPH03254573A - Encoding device for color picture - Google Patents

Abstract

PURPOSE:To attain the effective encoding of a color picture by encoding a multilevel color signal within a multivalued color picture area and a binary color signal outside of the multivalued color picture area separately and generating the position of the multivalued color picture area and a signal to indicate size. CONSTITUTION:A mask generator 28 outputs a mask signal 109 to execute the masking of binarizing processing by a binarizing circuit 21 to the area of an area multivalued color picture designated by an area designating signal 108 from an area designating part 19 to designate a multivalued color area at an area designating mode. For the binarizing processing, the second binarizing processing to encode and to transmit a multivalued color signal within the area designated as the multivalued color picture area by the area designating part 108 in the contents of a difference memory 24 with using an encoder B 26 is executed. Then, after that, the first encoding processing to encode and to transmit a binary color signal of the outside of the multivalued color picture area in the contents of a binary memory 22 with using an encoder A 25.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a color image encoding device for a color facsimile device or the like that communicates color images.

[Conventional technology]

Various proposals have been made regarding color still image encoding systems. Furthermore, the target color still images can be roughly divided into the following two types.

(1) Red, green, blue, cyan, magenta, yellow, white, black 8
Binary color image (2) where colors are treated as binary values (2) Red, green, and blue each have 1670 gradations with 256 gradations, for example.
As a multi-valued color image binary color image encoding method for displaying a million colors, a method using a modified Huffman method, which is a variable length encoding method currently used in facsimiles and the like, for each color has been considered. As another method, a predictive encoding method has been proposed in which a coded pixel is predicted from surrounding pixels. These methods fall under the category of lossless encoding, and data is preserved during encoding and decoding.

On the other hand, as a multi-value color image encoding method, 8 each of RGB
A method has been proposed in which after converting a bit signal into a luminance/chrominance signal, linear quantization is performed on coefficient values subjected to orthogonal transformation (ll! dispersion cosine transformation), and variable length encoding is performed on the quantized values. This method basically reduces image data by leaving the low frequency side of the spatial frequency of the image and cutting the high frequency side. This method is a lossy encoding method,
There is a trade-off between compression rate and image quality deterioration.

[Problem that the invention (device) is trying to solve] However,
A case where a color document image in which a color photograph is embedded in a color text is encoded using the above conventional example.

(1) In the binary power system, even if a color text image part can be encoded with a high compression rate, it is not possible to efficiently encode an image with gradation in a color photograph part.

(2) In the multilevel color one-sided method, as the compression rate is increased, the high frequency components of the image are largely cut off, and the deterioration of the image quality at the edges of characters etc. becomes noticeable. You cannot expect a high compression ratio.

There are problems such as:

Therefore, in a color still image transmission apparatus, in order to encode an image with a high voltage N rate and with little deterioration, it is necessary to prepare two types of encoders.

However, when performing these two types of encoding,
Encoding target regions may overlap.

For example, as shown in FIG. 18, when a color document image includes a color photographic image (multi-valued color image), a method is to encode the entire image using a binary color image encoder and then encode the multi-valued color image area. If this is done, there is a problem that the binary code word for the multi-level region becomes a redundant code.

[Means to solve the problem]

The present invention has been made in view of the above points, and an object of the present invention is to make it possible to efficiently encode a color image in which a binary color image and a multivalued color image are mixed. The first step is to encode a multivalued color signal within the region.
encoding means; 's2 encoding means for encoding a binary color signal outside the multivalued color image area in the color image;
and generating means for generating an area signal indicating the position and size of a multivalued color image area in the color image.

〔Example〕

The present invention will be explained below using preferred embodiments.

〔Example〕

FIG. 1 shows an embodiment of the configuration of a code section to which the present invention is applied.

In the image memory 20, red (R) and green (G) representing a full-color image manually input from a color still image input means such as a color scanner (not shown) are stored.

Blue (B) color image signals of 8 bits each are stored.

The image signal 100 of each color read out from the image memory 20 is subjected to binarization processing for each color in a binarization circuit 21, and is converted into R,
2 of 1 bit each for G and B (after being converted to 1 color signal,
Each color is stored in the binary memory 22. Binary memory 22
The binary color signal 103 read out is encoded by the encoder A for binary color signal encoding, and the code word 105 is
Output. This encoding process by encoder A is the first encoding process.

The same color image signal that has been subjected to the first encoding process described above is read out from the image memory 20. The subtracter 23 receives R, G, and B 8-bit signals 100 and 2 from the image memory 20.
A signal (0-0, 1→255) 102 obtained by level-converting the output from the value memory 22 into an 8-bit signal is manually input, and a signal 100 is subtracted from the signal 102 for each color. This difference signal 104 is stored in the difference memory 24 for each color. ,
The multi-value color signal 110 in the difference memory 24 is encoded by an encoder B for multi-value color signal encoding, and the code word 106 is
Output. The above encoding process by encoder B is 's2
This is the encoding process.

As shown in Table 5, the mode setting section 29 sends the control signal 107 according to the encoding mode to the mask signal generator 2.
8 and the encoder 27, and control them as follows.

(1) In the binary mode, the entire region is subjected to the binarization process by the binarization circuit 21, and only the first encoding process by the encoder A25 is executed.

(2) In the multilevel mode, the mask generator 28 generates a mask signal for the entire area so that the binarization circuit 21 does not perform the binarization process, and the contents of the binary memory 22 are all zero. Make it so. Further, as for the encoding process, only the second encoding process by the encoder B is executed.

(3) In the area specification mode, the binarization circuit 2
The mask generator 28 outputs a mask signal 109 so as to mask the binarization process by 1. 'Jgl Figure 5 is a diagram showing mask areas in the area specification mode, where area A2001 and area B200 out of the entire image area 2000 are
2, it is shown that masking of the binarization process is performed.

The area specifying unit 19 may automatically determine the multilevel color image area by monitoring the color image and output the area specifying signal 108, or may output the signal 108 according to manual area specification using a keyboard, digitizer, etc. You can also output it.

In addition, in the first step, the encoding process in the area specification mode uses the encoder B 26 to generate a multi-value color signal within the area specified as a multi-value color image area by the area specification unit 108 among the contents of the nutrient memory 24. Then, in the second stage, the encoder A25 is used to encode the binary color signal outside the multilevel color image area among the contents of the binary memory 22. A first encoding process is carried out for digitized transmission.

That is, as shown in FIG. 17, when executing the second encoding process in the first stage, one screen OG of FIG.
The multi-value color signal in the middle multi-value color image area CA (first
7(b)) is read out from the differential memory 24 and encoded. Furthermore, when executing the first encoding process in the second stage, the multi-valued color image 9r is
The binary color signal outside the i-area CA (FIG. 17(C)) is read out from the binary memory 22 and encoded.

Further, as shown in FIG. 3417(b), an area designation signal 191, which is a signal indicating the position and size of the multivalued color image area CA, is transmitted to the receiving side before the first stage encoded data is transmitted. During decoding, this area designation signal 191
The decoded multi-valued color image and binary color image are combined based on the above.

(4) When in automatic mode, the entire area is binarized by the binarization circuit 21, the binarization result is stored in the binary memory 22,
A first encoding process is performed by the encoder A25, and a binary color still image is encoded and transmitted. Next, the subtractor 23
The difference image 110 obtained by subtracting the original image from the level-converted binary image obtained by the above is subjected to the encoding process 's2 using the encoder B26, and is encoded and transmitted.

FIG. 16 shows line data 2 read out from the image memory 20.
03 is binarized by a threshold Th206 in the binarization circuit 21, and the level-converted signal 204. A difference signal 205 obtained by subtracting the signal 203 from the signal 204 is also shown. In this way, the subtracter 23 removes line signals (or edge signals) from the multivalued color image.

FIG. 2 is a block diagram of the binarization circuit 21.

The comparator 40 uses the threshold value Th206 and the original image signal D10.
0 is compared, and if D≧Th, the signal 113 is set to 1; otherwise, the signal 113 is set to 0. In addition, the gate circuit 41
forces signal 101 to turn O when the mask signal is true.
otherwise, the input signal 113 is passed.

In this embodiment, binarization was simply performed using comparative amounts, but the binarization process is not limited to this.

FIG. 3 shows the configuration of an embodiment of a decoding section that is compatible with the present invention.

The code word 106 of the multi-value color image is restored to multi-value image data for each color by the decoder B31 and stored in the difference memory 34. The data stored in the difference memory 34 corresponds to the difference signal in the multivalued color image area stored in the difference memory 24 shown in the first diagram. Furthermore, the storage area is specified by an area designation signal 19.
1 based on the area signal 3 from the composite instruction signal generator 37.
8.

Further, the code word 105 of the binary color image is restored to a dot image for each color by the decoder A30 and stored in the binary memory 33. This dot image, which is also determined by the area signal 38, corresponds to a binary signal outside the multilevel color image area stored in the binary memory 22 shown in the first figure.

In the synthesizer 35, according to the area signal 38, the binary memory 3
The level-converted image of the 1-bit RGB signals 113 from 3 and the difference signal 114 from the difference memory 34 are combined,
A signal 115 is obtained and stored in the image memory D36.

Image combination in synthesizer 35 or subtracter 23 shown in the first diagram
In other words, ′! Signal 204 to signal 2 in diagram J16
05 to obtain the original signal 203.

Note that in this embodiment, the encoding and transmission of a multivalued color image is performed in two ways.
Although the process is performed prior to encoding and transmitting a value color image, the order is not limited to this, and the multivalue color image may be transmitted after encoding and transmitting a binary color image.

FIG. 4 is a block diagram of the encoder 27 shown in FIG.

The binary color encoder A25 is composed of a prediction state circuit A50, a delay circuit A51, and a dynamic encoder 53.
Selector 52 operated by control signal 107
．． 54 switches the human output. Further, the multi-value color encoder B26 includes a color conversion circuit 55, an orthogonal conversion circuit 56,
, a linear quantizer 57, first to sixty-fourth page memories 58-1 to 58-64, a selector 59, a predicted state determination circuit B60, a delay circuit B61, and a dynamic encoder 53, and an encoder A25. Similarly, the input and output are switched by selectors 52 and 54 operated by the control signal 107.

Here, the dynamic encoder 53, which is the central part of the encoder 27, is shared by encoders A and B, and the hardware configuration can be simplified in this part. Below encoder A,
The processing of encoder B will be explained step by step.

First, encoder A will be explained.

The output 103 from the binary memory 22 is the predicted state circuit A50.
to go into. Regarding the pixel of interest, the prediction state circuit A50 generates a prediction state signal S, 11 composed of the surrounding coded pixels.
Outputs 4. Further, the delay circuit A51 outputs a 1-bit pixel signal X, 115 synchronized with the predicted state signal S, and both signals S, 114, X, 115 are input to the selector 52 manually.

FIG. 5 is a block diagram of the predicted state determination circuit A50,
FIG. 6 shows pixel positions for each color that are referred to for state prediction.

That is, FIG. 6(a) shows the reference pixel of the first color of encoding 'fjS (R in this example), and it is possible to refer to the seven encoded pixels around the encoded pixel indicated by *. It represents.

In addition, FIG. 6(b) shows the encoded second color (G in this example).
), which indicates that a total of eight pixels are referred to, including the same seven pixels as in (a) and the same position pixel of the first color.

In addition, FIG. 6(C) shows reference pixels of the third color (B in this example), including the same seven pixels as in FIG. 6(a) and each pixel at the same position of the first color and the This indicates that a total of nine pixels are referred to.

In the configuration shown in FIG. 5, the state of each color is determined by referring to a plurality of pixels at reference pixel positions for each color shown in FIGS. 1iS6 (a) to (c). The operation shown in FIG. 5 will be explained below.

The signal 103, which is a 3-bit signal consisting of 1 bit each for R, G, and B, is input to the latch groups 67 to 69 as RGB data 200 to 202, and is also input to the line memory 61.
．． 62 and 63, and RGB data delayed by one line is held by line memories 61 to 63. Furthermore, data delayed for each pixel clock is held in the latches 67a to 67h, latches 68a to 68h, and latches 69a to 69h.

In the latch group 67, the output of the line memory 61 is input to latches 67a, 67b, and 67c.

67d and the output of the line memory 61, data of five pixels on the previous line of the encoding line can be referenced. Furthermore, the two encoded pixels on the encoding line can be referenced by the outputs of the latches 67g and 67h. The data of these seven pixels are combined and used as a reference pixel position 210 for determining the state of R, which is the first color to be encoded. Further, from the latch 67f, the R data 211 of the encoded pixel is transmitted to other colors G,
It is output for determining the state of B.

Latch groups 68 and 69 having the same configuration as this latch group 67 are provided for data G201 and B2O2, and from these latch groups 68 and 69, seven pixel data similar to that of the latch group 67 are provided as reference pixel signals. 212 and 214.

Furthermore, the G data 213 of the encoded pixel is output from the latch 68f in the latch group 68 for determining the B state.

The selector 64 switches the reference pixel signal in response to a 2-bit color instruction signal 219 indicating the color corresponding to the output of each RGB color data. That is, color instruction signal 2
When 19 is R, reference pixel signal 210 and zero signal 2 bits
Select. Further, in the case of G, the reference pixel signal 212, the R signal 212, and 1 bit of the zero signal are selected. Also, B
At this time, the reference pixel signal 214, R signal 211, and G signal 213 are selected. The 9-bit selection signal 215 and the 2-bit color instruction signal 219 are sent to the backing circuit 65.
As a result, the state signal S+ is summarized into a 1-bit signal.
It becomes 206. Therefore, the state signal S1 indicates the color of the pixel to be encoded and the surrounding state, and indicates 27.2829 states for each of R, R, and B colors.

Next, the encoder B shown in FIG. 4 will be explained.

341 Image signal 1 read out from the nutrient memory 24 shown in FIG.
10 is color conversion I! 55, brightness and
The signal is converted into a color difference signal 400. The following formula is generally used for this conversion.

Y: 0.299R: 0.587G 100, 114 B Cr=0.713 (RY) Cb=0.564 (B-Y) However, R, G, B, Y, and Cr shown here.

cb is a standardized value.

Next, the orthogonal transform circuit 56 performs a discrete cosine transform to obtain 8×
The image of each 8-pixel block is converted into a conversion coefficient (intensity) for each frequency. The conversion coefficient shown in the $13 diagram is still 8
It is made up of ×8 blocks, and the converted values are numbered from 1 to 64. Coefficient number 1 indicated by 500 indicates the DC component. In addition, the coefficient number 2.3 indicated by 501.502
... indicates an alternating current component, and as the number increases, it indicates an alternating current component from low frequency to high frequency.

The transform coefficient signal 401 is quantized to, for example, 8 bits by a linear quantizer 57. In this linear quantizer 57, the quantization steps are determined so that the quantization steps for direct current and low frequencies are fine, and the quantization steps for high frequencies are coarse. The 64 quantized values constituting the 8×8 block described above are stored in 64 first to 64th page memories 58-1.
~58-64, respectively. That is, the first page memory 58-1 stores the quantized value of the DC component corresponding to coefficient number 1 of the 8×8 block, and the 64th page memory 58-64 stores the coefficient of the 8×8 block. The quantized value of the maximum high frequency AC component corresponding to number 64 is stored.

Therefore, each page memory 58-1 to 58-64 has 1
Quantized values at the same position of a plurality of 8×8 blocks constituting the screen of the page are stored.

The data of the first to 64th page memories 58-1 to 58-64 are inputted to the predicted state determining circuit B60 and the delay circuit B81 through the selector 59. The method of sending this data is
After sending out all the contents of the first page memory 58-1, the data of the second page memory 58-2 is sent out, and this is done for each page memory in order.
The contents of the page memory 58-64 are sent out. This is a switching signal 4 output from a central controller (not shown).
This is done by switching and controlling the selector 59 using 06.

! FIG. 13 shows a block diagram of the predicted state determination circuit Boo. Basically, the method is similar to the reference method shown in FIG. Encoding starts from the most significant bit brane, and the nbit-th brane refers to the pixels of the first to n1-th bit branes that have already been encoded. Further, the n-th bit brain refers to the surrounding 7 bits that have already been encoded.

FIG. 14 shows pixel positions for each bit referenced for state prediction.

That is, FIG. 14(a) shows the encoded first bit D+(MS
The reference pixel in B) is shown, and indicates that seven encoded pixels around the encoded pixel indicated by * are referred to.

In addition, FIG. 14(b) shows reference pixels for the second encoded bit D2, and a total of 8 pixels are referred to, including the same 7 pixels as in FIG. 14(a) and the pixel at the same position of 1 bit. It represents.

In addition, FIG. 14(C) shows the reference pixels for the third bit, including the same seven pixels as in FIG. It means to refer to.

Also, Figure 14(d) shows the 8th row.

(LSB) reference pixels are shown, and the same 7 as in (a) is shown.
This indicates that a total of 14 pixels are referred to, including the pixel and each pixel at the same position of the first to seventh bits.

In the configuration shown in FIG. 13, the state of each bit brain is determined by referring to a plurality of pixels at reference pixel positions for each bit shown in FIGS. 14(a) to 14(d). The operation shown in FIG. 13 will be explained below. Note that in FIG. 13, circuits related to the fourth to sixth bits are omitted to avoid complicating the drawing.

The signal 110, which is an 8-bit signal, is input to the latch groups 521-528 as each bit brain data 501-508, and is also input to the line memories 511-518, and each bit is delayed by one line by the line memories 511-518. Brain data is retained. Furthermore, the latch groups 521 to 528C are the latch groups 67 to 67 shown in FIG.
Similarly to 69, data delayed for each pixel clock is held.

In the latch group 52, the output of the line memory 511 is manually input to four latches, and the output of the line memory 511 makes it possible to refer to the data of five pixels on the previous line of the encoding line. Furthermore, the outputs of the latter two latches of the four latches into which the data 501 is directly input allow reference to the two encoded pixels on the encoding line. The data of these seven pixels are combined to form a reference pixel signal 5 for determining the state of data D1, which is the first encoded bit.
51. Furthermore, the latch group 521 outputs data 561 of encoded pixels for determining the state of other bit brains.

A latch group 522.52 having the same configuration as this latch group 521
3 to 527.528 are data D2゜D, ~D, and D8
These latch groups 522 to 52
From 8 onwards, data of 7 pixels similar to the latch group 521 are reference pixel signals 561.562, 563 to 557.55, respectively.
Output as 8.

Furthermore, the data 5 of encoded pixel D2 is received from the latch group 522.
62 is output for determining the state of each of the 3rd bit to 8th bit plane.

In the selector 530, the reference pixel signal is switched in accordance with a 3-bit bit instruction signal 570 indicating a bit corresponding to the output of data for each bit plane. That is, when the bit instruction signal 570 is the first bit D, the reference pixel signal 551 and the zero signal 7 bits are selected. *Ta, second
When bit D, reference pixel signal 552 and DI signal 5
61 and zero signal 6 bits are selected. Further, when the eighth bit is D, the reference pixel signal 558 and the signal 561,
D2 signal 562, D3 signal 563~D.

Signal 567 is selected. This 14-bit selection signal 2
The 15 and 3-bit color instruction signal 219 are combined into a 17-bit signal by a backing circuit 540 to become a status signal 52404. Therefore, the state signal S2 indicates the bit plane and surrounding state of the pixel to be coded.

This output signal 52404 is input to the selector 52 shown in YS4. Furthermore, the delay circuit B61 outputs the output signal X2405.
is synchronized with the reference signal S2.

The above signals St, X+ and S2. Control signal 107 outputted from a central controller (not shown)
4: Accordingly, the operating selector 52 causes the signal 5116,
Select as x117.

Further, this signal is encoded by a dynamic encoder 53, and the signal 11 is encoded by a dynamic encoder 53.
8 is switched by a selector 54 operating in accordance with a control signal 107 and output as a code word 106.

'i47 diagram is'! FIG. 9 is a block diagram of a dynamic code 953 illustrated in J4.

Before explaining FIG. 7, the arithmetic codes used in this embodiment will be explained.

As is conventionally known, arithmetic coding is a method in which a code is formed by arithmetic operations so that an input signal string becomes a code expressed in binary decimal numbers. This method uses Lang
The document by Don and R15sanen et al.
color of Black/White I
magesWith Arithmetic Co
d i ng , IEEE Tran Com
, COM-29, 6, (1981, 6), etc. According to this document, S is the manually encoded signal sequence, q is the probability of a less-common symbol (LPS), A(S) is the arithmetic register Augena, and C(S) is the code register.
), perform the following arithmetic operations for each input signal.

A (Sl)=A (S)XQ thPA (S)X2-Q...(1)
A (So) = <A (S) - A (31)> t・
...(2) <>7 is C(S
o)=C(S)...(3)C(Sl)
=C(S)+A(So)−” (4) Here, if the encoded data is the dominant symbol (O in the example above MPSz), A (50), C(SO) is the encoding of the next data. In the case of the inferior symbol (LPS: 1 in the above example), A(31) is used.

C(Sl) is used to encode the next data.

The new value of A is multiplied by 2s (S is an integer greater than or equal to 0), and 0.
It falls within the range of 5≦A<1.0.

This processing corresponds to shifting the calculation register A five times in hardware. The code register C is also shifted the same number of times, and a code is formed by repeating the process of 0 or more in which the shifted out signal becomes a code.

Further, as shown in equation (1), the occurrence probability q of LPS is approximated by a power of 2 (2-': Q is a positive integer), thereby replacing the multiplication calculation with a shift calculation. In order to further improve this approximation, q is approximated by a polynomial of a power of 2, such as equation (5). This approximation improves the worst point of efficiency.

q42-"+2-Q2".(s) Furthermore, since the arithmetic code allows the value of Q to be switched for each encoded data, the probability estimation section can be separated from the encoding.

In this embodiment, as described above, a dynamic method is used in which the probability is estimated while performing encoding.

A block diagram of the encoder 53 shown in FIG. 7 that performs the above arithmetic coding will be explained.

′! A status signal 5116 from the selector 52 shown in FIG. J4 is input to the counter memory 73 and the encoding condition memory 74.

The encoding condition memory 74 stores, for each state represented by the state signal 5116, a dominant symbol MPS 308, which is a symbol that is likely to appear, and an index 1307 indicating the encoding condition including the probability of occurrence of an LPS of an arithmetic code, which will be described later. has been done. The MPS 308 read out from the encoding condition memory 74 according to the color and state of the image to be encoded is input to the predictive conversion circuit 77, and the predictive conversion circuit 77 receives the serial pixel signal X117 from the selector 52 shown in FIG.
YN signal 301 which becomes O when matches MPS308
make. The YN signal 301 is input to the update circuit 75, and the update circuit 75 increments the count of the corresponding state among the count values stored in the counter memory 73 when the YN signal is 0. If the count value 0306 stored in the counter memory 73 matches the set value MC305 from the count table ROM 72, the index 1307 increases in the direction (LP
update in the direction in which the appearance probability q of S becomes smaller). (MP
S is not inverted. ) In addition, count table ROM7
2 is the number MC3 of MPS shown in Table 1, which is determined corresponding to the index I representing the probability q of appearance of LPS.
05 is supplied to the update circuit 75.

Also, in the update circuit 75, the MP5308 and the pixel signal x1
17 does not match, that is, Y from the prediction conversion circuit 77
When the N signal is 1, the index l307 is updated in a direction that decreases (in a direction that increases the LPS appearance probability q). Furthermore, when a YN signal with a value of 0 comes when the index is 1, processing is performed to invert the MPS (O-1 or 1-O).

Outputs I' 309 and MPS' 310 of the update circuit 75 are updated index values, and are stored in the encoding condition memory 74.
will be re-memorized.

In the encoding parameter determination circuit 76, the index 13
Coding parameter Q31 of arithmetic code based on the value of 07
1 is set in the arithmetic encoder 78. This arithmetic encoder 78
Then, the YN signal 301 from the predictive conversion circuit 77 is arithmetic encoded using the parameter Q311 to obtain a code 302.

Note that an initial value is given to the encoding condition memory 74, and 1.
By not updating the MPS, static encoding can be easily achieved.

FIG. 8 is a block diagram of the predictive conversion circuit 77. Serial pixel signal X117 and MPS308 are connected to EX-OR circuit 7
When the serial pixel signal X115 and the MPS 308 match, the YN signal 301 becomes 01 when the serial pixel signal X115 and the MPS 308 match, and becomes 1 when the serial pixel signal X115 and the MPS 308 do not match.

FIG. 9 is a block diagram of the update circuit 75.

When the YN signal 301 is 0, the count value C306 from the counter memory 73 is incremented by +1 by the adder 81 and becomes the signal C'312. This value is compared with MC305 from count table ROM72 by comparator 83,
If the value of C' matches the value of MC, the update signal UPA
Set 313 to 1. Further, the YN signal 301 becomes an update signal UPB 314, and UPA and UPB enter the index change circuit 85. Further, UPA and UPB are logically ORed by an OR circuit 87, and the output signal 31 of the OR circuit 87 is
5 is a switching signal for the selector 82. selector 82
Then, when the signal 315 is 1, select the O signal 319 to reset the value of the counter memory 73, otherwise select the output signal C'312 of the adder 81, and select the counter update signal C.
"316" and stores this in the counter memory 73. Therefore, the serial pixel signal X115 and MPS
If 308 does not match, or if the matching state continues a predetermined number of times, the count value of the counter memory 73 is reset.

The index change circuit 85 has signals d317 (standardly d=1) that control the index update increments and U
PA313, UPB314 and encoding condition memory 74
Since then, the current index ■307 has been manually created.

's3 table is a table showing the index update method in the index change circuit 85 (Table 3 shows cases where the update increments are d=1 and d-2). Increment condition d%UP
The updated index I' is determined by referring to A%UPB. Further, when I-1 is UPB-1 (when the serial pixel signal X115 and MPS308 do not match), the EX signal 318 is set. When the EX signal 318 is 1, the inverter 86 inverts the symbol of the current MP 3308 (0-1 or 1-0) to obtain an updated MPS' 310. Furthermore, when the EX signal is 0 (7), MPS' is not changed. The updated I' 309 and MPS' 310 are stored in the encoding condition memory 74 and used as the index I and MPS for the next processing. Note that the updating method shown in Table 343 can be configured as a table using a ROM or the like, or it can also be configured as a logic using an adder/subtractor.

As described above, when MPSs for the number of MPSs determined according to the value of the index I representing the appearance probability q of an LPS approximated by a polynomial of a power of 2 are generated, d is added to the index I and the arithmetic code is The appearance probability q of the LPS used is made small, and on the other hand, when an LPS occurs,
The index ■ is subtracted by d to increase the appearance probability q of LPS used for arithmetic codes. Furthermore, the appearance of LPS N11q is 0.5! a (index ■ is 1
If LPS occurs in the state), MPS is inverted.

In this way, the index I and MP are adaptively applied to the input image.
By updating S, arithmetic coding with high coding efficiency can be achieved.

FIG. 10 is a coding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of index I is indicated by lowercase i,
This curve is expressed by equation (6) when the LPS appearance probability is q and the approximate probability at the time of encoding is 91 dishes. And LP
S is sure to appear! Indexes I are sequentially assigned as 1, 2, 3, etc. from the larger value of q to the smaller value of q.

η 8 ... (6) Here, the numerator is entropy, and Qs+&f formula (7)
This is the value shown by .

q・mu”Q+ +Q2 ...(7)Q
The value of 1%Q2 is a polynomial approximation value of a power of 2 and is given in Table 4. For example, it is shown by (8) to (10).

Qe+ =2-'...(8)
QII2'-2-'2-' ・・・
(9) 9.3' Tomi 2-'+2-' -...
(1o), and the peak point ql at which the efficiency η becomes 1.0 in this probability is hereinafter referred to as the effective probability.The intersection of the efficiency curves is also referred to as the boundary probability Qb+, and the effective probability of the neighbor is calculated using this probability as the boundary. It is clear that the efficiency is improved by encoding using

In this embodiment, the effective probabilities q and 5 shown in Table 4 are selected from the probabilities that can be approximated by two terms as shown in equation (5). Furthermore, Q+, Q2, and Q3 in Table 4 are parameters Qe311 sent to the arithmetic encoder 78. That is, Ql,
Q2 is the shift amount given to the shift register, and a power of 2 calculation is performed by this shift operation. Also, Q
.

indicates the coefficient of the second term, and switches between + and -.

The values of MC in Table 1 are determined as follows.

That is, when the number of LPS is N, and the number of MPS is N,
The probability of LPS occurrence is given by equation (11).

Solving this equation using NM gives equation (12).

NM=NL (1/q-1)J...(12
) However, XJ is the formula 6 (
By giving q shown in FIG. 10 to q in 12), the number N of dominant symbols (M P S ) there
MI is calculated. Therefore, it is calculated from the MC wave equation (13).

MCi Tomin□II-NMI...(13)
3@1 The value of MC in the table is expressed by formulas (11), (12), (13)
It is calculated using NL=2.

In this way, the number N of dominant symbols MPS corresponding to each index I is calculated based on each boundary probability Qb+ as shown in FIG. MC for

Then, the value of Me and the number of generated dominant symbols MPS are compared as described above, and the value of MC and the number of dominant symbols MPS are
If the numbers match, it is determined that the state has passed the encoding using the adjacent index I, and the index I is changed. As a result, the index I is changed at a good timing based on the number of occurrences of the dominant symbol MPS, and encoding using the optimum index I can be adaptively achieved.

FIG. 11 is a block diagram of arithmetic encoder 78.

Of the control signals Q311 (Table 4) determined by the code parameter determination circuit 76, Ql is input to the shift register A90, Q2 to the shift register B91, and Q3 to the selector 92.

Q+ and Qz are Aug for shift registers A and B, respectively.
Instructs how many bits to shift the end signal A, 323 to the right. The shifted result is the output signal 330.3
It will be 31.

The signal 331 is complemented by the inverter 96, and the selector 92 selects the signal 331 or the output signal of the inverter 96 using the control signal Q to obtain an output signal 332.

Adder 93 receives signal 330 from shift register A90.
and the signal 332 from the selector 92 are added, and AS
An I signal 324 is output. The subtracter 94 subtracts the ASI signal 324 from the AS multiplied signal 23 to obtain the Aso signal 32.
Get 5. In the selector 95, AB6 signal 325 and Ag1
One of the signals 324 is selected by the YN signal 301. That is, when the YN signal is 1, the Aa16 signal is
When the signal is 0, the Ai+ signal becomes the A' signal 326. In the shift circuit 89, processing is performed to shift the A' times signal MSB to the left until it becomes 1, and as a result of this shift, an As' signal 327 is obtained. The shift signal 332 corresponding to the number of shifts is entered into the code register 99, and from the code register 99, bits corresponding to the number of shifts are MS.
The code data 330 is output in order starting from B.

The code data 330 is processed using a bit processing method (not shown).
The bttt sequence is processed to be within a finite number, and is transmitted to the decoding@14 side.

Further, the content CR32B of the code register 99 is stored in the adder 9
7, it is added to the Aso signal 325 and enters the selector 98. In addition, the unadded signal C of As0 325
R328 also enters the selector 98, and when the YN signal 301 is 1, CR' = when the CRYN signal is O, CR' = CR+
It is output as a CR' signal 329 which becomes Aso. The shift processing described above regarding code register 99 is also performed on the CR' signal.

Table 1 Table 4 Table 3 (-) indicates don'. Binary color signals outside the color image area are encoded separately, and signals indicating the position and size of the multi-value color image area are generated, so it is possible to encode the multi-value color signal and the binary color signal. This makes it possible to efficiently encode color images.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the configuration of the encoding unit to which the present invention is applied, Fig. 2 is a block diagram of the binarization circuit, Fig. 3 is a diagram showing an example of the configuration of the decoding unit, and Fig. 4 is a diagram of the encoder. Block diagram: FIG. 5 is a block diagram of the prediction state determination circuit A; FIG. 6 is a diagram showing reference pixel positions; FIG. 7 is a block diagram of the dynamic encoder; FIG. 8 is a block diagram of the prediction conversion circuit; Figure 9 is a block diagram of the update circuit, Figure 10 is a diagram showing a coding efficiency curve, Figure 11 is a block diagram of an arithmetic encoder, Figure 12 is a diagram showing transform coefficients, and Figure 13 is a diagram showing prediction state determination. A block diagram of circuit B. FIG. 14 is a diagram showing reference pixel positions, FIG. 15 is a diagram showing an example of area specification, FIG. 16 is a diagram showing an example of subtracter operation, and FIG. 17 is a diagram showing encoding operation. Figure 18 shows an example of a color document. 20 is an image memory, 21 is a binarizer, 22 is a binary memory, 23 is a subtracter, 24 is a difference memory, 25 is an encoder A,
26 is encoder B. Ino)°5 Tas 2e ())i Figure 74

Claims (1)

[Claims] a first encoding means for encoding a multi-value color signal within a multi-value color image area in a color image; and a second code for encoding a binary color signal outside the multi-value color image area in the color image. 1. A color image encoding apparatus, comprising: a color image encoding means; and a generation means for generating an area signal indicating the position and size of a multivalued color image area in the color image.