JPH03254135A - Structure of lead frame with semiconductor device attached - Google Patents
Structure of lead frame with semiconductor device attachedInfo
- Publication number
- JPH03254135A JPH03254135A JP5168590A JP5168590A JPH03254135A JP H03254135 A JPH03254135 A JP H03254135A JP 5168590 A JP5168590 A JP 5168590A JP 5168590 A JP5168590 A JP 5168590A JP H03254135 A JPH03254135 A JP H03254135A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- resin
- conductivity wires
- wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000011347 resin Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 abstract description 19
- 238000007789 sealing Methods 0.000 abstract description 12
- 238000002844 melting Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000000465 moulding Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004382 potting Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体素子付リードフレームの改良に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a lead frame with a semiconductor element.
パンケージ型の半導体ＩＣチップは、帯状のリードフレ
ーム上に半導体素子をダイボンディング加工工程によっ
て接続し、その後熱硬化性樹脂でインサート底形し、不
要部分を切り落とすことによって製品となる。このため
、インサート成形用の金型が不可欠で、その製作が煩雑
であり、しかも高価になる。また、最近、リードフレー
ム工法で、半導体素子の他に回路の導電部分を兼ねたパ
ターンをプレス加工することが提案されているが、回路
パターンの形状が複雑になるため、インサート成形用の
金型の設計製作が難しく、それが上記欠点をさらに助長
する結果となっている。A pancage type semiconductor IC chip is manufactured by connecting a semiconductor element onto a strip-shaped lead frame through a die bonding process, then shaping the bottom of the insert with thermosetting resin, and cutting off unnecessary parts. For this reason, a mold for insert molding is essential, and its manufacture is complicated and expensive. Recently, it has been proposed to press a pattern that also serves as the conductive part of the circuit in addition to the semiconductor element using the lead frame construction method, but since the shape of the circuit pattern becomes complicated, the mold for insert molding is It is difficult to design and manufacture, which further exacerbates the above-mentioned drawbacks.
したがって、本発明の目的は、リードフレーム上の半導
体素子をインサート底形によらないで、封止できるよう
にすることである。Therefore, an object of the present invention is to enable a semiconductor element on a lead frame to be sealed without depending on the bottom shape of the insert.
そこで、本発明は、リードフレーム上に、半導体素子を
位置決めし、この半導体素子の電極部分とリードフレー
ムの端子部分とをワイヤボンディング加工によって導電
ワイヤで電気的に接続状態とし、リードフレームの裏面
側に耐熱シートを置き、半導体素子および導電ワイヤを
ボッティング工程による樹脂によって被覆し、この樹脂
で半導体素子を封止している。Therefore, the present invention positions a semiconductor element on a lead frame, electrically connects the electrode part of the semiconductor element and the terminal part of the lead frame with a conductive wire by wire bonding, and A heat-resistant sheet is placed on the substrate, the semiconductor element and the conductive wire are covered with resin by a botting process, and the semiconductor element is sealed with this resin.
上記封止用の樹脂は、ポツティング工程によって、半導
体素子および導電ワイヤを充分に被覆する量だけ供給さ
れる。したがって、これらの半導体素子および導電ワイ
ヤの被覆のための封止過程で、インサート成形と異なり
、特別な金型が必要とされないため、インサート成形用
の金型の使用に伴う上記欠点が全て解決できる。しかも
、リードフレームの裏面側に耐熱シートが存在するため
、樹脂のポツティング工程で、その樹脂が流失せず、所
定の位置すなわち半導体素子および導電ワイヤを確実に
封止できる状態となる。The above-mentioned sealing resin is supplied by the potting process in an amount sufficient to cover the semiconductor element and the conductive wire. Therefore, unlike insert molding, a special mold is not required in the sealing process for covering these semiconductor elements and conductive wires, so all of the above-mentioned drawbacks associated with the use of molds for insert molding can be solved. . Moreover, since the heat-resistant sheet is present on the back side of the lead frame, the resin does not flow away during the resin potting process, and a predetermined position, that is, the semiconductor element and the conductive wire, can be reliably sealed.
第１図は、本発明の半導体素子付リードフレーム１の構
造を示している。FIG. 1 shows the structure of a lead frame 1 with a semiconductor element according to the present invention.
この半導体素子付リードフレーム１は、半導体素子２と
リードフレーム３とで組み立てられる。This lead frame 1 with a semiconductor element is assembled with a semiconductor element 2 and a lead frame 3.
半導体素子２は、例えばＩＣチップなどであり、外部に
対する電気的な接続のために、複数の端子２１を備えて
いる。The semiconductor element 2 is, for example, an IC chip, and includes a plurality of terminals 21 for electrical connection to the outside.
また、リードフレーム３は、第２図に示すように、帯状
の導電性薄金属板３１から両側縁の連続部３２を残して
、各連続部３２に対し連結部３３で連結された状態で、
製品単位毎にプレス打ち抜き加工によって成形され、そ
れぞれの用途に応し、スイッチ接続端子３４、一対の電
池接片３５の他、これらにつながり、上記半導体素子２
の端子２１に接続可能な端子部３６を一体的に形成して
いる。Further, as shown in FIG. 2, the lead frame 3 is connected to each continuous portion 32 by connecting portions 33 from the strip-shaped conductive thin metal plate 31, leaving continuous portions 32 on both side edges.
Each product unit is formed by press punching, and depending on the application, it has a switch connection terminal 34, a pair of battery contact pieces 35, and the semiconductor element 2 connected thereto.
A terminal portion 36 connectable to the terminal 21 is integrally formed.
そして、リードフレーム３の取り付は位置に半導体素子
２が接着剤４などによって固定され、またこの半導体素
子２の真下位置でリードフレーム３の下面側に、耐熱プ
ラスチックなどの耐熱シート５が接着剤６によって固定
されている。半導体素子２の端子２１は、導電ワイヤ７
によって、リードフレーム３の端子部３６に電気的に接
続される。この状態で、半導体素子２および導電ワイヤ
７は、リードフレーム３の表面側から封止用の樹脂８に
よって覆われ、直接外部に露出しないようになっている
。したがって、半導体素子付リードフレームｌは、従来
と同様に、封止用の樹脂８によって覆われているが、こ
の樹脂８は、熱溶融状態でポツティング工程によって成
形されるため、その成形に際し、成形金型などが必要と
されない。When mounting the lead frame 3, the semiconductor element 2 is fixed in position with an adhesive 4, and a heat-resistant sheet 5 made of heat-resistant plastic is placed on the lower surface of the lead frame 3 directly below the semiconductor element 2. It is fixed by 6. The terminal 21 of the semiconductor element 2 is connected to the conductive wire 7
It is electrically connected to the terminal portion 36 of the lead frame 3 by. In this state, the semiconductor element 2 and the conductive wire 7 are covered with the sealing resin 8 from the front side of the lead frame 3 so that they are not directly exposed to the outside. Therefore, the lead frame l with a semiconductor element is covered with a sealing resin 8 as in the past, but since this resin 8 is molded in a hot molten state by a potting process, the molding No molds are required.
〔製造方法」
半導体素子付リードフレーム１は、第３図のような工程
によって製作される。[Manufacturing method] The lead frame 1 with a semiconductor element is manufactured by the steps shown in FIG.
まず、プレス打ち抜き工程で、リードフレーム３が導電
性薄金属板３１から製品単位毎に連続的に打ち抜かれる
。First, in a press punching process, the lead frame 3 is continuously punched out from the conductive thin metal plate 31 for each product.
次の接着工程で、リードフレーム３の表面および裏面側
に、それぞれ接着剤４．６が塗布され、表面側に半導体
素子２が位置決め状態で接着剤４によって固定され、ま
た裏面側で、所定の大きさの耐熱シート５が接着剤６に
よって固定される。In the next adhesion process, adhesive 4.6 is applied to the front and back sides of the lead frame 3, and the semiconductor element 2 is fixed in position on the front side with the adhesive 4, and on the back side, a predetermined A heat-resistant sheet 5 of the same size is fixed with an adhesive 6.
このあとのワイヤボンディング工程で、半導体素子２の
端子２１とリードフレーム３の端子部３６との間に導電
ワイヤ７が自動ワイヤポンディング機による熱圧着など
によって取り付けられる。In the subsequent wire bonding step, the conductive wire 7 is attached between the terminal 21 of the semiconductor element 2 and the terminal portion 36 of the lead frame 3 by thermocompression bonding using an automatic wire bonding machine or the like.
最後のポツティング工程で、リードフレーム３の表面側
から、半導体素子２および導電ワイヤ７を覆うための封
止用の樹脂８が液状または熱溶融状態で、リードフレー
ム３の表面側から所定の量だけ供給される。このとき、
溶融状態の樹脂８は、その流動性によって、半導体素子
２や導電ワイヤ７の空間内にも入り込み、リードフレー
ム３の隙間から下方にも流れ出ようとするが、リードフ
レーム３の裏面側に、耐熱シート５が貼り付けられてい
るため、溶融状態の樹脂８は、耐熱シート５によって保
持され、流失しない。したがって、耐熱シート５の大き
さは、封止用の樹脂８の流失を防止するのに充分な大き
さに設定される。またその耐熱温度は、樹脂８の溶融温
度および加熱硬化過程の加熱温度によっても、変形しな
い値でなければならない。このあと、溶融状態の樹脂８
は、冷却または加熱過程で硬化し、半導体素子２や導電
ワイヤ７の外周面を覆い、リードフレーム３と一体化す
る。In the final potting step, a predetermined amount of the sealing resin 8 in a liquid or heat-molten state for covering the semiconductor element 2 and the conductive wire 7 is poured from the surface side of the lead frame 3. Supplied. At this time,
Due to its fluidity, the molten resin 8 tends to enter the space of the semiconductor element 2 and the conductive wire 7, and also tends to flow downward through the gap in the lead frame 3. Since the sheet 5 is attached, the resin 8 in a molten state is held by the heat-resistant sheet 5 and does not flow away. Therefore, the size of the heat-resistant sheet 5 is set to be large enough to prevent the sealing resin 8 from flowing away. Further, its heat-resistant temperature must be such that it will not be deformed even by the melting temperature of the resin 8 and the heating temperature during the heat curing process. After this, the molten resin 8
hardens during the cooling or heating process, covers the outer peripheral surfaces of the semiconductor element 2 and the conductive wire 7, and becomes integrated with the lead frame 3.
これらのそれぞれの工程は、連続部３２を送り真内部分
として、連続的に行われる。そして、最詩的に連結部３
３が連続部３２からカソト工程で切断されることによっ
て、半導体素子付リードフレーム１は、ユニット毎に製
品化される。なお、外付けのための部品例えばスイッチ
や、その他の電気回路部品などは、カント工程後に、リ
ードフレーム３の所定の位置に取り付けられる。Each of these steps is performed continuously using the continuous portion 32 as the inner feeding portion. And, most poetically, the connecting part 3
3 is cut from the continuous portion 32 in a kasoto process, the lead frame 1 with a semiconductor element is manufactured into units. Note that components for external attachment, such as switches and other electric circuit components, are attached to predetermined positions on the lead frame 3 after the canting process.
本発明では、下記の効果がある。 The present invention has the following effects.
半導体素子および導電ワイヤの封止過程で、インサート
成形が行われず、溶融状態の樹脂の流動性を利用して行
われるため、インサート成形のために高価な金型が必要
とされず、封止工程が簡略化される。In the process of encapsulating semiconductor elements and conductive wires, insert molding is not performed and the process utilizes the fluidity of the molten resin, so expensive molds are not required for insert molding, and the encapsulation process is simplified. is simplified.
しかも、半導体素子の大きさやリードフレームの形状の
変化に対しても、封止用の樹脂の量を加減するだけで、
半導体素子や導電ワイヤが完全な状態に封止できる。Moreover, even if the size of the semiconductor element or the shape of the lead frame changes, just adjust the amount of sealing resin.
Semiconductor elements and conductive wires can be completely sealed.
さらに、熱溶融状態の封止過程で、リードフレームの裏
面側に耐熱シートが存在するため、溶融状態の樹脂が流
失せず、半導体素子および導電ワイヤの他、リードフレ
ームの空間部分にも入り込んだ状態で、完全に一体化し
、従来の成形型パッケージとほぼ同様の強度が得られる
。Furthermore, during the sealing process in a hot molten state, the presence of a heat-resistant sheet on the back side of the lead frame prevents the molten resin from flowing away, allowing it to enter not only the semiconductor elements and conductive wires but also the open spaces in the lead frame. In this state, it is fully integrated and has almost the same strength as a conventional molded package.
第１図は本発明の半導体素子付リードフレームの断面図
、第２図は帯状の導電性薄金属板およびリードフレーム
の平面図、第３図は半導体素子付リードフレームの製造
工程の説明図である。
１・・半導体素子付リードフレーム、２・・半導体素子
、３・・リードフレーム、４・・接着剤、５・・耐熱シ
ート、６・・接着剤、７・・導電ワイヤ、８・・樹脂。
特 許 出 願 人 株式会社三協精機製作所代
理 人 弁理士 中 川 國 実弟７図
第３図
第２図
４２１
５Fig. 1 is a sectional view of a lead frame with a semiconductor element of the present invention, Fig. 2 is a plan view of a strip-shaped conductive thin metal plate and the lead frame, and Fig. 3 is an explanatory diagram of the manufacturing process of the lead frame with a semiconductor element. be. 1. Lead frame with semiconductor element, 2. Semiconductor element, 3. Lead frame, 4. Adhesive, 5. Heat resistant sheet, 6. Adhesive, 7. Conductive wire, 8. Resin. Patent applicant Sankyo Seiki Seisakusho Co., Ltd.
Attorney Patent Attorney Kuni Nakagawa Younger brother 7 Figure 3 Figure 2 421 5
Claims (1)
フレームと、上記半導体素子とリードフレームとを結合
する導電ワイヤと、上記半導体素子および導電ワイヤを
覆う樹脂と、上記半導体素子の真下に位置し、かつリー
ドフレームの裏面側に配置された耐熱シートとを備え、
上記樹脂で半導体素子を封止してなることを特徴とする
半導体素子付リードフレームの構造。A semiconductor element, a lead frame to which the semiconductor element is attached, a conductive wire that connects the semiconductor element and the lead frame, a resin that covers the semiconductor element and the conductive wire, and a lead located directly below the semiconductor element. Equipped with a heat-resistant sheet placed on the back side of the frame,
A structure of a lead frame with a semiconductor element, characterized in that the semiconductor element is sealed with the resin described above.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5168590A JPH03254135A (en) | 1990-03-05 | 1990-03-05 | Structure of lead frame with semiconductor device attached |
| CN 91101183 CN1030216C (en) | 1990-03-05 | 1991-02-22 | Electronic sound-producing device |
| KR1019910002989A KR0165544B1 (en) | 1990-03-05 | 1991-02-25 | Electronic sound producing device |
| US07/662,522 US5264656A (en) | 1990-03-05 | 1991-02-28 | Electronic sound generating device |
| GB9104356A GB2243479B (en) | 1990-03-05 | 1991-03-01 | Electronic sound generating device |
| DE4106824A DE4106824A1 (en) | 1990-03-05 | 1991-03-04 | ELECTRONIC SOUND GENERATOR DEVICE AND METHOD FOR THEIR PRODUCTION |
| FR9102621A FR2659164B1 (en) | 1990-03-05 | 1991-03-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5168590A JPH03254135A (en) | 1990-03-05 | 1990-03-05 | Structure of lead frame with semiconductor device attached |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03254135A true JPH03254135A (en) | 1991-11-13 |
Family
ID=12893747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5168590A Pending JPH03254135A (en) | 1990-03-05 | 1990-03-05 | Structure of lead frame with semiconductor device attached |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03254135A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487181A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Resin sealing method for semiconductor element |
-
1990
- 1990-03-05 JP JP5168590A patent/JPH03254135A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487181A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Resin sealing method for semiconductor element |
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