JPH03253017A - Wafer and manufacture thereof - Google Patents

Wafer and manufacture thereof

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Publication number
JPH03253017A
JPH03253017A JP2051070A JP5107090A JPH03253017A JP H03253017 A JPH03253017 A JP H03253017A JP 2051070 A JP2051070 A JP 2051070A JP 5107090 A JP5107090 A JP 5107090A JP H03253017 A JPH03253017 A JP H03253017A
Authority
JP
Japan
Prior art keywords
wafer
stage
air
patterns
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2051070A
Other languages
Japanese (ja)
Inventor
Keisuke Tanimoto
啓介 谷本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2051070A priority Critical patent/JPH03253017A/en
Publication of JPH03253017A publication Critical patent/JPH03253017A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To enable a wafer in defective flatness to closely adhere to the stage of a flat aligner without rolling up air in the stage for flattening the surface of the wafer thereby enabling the fine patterns to be formed. CONSTITUTION:After forming silicon films on the surface and rear surface of a silicon wafer 1 by thermal oxidation process, a resist film 3 is formed on the rear surface and then exposed in specific patterns and developed so as to form continuous trench type resist patterns. Next, after etching away the films 2 using the patterns 3a as masks, the wafer 1 is etched away to form the continuous trenches 4 reaching both ends. Then, the multiple trenches reaching both ends of the wafer 1 are formed on the rear surface of the wafer 1. Through these procedures, the wafer 1 in defective flatness can closely adhere to the stage of a flat aligner for flattening the surface of the wafer without rolling up air in the stage, thereby enabling the fine patterns 3a to be formed.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、ウェハ及びその製造法に関する。[Detailed description of the invention] (b) Industrial application fields The present invention relates to a wafer and a method for manufacturing the same.

ことに、半導体集積回路の製造に用いられる。In particular, it is used in the manufacture of semiconductor integrated circuits.

(ロ)従来の技術 近年、半導体集積回路は高集積化の要求とともに、基板
上に形成される素子や配線パターンが微細化され、これ
に伴いホトリソグラフィ工程における露光焦点深度の低
下か問題となって0る。
(b) Conventional technology In recent years, with the demand for higher integration of semiconductor integrated circuits, the elements and wiring patterns formed on the substrate have become finer, and this has led to the problem of a decrease in the depth of focus of exposure in the photolithography process. te 0ru.

従来のウェハは、裏面未加工のウェハである。A conventional wafer is a wafer with an unfinished backside.

ホトリソグラフィ工程におけるウェハの露光は、表面に
素子又;よ素子中間体とホトレジスト膜とか順に積層さ
れ裏面未加工のウェハを吸引口を有する平坦な露光装置
のステージ上に載置し、吸引口から吸引することによっ
てその裏面をステージに吸着させ、その表面に対して露
光焦点合せの操作を行った後、光を照射して行われる。
In the photolithography process, a wafer is exposed to light by placing the wafer, which has elements or intermediates and a photoresist film laminated on the front surface in order and whose back side is unprocessed, on the stage of a flat exposure device that has a suction port. This is done by adhering the back surface to the stage by suction, performing an exposure and focusing operation on the front surface, and then irradiating it with light.

(ハ)発明が解決しようとする課題 従来の技術において、特に平坦度が損なわれたウェハを
露光する場合、縮小投影露光装置のステージにウェハを
真空吸着しても尚平坦度か改善さ把なかったり、逆に平
坦度の悪いウェハを真空吸着することでかえって平坦度
が損なわれる場合がある。このような場合は、ウェハ表
面に対して露光焦点か合わなくなり微細なパターンが形
成できないという問題がある。
(c) Problems to be Solved by the Invention In the conventional technology, especially when exposing a wafer with impaired flatness, even if the wafer is vacuum suctioned to the stage of a reduction projection exposure device, the flatness cannot be improved. On the other hand, vacuum suction of a wafer with poor flatness may actually impair the flatness. In such a case, there is a problem that the exposure focus is not on the wafer surface and a fine pattern cannot be formed.

この発明は、上記問題を解決するためになされf二もの
であって、平坦度が損なわ把たウェハに対してら平坦な
露光装置のステージに空気を巻込むことなく密着させて
表面を平坦にすることかてき、露光焦点を合わせて@細
なパターンを形成することができるウェハ及びその製造
法を提供しようとするしのである。
This invention was made in order to solve the above-mentioned problems, and it flattens the surface of a wafer whose flatness has been damaged by bringing it into close contact with the stage of a flat exposure device without entraining air. Therefore, it is an object of the present invention to provide a wafer that can form a fine pattern by focusing exposure and a method for manufacturing the same.

(ニ)課題を解決するための手段 この発明によ乙ば、ウェハの裏面に所定間隔てウェハ両
端面に達する連続的な微細溝を設けてたるウェハが提供
される。
(d) Means for Solving the Problems According to the present invention, there is provided a wafer in which continuous fine grooves are provided on the back surface of the wafer at predetermined intervals and reach both end surfaces of the wafer.

上記溝は、吸引口を有する実質的に平坦な露光装置のス
テージに載置されたウェハとこのステージ間の空気の一
部を、吸引によってこれらの間にとじ込められないよう
に(空気だまり防止)排出するためのものてあって、ス
テージ上にウェハか載置さ把た状態て上記吸引口から空
気を吸引すると、吸引に伴ってそりによって離れていf
ニウェハの裏面が平坦なステージ面に接近し、さらに吸
弓すると、溝を通してウェハの端面より空気を排出しな
が与ウェハのそりを減少しウェハを平坦なステージに密
着させることによってそのそりを解消しうるちのか適し
ている。
The grooves are designed to prevent part of the air between the stage and the wafer placed on the stage of the exposure equipment, which is substantially flat and has a suction port, from being trapped between them by suction (preventing air pockets). ) When a wafer is placed on the stage and air is sucked through the suction port, the wafer is warped and separated by the suction.
When the back side of a new wafer approaches the flat stage surface and is further sucked, air is exhausted from the edge of the wafer through the groove, reducing the warpage of the wafer and eliminating the warpage by bringing the wafer into close contact with the flat stage surface. Shiuruchika is suitable.

この溝の形成は、上記吸引によってウェハとステージ間
に空気fこまりを生じ広いようにウェハの裏面に配置し
て行われ乙ぽよく、ウェハのそりの大きさによってその
裏面に適宜分布させることがてきるか、通常ウェハの裏
面に均一に所定間隔になるように配置することができる
。この溝の間隔は、通常2〜IO,tv、好ましくは5
 x7fu度とすることができる。まfこ、この溝の空
気排出口は、ウェハの端面に形成されるのが適しており
、ウェハ裏面に、そのウェハ両端面に達する連続的な微
細な溝を形成することによって、ウェハ端面に配置する
ことかできる。
The grooves are preferably formed on the back surface of the wafer so that they are wide enough to create air pockets between the wafer and the stage due to the suction, and can be appropriately distributed on the back surface depending on the size of the warp of the wafer. Alternatively, they can be placed uniformly on the back surface of the wafer at predetermined intervals. The interval between these grooves is usually 2 to IO, tv, preferably 5
x7fu degree. It is suitable for the air outlet of this groove to be formed on the end surface of the wafer, and by forming continuous fine grooves on the back surface of the wafer that reach both end surfaces of the wafer, It can be placed.

また、この溝は、少なくとら空気が瞬時に通過てきる大
きさを有すると共に上記吸引口から吸弓によって生じる
ウェハに対するステージの吸着力(ウェハのそりを解消
しうる大きさ)を阻害しない程度に微細にすることが必
要である。この様な要件を満fこす溝のサイズは、通常
幅50〜300μm、深ざ1−10μmo′)l断面か
らなる。この溝の具体的な形成は、飼えばホトリソグラ
フィ広等によって行うことかできる。ホトリソグラフィ
庄によると、まず、ウェハを裏4して処理するfコめに
表面の保護膜として、例え:f酸化膜を形成する。次に
公知の方法によってレジスト膜を形成する。レジスト膜
のパターニング:よ、溝Iくターンの入っfこレチクル
を縮小投影露光装置に装着して露光するか、又はウェハ
を走査させなからスポット光を当てる方法でも良い。次
に行う酸化膜とウェハのエツチングは、等方性のものを
用いてもよいか、異方性のものでも構わない。等方性エ
ツチングでは、例えば弗酸で酸化膜をエツチングし、続
いて弗酸と硝酸の混合液でウェハ(基板シリコン)をエ
ツチングすることができる。異方性エツチングでは、平
行平板型RIEエツチング装置とCHF、ガス(他にC
H,、C,F、?、;ど)を用いて酸化膜のエツチング
ができる。この後に平行平板型RIEエツチング装置と
SF、ガス(又はCIt、 S i C14゜CF、、
CC1,など)を用いてシリコンのエツチングが可能と
なる。この後硫酸などでレジストを除去し、更に弗酸l
とて基板両面の酸化膜を除去して溝を形成する二とかで
きる。
In addition, this groove has a size that allows at least air to pass through instantaneously, and is also large enough to not impede the suction force of the stage to the wafer (a size that can eliminate warping of the wafer) generated by the suction bow from the suction port. It is necessary to make it fine. A groove that satisfies these requirements usually has a cross section with a width of 50 to 300 .mu.m and a depth of 1 to 10 .mu.m. The specific formation of this groove can be performed by photolithography, etc. According to Photolithography Sho, first, a wafer is turned over and an oxide film, for example, is formed as a protective film on the surface of the wafer to be processed. Next, a resist film is formed by a known method. Patterning of the resist film: The reticle with the grooves and the turns may be attached to a reduction projection exposure device and exposed, or a method may be used in which the wafer is not scanned and a spot light is applied. The subsequent etching of the oxide film and wafer may be isotropic or anisotropic. In isotropic etching, for example, the oxide film can be etched with hydrofluoric acid, and then the wafer (silicon substrate) can be etched with a mixed solution of hydrofluoric acid and nitric acid. In anisotropic etching, a parallel plate type RIE etching apparatus and CHF, gas (in addition, C
H,,C,F,? , ; etc.) can be used to etch the oxide film. After this, parallel plate type RIE etching equipment and SF, gas (or CIt, SiC14°CF,...
CC1, etc.) can be used to etch silicon. After that, remove the resist with sulfuric acid, etc., and then remove the resist with hydrofluoric acid.
Then, the oxide film on both sides of the substrate can be removed to form a groove.

上述のようにして裏面に所定の溝か形成さ乙几ウェハは
、通常表面に素子又(よ素子の中間体とレジスト膜とを
頓に形成し、次に第4図(a)及ff (b)等で示す
ような吸引口を有する平坦広露光装置のステージ上に載
置される。ただしIIa、llbは露光装置のステージ
、+2a、12bは吸引口、+3a、+3bは平坦な支
持部材である。次に吸引口より吸引することによってウ
ェハとステージ間の空気をウェハの溝を通してウェハ両
端面の溝の開口から排出し、空気を巻込むことなくウェ
ハをステージに密着させる。この密着によってウェハは
、その表面が平坦化さ乙、平坦な表面に露光焦点を合わ
せて露光することができる。
The wafer with the predetermined grooves formed on the back surface as described above is usually formed with an element or an element intermediate and a resist film on the front surface, and then as shown in FIGS. 4(a) and ff( b) It is placed on the stage of a flat wide exposure apparatus having a suction port as shown in FIG. Next, by suctioning from the suction port, the air between the wafer and the stage is discharged through the grooves of the wafer and from the openings of the grooves on both end faces of the wafer, and the wafer is brought into close contact with the stage without entraining air. can be exposed by focusing the exposure on the flat surface, so that the surface is flattened.

(ホ)作用 ウェハ裏面に形成されfコ溝か、露光装置のステージと
ウェハとの間の空気を通して空気たまりを生じることな
くウェハ両端面から排出させウェハを平坦なステージに
密着させこの半導体基板表面のそりを解消する。
(e) Operation Air is passed between the stage of the exposure device and the wafer through the f-groove formed on the back surface of the wafer, and is discharged from both end surfaces of the wafer without creating any air pockets.The wafer is brought into close contact with a flat stage on the surface of the semiconductor substrate. Eliminate warpage.

(へ)実施例 この発明の実施例を図面を用いて説明する。(f) Example Embodiments of the invention will be described with reference to the drawings.

実施例1 ウェハ裏面の溝の作製 第2図(a)及び(b)に示すように、直径4インチ、
厚さ525μmのシリコノウエバlの表面と裏面とに勢
酸化法によってノリコン酸化膜2を形成する。
Example 1 Preparation of grooves on the back side of the wafer As shown in FIGS. 2(a) and (b), grooves with a diameter of 4 inches and
A silicon oxide film 2 is formed on the front and back surfaces of a 525 μm thick silicone wafer 1 by a oxidation method.

次に、第2図(C)及び(d)に示すようにこの裏面に
レジスト膜3を形成し、このウニ/\を走査させなか与
レジスト膜3にスポット先を線状に当てることによって
所定パターンに露光し、現像することによって連続的む
溝状のレジストパターン3aを形成する。
Next, as shown in FIGS. 2(C) and (d), a resist film 3 is formed on this back surface, and a predetermined spot is applied to the resist film 3 in a linear manner while scanning the sea urchin/\. By exposing the pattern to light and developing it, a continuous groove-like resist pattern 3a is formed.

次に、第2図(e)に示すようにレジストパターン3a
をマスクにして弗酸水溶演によってソリコン酸化@2を
エツチングし、続いて弗酸と硝酸との混合水溶液によっ
てシリコノウエバlをエツチングしてノリコンウェハ両
端面に達する連続的な溝4を形成する。
Next, as shown in FIG. 2(e), the resist pattern 3a is
Using as a mask, the silicon oxide @2 is etched by aqueous hydrofluoric acid solution, and then the silicone wafer l is etched with a mixed aqueous solution of hydrofluoric acid and nitric acid to form continuous grooves 4 reaching both end faces of the silicone wafer.

次に第2図([’)及L”(g)に示すようにレジスト
パターン3a及ブノリコン酸化膜2を除去する。この結
果、第1図(a)及び(b)に示すようにシリコンウェ
ハIの裏面5に幅100μm、深さ5μmの横断面を有
しノリコンウェハの両端面に達する溝4か4.51間隔
て多数形成さ乙fコシリコンウエハを得る。
Next, the resist pattern 3a and the silicon oxide film 2 are removed as shown in FIG. 2 ([') and L" (g). As a result, the silicon wafer is A silicon wafer is obtained in which a large number of grooves 4 are formed at 4.51 intervals on the back surface 5 of the silicon wafer, each having a cross section of 100 μm in width and 5 μm in depth, reaching both end surfaces of the silicon wafer.

このシリコンウェハは、ウェハを平坦な台の上に載置し
て基板面の最大高さを測定することにより得eれるそり
量が5μmであった。
The amount of warpage of this silicon wafer was 5 μm, which was obtained by placing the wafer on a flat table and measuring the maximum height of the substrate surface.

ウェハ表面の素子用薄膜及びレジスト膜の作製上記裏面
に溝が形成さ乙几シリコンウェハlの表面に熱酸化法に
よってノリコン酸化膜7を形成し、この上に化学気相成
長(CVD)法によって膜厚02μmのタングステンシ
リサイド層8を積層する。
Preparation of element thin film and resist film on the wafer surface Grooves are formed on the back surface of the wafer.Noricon oxide film 7 is formed on the surface of the silicon wafer 1 by thermal oxidation method, and on this is formed by chemical vapor deposition (CVD) method. A tungsten silicide layer 8 having a thickness of 02 μm is laminated.

次に、この上にレジスト溶液を塗布し、ホットプレート
上で加熱乾燥して膜厚1μmのレジスト膜9を形成する
。このウェハは、第3図(a)に示すように上記測定と
同様にして得られるそり量10か20μmてめった。
Next, a resist solution is applied thereon and dried by heating on a hot plate to form a resist film 9 having a thickness of 1 μm. As shown in FIG. 3(a), this wafer was subjected to a warpage of 10 to 20 μm obtained in the same manner as the above measurement.

半導体基板の露光 第4図(b)に示すように表面に平坦な支持部材13a
と吸引口+2bとを有する露光装置のステンIlb上に
、上記20μmのそりを有するウェハ1(第3図(a)
)を載置し、吸引口12bより空気を吸引する。この結
果、ウェハl中央部下部に巻き込ま乙んとする空気か溝
4を通ってウェノ\両端面の溝開口部から放出さ乙(第
3図(b))に示すようにウェハlのそりが吸引力によ
って解消されてステージllb上に表面平坦な状態て固
定さ乙fコ。なお、第4図(b)に示すような露光装置
のステージの代わりに第4図(a)に示すようなステー
ジによっても同様に行うことかできる。第4図(a)に
おいて、llaは露光装置のステージ、12a吸引口、
13aは平坦な支持部材である。
Exposure of semiconductor substrate As shown in FIG. 4(b), a support member 13a with a flat surface is provided.
The wafer 1 having the warp of 20 μm (see FIG. 3(a)
) is placed and air is sucked through the suction port 12b. As a result, the air that is caught in the lower center of the wafer passes through the groove 4 and is released from the groove openings on both end faces of the wafer (as shown in Figure 3 (b)), causing the wafer to warp. The surface is fixed on the stage llb in a flat state by being released by the suction force. Note that the same process can be performed using a stage as shown in FIG. 4(a) instead of the stage of the exposure apparatus as shown in FIG. 4(b). In FIG. 4(a), lla is the stage of the exposure device, 12a is the suction port,
13a is a flat support member.

次に、露光装置の光源に対してシリコノウエバlの表面
(レジスト@)に焦点を合わせて、シリコノウエバlを
所定パターンに露光し、現像してレジストパターンを形
成する。
Next, the light source of the exposure device is focused on the surface (resist@) of the silicone rubber l, and the silicone web l is exposed to light in a predetermined pattern and developed to form a resist pattern.

得ら杷fこレジストパターンは顕微鏡によって検査しr
二ところ微細なパターンか精度よく形成されていること
か確二Σさ乙に。
The resulting resist pattern was examined under a microscope.
The two most important points are that the fine patterns are formed with high precision.

比較例1 実施列1において、ノリコンウェハ裏面に溝の作製を行
う代わりに、溝を作製せず、この(也:よ実施例1と同
様にして第5図(a)に示すようにシリコンウェハ2I
上にノリコン酸化膜22を介してタングステンソリサイ
ド膜23を形成し、この上にレジスト膜25を形成しT
こ。このウェハは、実施例1と同様のそり量(20μm
)てあった。
Comparative Example 1 In Example 1, instead of forming grooves on the back surface of the silicon wafer, a silicon wafer 2I was formed in the same manner as in Example 1 without forming the grooves.
A tungsten solicide film 23 is formed on top via a silicon oxide film 22, and a resist film 25 is formed on this.
child. This wafer had the same amount of warpage as in Example 1 (20 μm
) was there.

次に、このウェハを実施例1と同様にして露光装置のス
テージllbに真空吸着させたところ第5図(b)に示
すように基板中央部下方に空気を巻き込んで空気巻込み
部27か形成され、2〜3μmのウェハ表面のそり26
が発生し、この状態では、露光装置の光源に対してシリ
コンウェハ1の表面(レジスト膜)に焦点を合せること
がてきなかった。
Next, this wafer was vacuum-adsorbed onto stage llb of an exposure apparatus in the same manner as in Example 1, and as shown in FIG. wafer surface warpage of 2 to 3 μm
In this state, the light source of the exposure apparatus could not be focused on the surface (resist film) of the silicon wafer 1.

(ト)発明の効果 この発明によれば、平坦度が損なわれrニウェハに対し
てら平坦G露先装置のステージに空気を巻込むことなく
密着させてその表面を平坦にすることかでき、露光焦点
を合nせて微細Gパターンを形成することのてきるウェ
ハ及びその製産法を提供することができる。
(G) Effects of the Invention According to this invention, even if the flatness of a wafer is impaired, it is possible to flatten the surface of the wafer by bringing it into close contact with the stage of the flat G exposure device without entraining air, and to expose the wafer. It is possible to provide a wafer on which a fine G pattern can be formed by focusing, and a method for manufacturing the same.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)はこの発明の実施例で作製したノリコンウ
ェハ裏面に形成されfコ溝の説明図、’41E1(b)
は溝の拡大説明図、第2図(a)〜(g)は同じく溝の
形成工程説明図、第3図(a)は同しくシリコンウェハ
のそりの説明図、第3図(b)は同じく露光装置のステ
ージに真空吸着されたシリコンウェハの説明図、第4図
は同じく露光装置のステージの説明図、第5図は従来の
露光装置のステージに真空吸着されrこウェハの説明図
である。 溝、5・ シリコン基板の裏面、 ノリコノ基板の表面、 ・・・ノリコン酸化膜、 ・タングステンソリサイト層、 レジスト膜、10 ・そり量、 11b・・ ・露光装置のステージ、 +2b  ・ 吸引口、 13b・・・平坦む支持部材。 7 ・ 1a 2a 3a l・・・・・・シリコン基板、2・・・・・・シリコン
酸化膜、3・・・・・レジスト膜、 3a・・・・・・レジストパターン、 III 1  !1(a) (a) 禦 21 (b) * 1  w (b) (a) 筒 胃
FIG. 1(a) is an explanatory diagram of the f-shaped groove formed on the back surface of the Noricon wafer produced in the embodiment of the present invention, and '41E1(b)
is an enlarged explanatory diagram of the groove, FIGS. 2(a) to (g) are also explanatory diagrams of the process of forming the groove, FIG. 3(a) is an explanatory diagram of warping of the silicon wafer, and FIG. Similarly, FIG. 4 is an explanatory diagram of a silicon wafer vacuum-adsorbed on the stage of an exposure apparatus. FIG. 5 is an explanatory diagram of a silicon wafer vacuum-adsorbed on the stage of a conventional exposure apparatus. be. Groove, 5. Back side of silicon substrate, surface of Norikono substrate, ... Noricon oxide film, - Tungsten soricite layer, resist film, 10 - Amount of warpage, 11b... Stage of exposure device, +2b - Suction port, 13b ...Flat support member. 7. 1a 2a 3a l...Silicon substrate, 2...Silicon oxide film, 3...Resist film, 3a...Resist pattern, III 1! 1 (a) (a) 禦 21 (b) * 1 w (b) (a) Cylindrical stomach

Claims (1)

【特許請求の範囲】 1、ウェハの裏面に所定間隔でウェハ両端面に達する連
続的な微細溝を設けてなるウェハ。 2、ウェハの両面に保護膜を形成し、ウェハ裏面上にレ
ジスト膜を形成し、次いで所定ウェハ端面に達する線状
パターンを形成した後、保護膜及びウェハをエッチング
し、次いで保護膜とレジスト膜を除去することからなる
微細溝を有するウェハの製造法。
[Claims] 1. A wafer in which continuous fine grooves are provided on the back surface of the wafer at predetermined intervals and reach both end surfaces of the wafer. 2. Form a protective film on both sides of the wafer, form a resist film on the back side of the wafer, then form a linear pattern that reaches a predetermined wafer edge, then etch the protective film and the wafer, and then remove the protective film and resist film. A method for manufacturing a wafer having microgrooves, which comprises removing.
JP2051070A 1990-03-01 1990-03-01 Wafer and manufacture thereof Pending JPH03253017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2051070A JPH03253017A (en) 1990-03-01 1990-03-01 Wafer and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2051070A JPH03253017A (en) 1990-03-01 1990-03-01 Wafer and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03253017A true JPH03253017A (en) 1991-11-12

Family

ID=12876546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2051070A Pending JPH03253017A (en) 1990-03-01 1990-03-01 Wafer and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03253017A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008177468A (en) * 2007-01-22 2008-07-31 Tokyo Electron Ltd Processing method of substrate, coater and substrate treatment system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008177468A (en) * 2007-01-22 2008-07-31 Tokyo Electron Ltd Processing method of substrate, coater and substrate treatment system

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