JPH03252997A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress the increase of the number of elements to flexibly relieve defects by providing an address decoding means and an output control means which outputs a prescribed value in response to the decoded result of the decoding means independently of contents stored in semiconductor memory elements. CONSTITUTION:A select detecting circuit 200 which detects that at least a part of signals generated by an address decoder 100 is selected and a control circuit which outputs preliminarily determined prescribed information at the time of detecting this selection by the select detecting circuit 200 and outputs information from a read circuit 302 at the time of not detecting it are provided. Consequently, an independent address decoding means for relief is unnecessary because a relief area is detected in response to the decoded result of the address decoding means, namely, the address decoder 100 which accesses semiconductor memory elements. Thus, defects are relieved with the area, which is designated by the address decoder 100, as a unit, to improve the relief flexibility.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a defect relief technique in a read-only semiconductor memory.

[Conventional technology]

As the degree of integration of semiconductor integrated circuits increases, a reduction in yield due to defects generated during the manufacturing process has become a problem.

For example, in logic LSIs, such defects may cause errors in logic values. In order to provide a defect relief function that automatically corrects this, there is a technique of providing an additional defect relief circuit, that is, a redundant circuit, on the chip to improve yield.

On the other hand, semiconductor memory, especially read-only so-called RO
In M, it is effective to repair defects in unused areas or areas where the same data continues.

An example thereof is described in JP-A-1-241100. In this prior art, the RO to be rescued
Detecting access to the unused area (relief area) of M,
Controls the data to be output.

[Problem to be solved by the invention]

According to the study by the inventors of the present application, in the above-mentioned conventional technology, a relief decoder circuit is provided separately from a decoder circuit for accessing the ROM, and a control signal is generated in response to input of an address for accessing a relief area. And this causes R
A predetermined fixed value is output instead of OM data.

Therefore, it has become clear that the number of elements required to provide a relief area decoder circuit separately from the decoder circuit for accessing the ROM increases, resulting in an increase in chip area.

Furthermore, the maximum number and area size of the relief areas are fixed depending on the configuration of the relief decoder circuit, which results in a lack of flexibility as a relief method. For example, “0” which is less than the size of the area (relief area) specified by the relief decoder
Alternatively, it is impossible to repair defects in a continuous area of 1''.

Furthermore, if the number of relief areas exceeds the maximum number of decoded outputs of the relief decoder, relief must be abandoned. In order to solve these flexibility problems based on the above-mentioned prior art, a rescue decoder circuit of the same size as the original decoder circuit is required. This results in a significant increase in the number of elements.

Note that the number of relief areas here refers to the number of relief areas that are divided by areas that are not relief areas (non-relief areas) in the memory area, and the size of relief areas refers to the number of relief areas that exist within the memory area. This refers to the size of the address space.

An object of the present invention is to provide a semiconductor memory device that can perform defect relief with great flexibility while suppressing an increase in the number of elements.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory device of the present invention includes an information storage means comprising a plurality of semiconductor memory elements, and an address decoding means for decoding an address signal to access at least one element of the plurality of semiconductor memory elements. and output control means for outputting a predetermined value regardless of the content stored in the semiconductor memory element in response to the decoding result by the decoding means.

More specifically, the semiconductor memory device of the present invention includes a memory matrix made up of a plurality of semiconductor memory cells arranged in a matrix, and a signal that decodes an address signal to specify a predetermined area in the memory matrix. a readout circuit that reads information stored in the memory matrix; a selection detection circuit that detects selection of at least a part of the signal generated by the address decoder; and a selection detection circuit that detects selection. It has a control circuit that outputs predetermined information when detected, and outputs information from the readout circuit when detected.

[Effect]

According to the present invention, a relief area can be detected in response to the solution result of the address decoder (address decoder) for accessing the semiconductor memory element, so the relief area can be detected by the address decoder (relief decoder) There is no need to provide a separate one.

Furthermore, defect relief can be performed in units of areas specified by address decoding means (address decoder) that accesses the semiconductor memory element, thereby increasing the flexibility of relief.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows the constituent countries of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, a decoding result output line (
selection detection means 20 coupled to the word line) 110;
0 is set, and access to the area 320 to be rescued is detected.

In this embodiment, each address decoded by the address decoder 100 corresponds to one word in the memory cell array 300 (for example, one word arranged horizontally in the memory cell array 300).
6-bit area), and relief is performed in units of words. The detection result is detected on the detection signal line 12.
0 is sent to the fixed value output means 400, which forcibly outputs a predetermined fixed value according to the logical value of the relief area. More specific operations are as follows.

An example will be explained in which the relief area 320 is an area where "'O" should originally be continuous. When this relief area 320 is accessed, decoding result output lines 110b, C, f, g+h select the relief area 320.

One of i is enabled. Selection detection means 200
is electrically connected to the decoding result output line for selecting the relief area 320, and detects access to the relief area 320. The detection result is transmitted to the fixed value output means 400 via the detection signal line 120, and the fixed value output means 400 is transmitted to the fixed value output means 400 through the detection signal line 120. More whole pi
~II Output OII. However, the non-relief area 310
When any address in the relief area 320 is accessed, the relief area 320
The decode result output line that selects is not equivalent to enable. Therefore, the selection detection means 200 does not detect the enable of the decoding result output line that selects the relief area 320,
Fixed value output means 4. OO outputs the contents of the ROM read out via the read circuit (sense amplifier) 302, that is, the information actually written in the non-relief area 310 as is.

As in this example, the area where (lOII should be continuous) will be called the O (defect) relief area.Similarly, the area where (11II should originally be continuous) will be called the 1 (defect) relief area. Make it.

The location where the selection detection means 200 and the decoding result output line 110 are electrically connected can be determined by defining the relief area. Therefore, 1. For example, if the memory cell array 300 is composed of a mask ROM, when writing data to the mask ROM in the manufacturing process of this memory device, a relief area is determined according to this data, and a relief area is determined according to the arrangement of this relief area. The electrical connection between the selection detection means 200 and the decoding result output line 110 can be determined.

Furthermore, the memory cell array 300 may be configured with an electrically writable ROM (EPROM). At this time, a circuit for writing to this EPROM is provided. Next, a more specific embodiment will be described using FIG. 2. Address decoder 100 decodes an address and outputs the decode result to a word line (decode result output line) that is its output. Further, a detection fi 210 that can be electrically connected to the word line 110 and detects access to the relief area, and a gate 411 that inverts the logic of the detection line)
Based on the data stored in the memory cell array 300 and the output of the gate 411, a fixed value of 110 is determined only when accessing the relief area.
The configuration includes a gate 410 that outputs.

The data stored in the memory cell array 300 (ROM) is
It consists of a relief area 320 and a non-relief area 310. Word lines 110b, c, f, g accessing the relief area 320
Connection pattern 2↓1 where only , h, and i are marked with ○ marks in figure 1
It is electrically connected to the detection line 210. The detection line 210 connects all word lines 110b accessing the relief area 320.
,c.

It is an OR logic of f, g, h, and i. therefore,
Accessing the relief area 320 110b.

Any one of the C+ L gt ++ 1 word lines is accessed, causing the detection line 210 to take a logic value of 111 ++. This is input by gate 411 as a logical value II O++ as one input to AND gate 410 . Therefore, the memory cell array 300
Regardless of the data read from the gate 410, the output of the gate 410 will be "0". Therefore, there is a defect in the relief area 320 to which II O++ should originally be output, and the relief area 320
Even if the data actually written in the memory cell array contains rr 1 ++, the desired data "O++" can be output. Note that the means for reading the data in the memory cell array, such as a sense amplifier, etc. It is omitted in the drawing.

On the other hand, when an arbitrary address in the non-relief area 310 is accessed, the word line 1 accessing the relief area 320
10b, c, ft gt ++ i are all logical value 11
Since it remains at 0 H, the detection line 210 has the logical value 'O
It is n. Therefore, the logic value II I to gate 410
Since ++ is input, the data read from the Lumory cell array 300 is output as is.

FIG. 3 is a diagram showing a configuration example of a connection pattern 211 that connects the word line 110 and the detection line 210 in FIG. 2. The connection pattern is composed of a connection diode 250, and the detection line 210 is grounded via a resistor 260 with a high resistance value.

When the word line 110c connected to the detection line 210 is selected, the word line driver 1 in the address decoder 100
11 (but omitted in Figure 2) to connection diode 25
A current flows through the detection line 210 through 0. As a result, the potential level of the detection line 210 becomes High, and access to the relief area can be detected as a logic value of 1.

FIG. 4 is a diagram showing another example of the configuration of the connection pattern. The connection pattern is composed of a connection transistor 251, and the detection line 210 is connected to the power supply via precharge 1 to transistor 261. The detection line 210 is kept at a high level in advance by a precharge transistor 261. When the word line connected to the detection line 210 is selected, a voltage is applied to the gate of the connection 1 transistor 251 via the word line driver 111, and the connection 1 transistor 251 is turned on. As a result, the detection line 210 is discharged and the potential level becomes Low, and access to the relief area can be detected as a logic value 1 via the inverter 212.

Note that, as a further example of the configuration of this connection pattern, it is of course possible to configure it using memory cells, as will be described later.

As described above, according to this embodiment, the memory cell array 30
Regardless of the arrangement of the stored 0 data, the O defect relief area can be selected in units of address decoder outputs.

In order to obtain the same effect as the present invention using the above-mentioned prior art method, it is necessary to have one extra address decoder for relief with the same configuration in addition to the address decoder for accessing the ROM. . When configuring this address decoder, for example, IMbit (8 bits x 12
8 word configuration) In a ROM, if the transistor is placed at the intersection of the address line and the data line, then
2.125M transistors are required. However, in the configuration of the above-described embodiment, 128 transistors are sufficient, which is 1/17 of the conventional technology.

Note that among the above-mentioned components, the address decoder 100
．． Memory cell array 300. It goes without saying that the reading means 302 can be constructed using conventionally known techniques.

FIG. 5 shows another embodiment of the invention. In this example, the second
This is a modification of the embodiment shown in the figure, and is an embodiment in which a defect in a region consisting only of tr 1 n of a memory cell array is relieved. The difference in structure from the embodiment shown in FIG. 2 lies in the gates 420 and 421.

The operation is almost the same as the embodiment shown in FIG.
II is output from gate 420. Even if LL O11 is mixed in the data written in this way, the desired data "1" can be output.

FIG. 6 shows another embodiment of the invention. This embodiment is a combination of the above two embodiments, and is originally "0'".
Defects in the region 320 where `` should be continuous and originally It I
II relates to the case where both defects in the region 330 that should be continuous are repaired.

Of the word lines 110 that are the output of the decoder 100, O
Word lines 110f and 110g for accessing the relief area 320
A detection line 210 for detecting access to the O relief region electrically connected to +h, i, and a gate 431.1 for inverting the logic of this detection line 210; word lines 110b, c for access to the relief region 330; A detection line 220 for detecting access to the relief area electrically connected to the gate 432 . It is configured to include a gate 430 that outputs a fixed value ``0'' or ``1'' only when accessing a relief area based on the data stored in the memory cell array 300 and the outputs of gates 431 and 432. 310 of the regions in the memory cell array are non-relief regions.

By accessing the O relief area 320 at an arbitrary address, the detection line 210 becomes the logical value 111 +7, and the gate 4
31 is input to the composite gate 430 as a logic value "'O". Therefore, regardless of the data read from the ROM or the output of the gate 432, the output of the composite gate 430 will be 0''. Therefore, even if there is a defect in the O relief area 320, which should originally output “'O”, it can be relieved. can do.

Similarly, by accessing any address in the 1-relief area 330, the output of the composite gate 430 becomes II II II, regardless of the data read from the ROM.

Therefore, even if there is a defect in the 8/1 relief area 330 where 111 II is originally output, it can be relieved.

FIG. 7 shows another embodiment of the present invention. This embodiment is an example in which one word is divided into a plurality of fields and repair is performed in units of fields.

One word of 16 bits is composed of four fields of 4 bits each, and a detection line 210 or 220 and fixed value output means 400 are provided corresponding to each field. Fixed values are determined for each field as O relief field and 1 relief field. Connections 211 and 221 between the detection line and the word line make it possible to select relief in field units, so O relief field 320.1 relief field 330,
It becomes possible to mix non-relief fields 310. Moreover, each fixed value output means is capable of not only O relief and 1 relief but also relief of a pattern in which II Ou and 1'' are mixed, depending on the circuit configuration.

In this embodiment, one word consists of four fields of 4 bits each, and the bit width of each field is equal, but the bit width of each field and the number of fields in a word can have any configuration. .

According to this embodiment, one
Divide a word into multiple fields and set relief or non-relief using this field as a unit.

It is possible to set a fixed value at the time of rescue.

FIG. 8 shows another embodiment of the present invention. In this embodiment, an area to be relieved (relief field) and an area not to be relieved (non-relief field) coexist in one word, and the division of both fields is programmable. Note that the area to be relieved is the O relief field.

Detection line 230, which detects access to the O relief area and which is electrically connectable to word line 110 which is the output of decoder 100, detects Ii! Gate 4 that inverts the logic of 230
41) Always logical value II regardless of the logical value of the detection line
Gates 442° and 441 and 4 output II.
443) A gate 440 outputs a fixed value corresponding to the relief field only when the relief area is accessed from the data stored in the memory cell array 300 and the contents of the relief field program area 443. be done.

By accessing an arbitrary address in the O relief area 320, the detection line 230 becomes the logical value II II II. this is,
It is input by gate 441 to relief field program area 443 as a logic value it O'''.

Further, the gate 442 always inputs the logic value "'1" to the relief field program area 443.

(This can also be supplied by other means such as a power supply.) In the relief field program area 443:
A connection pattern 444 connects the output of gate 441 or 442 to the input of gate 440. When the output of the gate 441 is connected, it becomes a relief field, and when the output of the gate 442 is connected, it becomes a non-relief field. Therefore, when the relief area is accessed, the output of the gate 4.40 becomes II OII only in the range designated as the relief field, regardless of the data read from the ROM. Otherwise, the contents of the ROM are output as is. Therefore, even if there is a defect in the relief field of the O relief region 320, it can be relieved.

It goes without saying that the connection pattern 444 in the relief field program area can have a configuration as shown in FIG. 3 or FIG. 4 above. Furthermore, it can also be configured by a simple ohmic connection of metal wiring.

FIG. 9 is a diagram showing an embodiment in which the O relief field in the embodiment shown in FIG. 8 is changed to a 1 relief field.

A detection line 240 for detecting access to one relief area, which is electrically connectable to the word line 110 which is the output of the decoder 100, and a gate 451 for transmitting the logic of the detection line 240.
) Always logical value LL regardless of the logical value of the detection line OII
A gate 452 that outputs a program area 45 that sets a relief field from the outputs of gates 451 and 452.
3. It consists of a gate 450 that outputs a fixed value corresponding to the relief field only when the relief area is accessed from the data stored in the memory cell array 300 and the contents of the relief field program area 453.

It operates similarly to the embodiment shown in FIG.
It is possible to recover even if there is a defect in the relief field.

FIG. 10 is a diagram showing an embodiment in which the embodiments shown in FIGS. 8 and 9 are combined.

As shown in FIG. 10, in order to combine the field relief of the O relief area similar to the embodiment of FIG. 8 and the field relief of the one relief area similar to the embodiment of FIG. A composite gate 460 is used as in the example.

FIG. 11 is a diagram showing an embodiment in which the embodiments shown in FIGS. 6 and 10 are combined.

As shown in FIG. 11, relief of the O relief area and the work relief area similar to the embodiment of FIG. 6, and field relief of the O relief area and field relief of the 1 relief area similar to the embodiment of FIG. In order to combine these, multistage composite gates 460 and 470, which are expanded versions of the composite gate of the embodiment shown in FIG. 6, are used.

FIG. 12 is a diagram showing a modification of the embodiment shown in FIG.
1, 221, 231, 241) That is, this is an embodiment in which the selection detection means is configured as a part of the memory cell array 300. In other words, the selection detection means is the memory cell array 3.
This is an example configured with a ROM similar to the ROM cell in 00.

The arrangement of relief and non-relief areas in the memory cell array is as follows:
Same as in the figure.

As shown in FIG. 12, the detection lines 210, 220° 230
．． Detection column 215°225.23 instead of 240
5,245 was established. Data in the detection column is also read during memory access. still.

Means for reading data from the detection column, such as a sense amplifier, are omitted in the drawings. The data in the detection column indicates whether the accessed word is in the respective relief area by '1''rr O++, and these data are transmitted as they are to the fixed value output means.

According to this embodiment, the same effect as the embodiment shown in FIG. 11 described above can be easily obtained by only slightly increasing the bit width of the memory cell array.

Further, the word line selection detection means 200 of this embodiment can be provided in any part of the memory cell array. Furthermore, it is also possible to provide it outside the memory cell array.

FIG. 13 is a diagram showing an embodiment in which the address decoder is composed of a row decoder 101) and a column decoder 102.

As shown in FIG. 13, of an address consisting of, for example, 12 bits, the upper 8 bits are input to the row decoder 101 and the lower 4 bits are input to the column decoder 102, where they are respectively decoded. The output of the row decoder appears on word line 110 and the output of the column decoder appears on bit line 115.

The data stored in memory cell array 300 is as follows.

It is read by a combination of word line 110 and bit line 115. Therefore, word/I/bit line selection detection means 201 is provided to be coupled to word line 110 and bit line 115 to detect access to the relief area.

The detection result is sent to the fixed value output means 4 via the detection signal line 120.
00, and defect relief is performed.

According to this embodiment, even when an address decoder is composed of a row decoder and a column decoder, the same effects as those of the above-described embodiments can be obtained.

FIG. 14 is a diagram showing an example in which an electrically writable EPROM is used as the memory cell array 300. In this embodiment, not only the memory cell array 300 but also the selection detection means 200 are constructed of EPRON, but one of them may be a normal ROM (mask ROM).

As shown in FIG. 14, in this embodiment, the data buffer 7
In response to the data latched to 00 and the write control signal 730, the high voltage V
A write circuit 720 that converts pp into a write control high voltage Vpp', a relief circuit that determines whether a pre-prepared relief condition matches the data launched into the data buffer 700, and outputs a relief condition fulfillment signal 740 to the selection detection means 200. A determination circuit 710 is added.

In this embodiment, the write control signal 730 is
When it is I++, it is a data write state to the memory cell, and when it is gL O++, it is a data read state. When the write control signal 730 is in the data write state (11171), the write circuit 720
High voltage Vpp for write control, which is obtained by dividing high voltage Vpp
is generated and supplied to selection detection means 200 and memory cell array 300. Note that the write control signal 730 is
In the case of IQ++, that is, in the data read state, Vpp is not output.

The memory cell array 300 writes the value held in the data buffer to the selected address of the word line from Vpp, Vpp'L knee.

On the other hand, the relief determination circuit 710 holds a data pattern as a relief condition and compares it with the data latched in the data buffer. More specifically, the number of comparators equal to the number of bit widths of data supplied from the data buffer and the AND of the outputs of these comparators are A.
It is configured including an ND circuit. The output of this AND circuit is output as a relief condition fulfillment signal. One input of each comparator is information on each bit of data supplied from the data buffer, and the other input is information on each bit of data representing a preset relief condition. The data representing the relief condition is, for example, all bits O when the O relief area mentioned in the previous embodiment is to be relieved. When the data supplied from the data buffer and the data representing the relief condition match, all comparators detect the match,
Therefore, a relief condition fulfillment signal 740 is output.

This is transmitted to the selection detection means 200.

In the selection detection means 200, when data is being written and the relief condition fulfillment signal 740 is enabled, information regarding the connection between the word line selected by the address decoder 100 and the detection line is set to Vpp+Vpp'.
Write using.

FIG. 15 is a diagram showing an example of the configuration of the selection detection means 200 in FIG.
1 shows an arrangement for forming connections between 10;

In the write state, the write control signal 730 is “
1", and the gate T r 283 is turned on. When the word line 110 in the figure is selected in this state, the output of the AND gate 281 becomes "1", and the gate T r 282 is turned on. In order to turn on, the high voltage Vpp is
Applied to the gate of PROM memory cell 270. Furthermore, the relief condition is satisfied and the relief condition fulfillment signal 740 becomes 111.
71, the gate Tr280 is turned on, so that the write control high voltage Vpp' is applied to the drain of the EPROM memory cell 270 via the gate Tr283. As a result, electrons are trapped in the bloating gate of the EPROM memory cell 270, and the connection between the word line and the detection line is programmed.

Next, in the read state, the write control signal 73
Since 0 is “OIJ”, gate Tr284,2
85 is ON. Also, in this state, the gate Tr
282 and 283 are OFF. When the word line 110 in the figure is selected by accessing the ROM, the gate Tr28
5, current flows to the gate of the EPROM memory cell 270, and the gate potential becomes High. Gate T at the same time
Since r286 is also turned ON, the charge of the detection line 210, which has been precharged to Vcc, is transferred to the gate Tr286.
, 284 to the drain of EPROM memory cell 270.

When the EPROM memory cell 270 is programmed to "1", that is, when electrons are trapped in the floating gate, the EPROM memory cell 270 will not turn on even if a gate bias is applied, so the detection line 210 will not turn on. The potential is maintained. This would mean access to relief areas. FIG. 15 shows the case where the O relief area is specified, and the logic value of the detection line 210 is inverted to be the logic value of the detection signal line.

Mata, EPROM mail T-IJ-t'#270 is 11
Q71 When nibprogrammed, that is, when no electrons are trapped in the floating gate, the E P ROM memory cell 270 is turned on, so
Charges are discharged from the detection line 210, and the potential decreases. This means access to non-relief areas.

According to this embodiment, it is possible to set a relief area at the same time when writing data to the EPROM memory cell array.

Further, according to this embodiment, it is possible to set a defect relief area even after the semiconductor memory device is manufactured. Therefore, it is also possible for the user to set a relief area.

FIG. 16 is a diagram showing an embodiment in which the connection between the decoding result output line 110 and the detection line 210 in the selection detection means 200 is made programmable. Selection detection means 20
0 contains the connection pattern control signal 205. and connection pattern clear signal 206 are input.

FIG. 17 is a diagram showing an example of the configuration of the selection detection means 200 in FIG. 16. IL L connection pattern control signal 205
By setting i to the write state where information regarding the connection between the word line and detection line can be written
By setting t On, the memory cell array 300 is brought into an exposed state where it can be read.

In the write state, the gate Tr290 is ON, so when the word line 110 in the figure is selected by accessing the ROM, the logic value 111 ++ is lowered from Vcc.
is taken into latch 292 via gate 296 in synchronization with the clock signal. Note that data is not written to the memory cell array at this time.

In the read state, the gate Tr294 is ON. Word 111 in the figure is accessed by ROM access.
When 0 is selected, Tr293 is turned on to game 1,
The charge on the detection line 210 precharged to Vcc passes through the gate Tr293 and 294 to the gate Tr2.
Flows to the drain of 95.

When the latch 292 is programmed to 1'1'', the gate Tr 295 is OFF, so the potential of the detection line 210 is maintained. This means access to the relief area.

When the latch 292 is programmed to "O++", since the gate T r 295 is ON, charges are dissipated from the detection line 210 and the potential decreases. This means access to the non-relief area.

Furthermore, by enabling the connection pattern clear signal 206, all latches associated with each word line can be reset in synchronization with the clock signal.

FIG. 18 is a block diagram of a logic LSI (microcomputer) that incorporates the read-only semiconductor memory device of the present invention and is integrated on an l chip. The semiconductor memory device of the present invention explained through the above embodiments can be used as part of a logic LSI such as a microcomputer.

The logic LSI 500 includes a CPU 510. RAM520
, a ROM 530 which is a semiconductor memory device of the present invention, and these are connected to an address bus 560 and a data bus 5.
70. Communication with the outside is performed via address buffer 540 and data buffer 550. By using the ROM530 of the present invention, the conventional ROM
It is possible to repair a logic LSI chip that has become defective only due to the defect, and the yield can be improved.

In this embodiment, the write control signal 730. shown in FIG. Connection pattern control signal 20 shown in FIG.
5 and the connection pattern clear signal 206 can be generated under the control of the CPU 510 on the chip. Of course, these signals can also be input from outside the microcomputer chip via pins.

〔Effect of the invention〕

According to the present invention, since access to the relief area is detected from the decoding result output line, defect relief can be realized with a smaller number of elements than in the past. In addition, since the defect relief area can be selected in units of the decoded output of the address decoder (for example, word by word), the size and number of relief areas are not restricted.Furthermore, the configuration of the fixed value output means The degree of freedom of selection can be further increased.

[Brief explanation of drawings]

1 and 2 are configuration diagrams of a semiconductor memory device according to an embodiment of the present invention, FIGS. 3 and 4 are diagrams showing an example of the configuration of a connection pattern, and FIG. FIG. 6 is a block diagram of a semiconductor memory device according to a modified embodiment of the example. FIG. 6 is a block diagram of a semiconductor memory device according to a modified embodiment that combines the embodiments shown in FIGS. 2 and 5. FIG. 8 and 9 are configuration diagrams of semiconductor memory devices of modified embodiments for performing relief.
The figure is a block diagram of a semiconductor memory device of a modified embodiment in which field division is programmable, and FIG. 10 is a block diagram of a semiconductor memory device of a modified embodiment that combines the embodiments shown in FIGS. 8 and 9. FIG. 11 is a block diagram of a semiconductor memory device according to a modified embodiment that combines the embodiments shown in FIGS. 6 and 10, and FIG. 12 is a semiconductor memory device according to a modified embodiment in which selection detection means is configured by memory cells. FIG. 13 is a configuration diagram of a semiconductor memory device according to a modified embodiment using a ROM that can be written in column D; FIG. 15 is a diagram showing an example of the configuration of the selection detection means in FIG. 14; 17 is a diagram showing a configuration example of the selection detection means in FIG. 16, and FIG. 18 is a diagram showing a semiconductor memory device according to a modified embodiment in which the selection detection means is programmable. FIG. 2 is a configuration diagram of a built-in microcomputer. 100... Address decoder, 101... Row address decoder, 102... Column address decoder, 110
...Decoding result output line (word line), 111...
Word line driver, 115...Bit line, 120...
・Detection signal line, 200...word line selection detection means, 2
01... Word line/bit line selection detection means, 205.
・Connection pattern program control signal, 206...Connection pattern clear signal, 210, 220, 230°2
40...Detection line for detecting access to the relief area, 21
1.221,231,241.4-4.4,454 connection pattern, 212...Inverter, 215°225.
235, 245...Column for detecting access to relief area, 250...Connection diode, 251...Connection transistor, 260...Resistor, 261...Precharge transistor, 270...EPROM memory cell , 300...Memory cell array, 301...Bank selector, 302...Read circuit (sense amplifier)
, 310...non-relief area, 320...0 relief area, 3
30...1 relief area, 400...fixed value output means,
410,420,430,440,450°460.4
70...Gate that outputs a fixed value when accessing the relief area, 4.11, 431, 441...Gate that inverts the logic of the detection line, 421,432°451...Gate that transfers the logic of the detection line , 442... always logical value u 1
Gate that outputs ++, 452... always logic value II
Gate outputting O++, 443°453... Relief field program area, 500 logic LSI, 5
10...CPU, 520...RAM, 530...
ROM, 540...address buffer, 550...
Data buffer, 560/address bus, 570...
Data bus, 580...Address port, 590...
・Data port, 700...Data buffer, 710
... Relief judgment circuit, 720 ... Write circuit, 730
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Claims (1)

[Scope of Claims] 1) Information storage means comprising a plurality of semiconductor memory elements, address decoding means for decoding an address signal to access at least one element of the plurality of semiconductor memory elements, and decoding by the decoding means. A semiconductor memory device characterized by comprising an output control means for outputting a predetermined value regardless of the contents stored in the semiconductor memory element in response to the result. 2) The output control means includes selection detection means coupled to at least one of the plurality of output lines of the address decoding means, reading means for reading out information stored in the information storage means, and selection detection means. 2. The semiconductor memory device according to claim 1, further comprising control means for outputting predetermined information when said selection is detected. 3) The semiconductor memory device according to claim 2, wherein the control means outputs the information from the reading means when the selection detection means does not detect a selection. 4) The semiconductor memory device according to claim 1, wherein the semiconductor memory element is a mask ROM. 5) The semiconductor memory element is an electrically writable RO
4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is M. 6) a memory matrix consisting of a plurality of semiconductor memory cells arranged in a matrix; an address decoder that decodes address signals and generates a signal specifying a predetermined area in the memory matrix; a readout circuit that reads out information; a selection detection circuit that detects that at least a part of the signal generated by the address decoder is selected; and a selection detection circuit that detects predetermined information when the selection detection circuit detects selection. A semiconductor memory device comprising a control circuit that outputs information from the read circuit when not in use. 7) The semiconductor memory device according to claim 6, wherein the address decoder generates a plurality of output signals specifying memory cells in the memory matrix in units of words. 8) The semiconductor memory device according to claim 7, wherein the selection detection circuit is coupled to at least one of the plurality of output signals. 9) Among the memory cells in the memory matrix, the memory cell designated by the at least one output signal line is a memory that should originally store either a value of "0" or "1". 9. The semiconductor memory device according to claim 8, wherein the semiconductor memory device is a cell. 10) The area specified in units of words is further divided into a plurality of areas, and the control circuit is configured to provide predetermined information to each of the divided areas when the selection detection circuit detects selection. 7. The semiconductor memory device according to claim 6, wherein information from said readout circuit is output when not detected. 11) The selection detection circuit detects selection for each of the plurality of divided regions, and the control circuit detects a predetermined selection for each of the divided regions when the selection detection circuit detects selection. 11. The semiconductor memory device according to claim 10, wherein when the information is not detected, the information from the readout circuit is output. 12) The semiconductor memory device according to claim 7, wherein the selection detection circuit is coupled to at least two of the plurality of output signals. 13) Among the memory cells in the memory matrix, the memory cell designated by one of the at least two output signal lines is originally "0", and the memory cell designated by the other is originally "0". 13. The semiconductor memory device according to claim 12, wherein the memory cell is a memory cell in which a value of 1'' is to be stored. 14) The address decoder includes a first decoder that generates a plurality of output signals that specify memory cells in the memory matrix in units of words, and a second decoder that generates a plurality of output signals that specify memory cells in the memory matrix in units of bits. 7. The selection detection circuit is coupled to at least one of the plurality of output signals of the first decoder and at least one of the plurality of output signals of the second decoder. semiconductor storage device. 15) The semiconductor memory device according to claim 6, wherein the control circuit is constituted by a logic gate element that responds to a signal from the readout circuit and a signal from the selection detection circuit. . 16) The semiconductor memory device according to claim 15, wherein the control circuit is constituted by a number of logic gate elements corresponding to the number of bits in the specified area. 17) Claim 1, wherein the selection detection circuit includes a detection line grounded through a resistor, and a diode connected between the detection line and the output signal line of the address decoder. 17. The semiconductor memory device according to any one of 16 to 16. 18) The selection detection circuit includes a precharged detection line and a transistor connected between the detection line and the output signal line of the address decoder, and the gate of the transistor is connected to the output line and the 17. The semiconductor memory device according to claim 1, wherein one of a source and a drain of the transistor is connected to the detection line. 19) The selection detection circuit comprises a detection semiconductor memory cell specified by the output signal of the address decoder and a detection readout circuit that reads information stored in the detection semiconductor memory cell. 17. The semiconductor memory device according to any one of Items 1 to 16. 20) The semiconductor memory device according to claim 19, wherein the detection semiconductor memory cell constitutes a memory cell array together with the plurality of semiconductor memory cells arranged in a matrix. 21) The semiconductor memory device according to claim 1, wherein the semiconductor memory cell is constituted by a mask ROM. 22) The semiconductor memory device according to claim 1, wherein the semiconductor memory cell is constituted by an electrically writable ROM. 23) The semiconductor memory device according to claim 19 or 20, wherein the semiconductor memory cell and the detection semiconductor memory cell are constituted by a mask ROM. 24) The semiconductor memory device according to claim 19 or 20, wherein the semiconductor memory cell and the detection semiconductor memory cell are constituted by an electrically writable ROM. 25) The semiconductor memory device according to claim 22 or 24, wherein the semiconductor memory device further includes a write circuit for the electrically writable ROM. 26) A microcomputer, characterized in that it incorporates the semiconductor memory device according to any one of claims 1 to 25 and is formed into a single semiconductor chip. 27) The microcomputer according to claim 26, wherein the logic LSI includes a CPU, the semiconductor memory device, and a bus connecting the CPU and the semiconductor memory device.