JPH07111096A - Mask rom device with relieving function - Google Patents

Abstract

PURPOSE:To provide a mask ROM device with relieving function which can effectively relive a defective bit by relieving a few bits without replacing a row or a column of a defective cell, as a defect relieving circuit using replacement of redundant data of a mask ROM. CONSTITUTION:In a mask ROM device constituted of an address buffer 10, a X-decoder 11, a Y-decoder 12, a mask ROM 13, a Y-selector 14, a sense amplifier 15 and an output buffer 20, a correcting circuit 19, a PROM 16, a PROM decoder 17 and a sense amplifier 18 are provided. An output signal of the mask ROM of a word including a defective bit caused by a defective cell of the mask ROM and a correcting signal of the PROM correcting the defective bit are inputted to a correcting circuit, and the defective bit is corrected in accordance with a correcting instruction instructed by the correcting signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM for writing data in a manufacturing process of a semiconductor memory, and more particularly to a mask ROM device with a relief function for relieving defective bit products and improving yield.

[0002]

2. Description of the Related Art An example of a conventional mask ROM device with a relief function will be described with reference to the invention disclosed in Japanese Patent Laid-Open No. 2-201800. FIG. 7 is a block diagram of an embodiment of the invention described in JP-A-2-201280.

The present invention is an invention of a semiconductor memory device, in which data is fixed in advance in a mask ROM 116, and the fixed data is read according to an address signal. PR
The OM 123 is a rewritable and non-volatile memory. The command means 112 outputs the address signal to the mask ROM 11
When it coincides with the redundant address indicating the defective cell of 6, the switching command signal is output. The selection circuit 125 normally selects the fixed data, and when the switching command signal is output from the command means 112, selects the data from the PROM 123 and outputs the selected data via the output circuit 126. .

In the above structure, the mask ROM
When a defective cell is found in 116, an address indicating a row or a column including the defective cell is set in the redundancy judgment circuit 113,
The same data as data to be written to the cell array for one row or one column including the defective cell (redundant data)
Is supplied to the write control circuit 119 and written in the PROM 123. Then, when an address signal indicating a row or a column including a defective cell is input, the selection circuit 125 switches to reading from the PROM in response to a switching command signal output from the commanding unit 112 to repair the defect. A plurality of rows or columns to be relieved can be set as necessary.

The PROM can be configured by using a polysilicon fuse type in which a large current is caused to flow and blow it out, or an EPROM in which charges are injected into a floating gate for writing, but since it becomes a field programmable logic array, it is written. Embedded circuits tended to be complicated.

On the other hand, a polysilicon fuse which is blown by a laser has an advantage that a writing circuit is unnecessary and the circuit structure is simple. This writing is a method in which the address of the defective bit is stored in the floppy disk of the measuring device at the time of wafer measurement (P / W) and cut by the laser trimmer.

[0007]

When the LSI has a high degree of integration and the chip size becomes large, bit defects due to dust and defects frequently occur. In the mask ROM relief circuit by replacing the redundant data according to the conventional technique, 16M
In case of bit mask ROM, PROM for one row is 4k
Since it also becomes bits, the size of the PROM becomes large.
In addition, the effective chip decreases as the chip size increases by about 10%. In particular, even in the case of a 1-bit defect that occupies 99% of defects contained in 1 word, data for 1 row needs to be written, and a large number of repair cells are required.

In the case of a polysilicon fuse which is blown by a laser, a defective product cannot be obtained due to a write error of 0.1% × about 2 k bits. Further, the writing time becomes as long as 1 to 2 hours per wafer, many writing failures occur, defects are likely to occur in the relief process itself, and the writing yield decreases, which makes practical application difficult.

In view of the above points, the present invention has an object to provide a mask ROM device with a relief function capable of effectively relieving a bit defect by relieving a small number of bits.

[0010]

A mask ROM device with a relief function of the present invention is a mask ROM device having a mask ROM including a defective cell and the address of the defective cell is known in advance. Mask RO with a relief function that outputs a correct signal in which the defective bit is corrected
An M device having a programmable repair memory, a programmable decoder, and a correction circuit, wherein the address of the defective memory in the repair memory is determined to correspond to the address of the defective cell. A correction signal for instructing the correction of a defective bit caused by is written in advance, and an address of a mask ROM in which a word including a defective bit is written is written in advance as a defective address in the decoder to specify the address. When the address signal is input, the decoder outputs a decode signal for selecting the word line of the relief memory cell in which the correction signal for correcting the defective bit is written, and the correction circuit outputs the mask ROM output signal and the mask ROM output signal. A correction signal is input and the defective bit is corrected according to the correction instruction indicated by the correction signal.

[0011]

In the relief of the bit defect of the present invention, the output 1
By correcting only the defective bit portion on a word-by-word basis, it is possible to effectively repair the defective bit by repairing a small number of bits.

Further, by writing and correcting only the portion corresponding to the defective bit, the writing portion can be reduced, that is, the writing failure and the writing time can be reduced.

Furthermore, bit defects that are concentrated in a partial area of the cell array due to dust or defects can be replaced in block units in accordance with the bit arrangement of the layout, so that defective bit clusters can be obtained. The part can be corrected, and the correction can be simplified.

From the above, by effectively repairing defects with a small number of bits, the bit capacity can be reduced, the increase in chip size can be suppressed by 1 to 2%, and the repair of bit defects is 10 to 20. % Yield improvement can be expected.

[0015]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a mask ROM device to which the present invention is applied. In FIG. 1, the mask ROM device is an address buffer 10, X-
Decoder 11, Y-decoder 12, mask ROM 13,
Y-selector 14, sense amplifier 15, output buffer 2
It is composed of 0s.

Further, a correction circuit 19, a PROM 16, a PROM decoder 17, and a sense amplifier 18 are provided to correct the defective bit. The correction circuit 19 reads the signals (S ₀ , S ₁ , ...) From the mask ROM 13.
, S _k ) and the correction signal C (C ₀ , C ₁ , ..., C _k ) are input, and the signal S _x read from the defective bit x of the mask ROM 13 is corrected and output. Here, assuming that the address of the PROM 16 is the correction address, the PROM decoder 1
7 is an address signal (A ₀ , A ₁ , ...) Of the mask ROM 13.
, A _m ), and the PRO bit corresponding to the defective bit x
The corrected address y of M16 is designated. Here, if the high level of the signal is H level and the low level is L level, the correction address y of the PROM 16 stores the correction signal C _y of H level, and the correction signals C _j of L level are stored at the other addresses. (J = 0, 1, ..., k, where j ≠ y)
Is stored. The sense amplifier 18 is the PROM 16
The signal read from is amplified and output to the correction circuit 19.

2, 3 and 4 are circuit diagrams of the correction circuit elements constituting each bit of the correction circuit 19. Here, if the bit that should originally be at the L level is the mask R
When the H level is indicated due to the defect of the OM13, the L
If the level bit is defective, and the bit that should originally be at the H level indicates the L level due to a defect in the mask ROM 13, it is considered as the H level bit defect.

FIG. 2 is a diagram showing a correction circuit element for correcting an input signal having an L level bit defect. I of correction signal C
When the th bit C _i is at the H level, that is, when the correction signal C _i is the data read from the correction address, when the H level input signal S _i is input, the L level is output from the AND gate. Is output. Therefore, the L-level defective bit input signal S _i is corrected to the L-level signal. On the other hand, the correction signal C _i is L
In the case of the level, the input signal S _i is not corrected and is output as it is. Table 1 is a truth table of the circuit elements of FIG.

[0019]

[Table 1] FIG. 3 is a diagram showing a correction circuit element for correcting an input signal having an H level bit defect. Also in this circuit, when the correction signal C _i is at the L level, the input signal S _i is not corrected and is output as it is from the OR gate. However, when the correction signal C _i is at the H level, the L level input signal S _i
A high-level signal B _i is output for Therefore, the input signal S _i having the H-level bit defect is corrected to the H-level signal. Table 2 is a truth table of the circuit elements of FIG.

[0020]

[Table 2] As is clear from the fifth row from the top of Table 1, the circuit of FIG. 2 cannot correct the input signal (L level) having an H level bit failure. Further, as is clear from the fourth row from the top of Table 2, the circuit of FIG. 3 cannot correct the input signal (H level) having the L level bit failure.

FIG. 4 is a diagram showing a correction circuit element capable of correcting both an input signal having an H level bit defect and an L level bit defect. This circuit is configured by connecting a transfer gate G ₁ and a transfer gate G ₂ in parallel. Of these, Transfer Gate G
₁ transfers the inverted signal of the input signal S _i , and the transfer gate G ₂ transfers the input signal S _i . On-off control of the transfer gates G1, G2 are carried out by the correction signal C _i, the correction signal C _i is the transfer gates G ₁ when the H-level to turn on the transfer gate G ₂ is turned off. As a result, the inverted signal of the input signal S _i is output from the transfer gate G ₁ as a corrected signal.
When the correction signal C _i is at L level, the transfer gate G ₁ is turned off and the transfer gate G ₂ is turned on. Therefore, the input signal S _i is directly output from the transfer gate G ₂ without being corrected. As a result, regardless of whether the input signal S _i is the input signal with the H level bit failure or the L level bit failure,
The corrected signal B _i is output. Table 3 is a truth table of the circuit elements shown in FIG.

[0022]

[Table 3] In FIGS. 2, 3 and 4, an example in which the defective bit is corrected when the correction signal C _i is at the H level is shown, but it is realized by a circuit which corrects the defective bit when the correction signal C _i is at the L level. It is also possible.

From the above, the operation in the configuration of FIG. 1 will be described. When a bit defect occurs, the address of the defective bit is set in the PROM decoder 17, the polysilicon fuse is blown by the laser, and the H level is written in the PROM cell at the position corresponding to the position of the output bit. Thus, by specifying the address of the defective bit, it reads the data of the PROM cell of the address through the sense amplifier 18, since the correction signal C _i which corresponds to the defective bit output O _i is H level, correcting the input signal S _i The output signal B _i is output, and correct data is output to the output O _i through the output buffer 20.

Another embodiment of the correction circuit 19 in FIG. 1 will be described. FIG. 5 is a diagram showing an example of an H level or L level forcible correction circuit of the output. In FIG. 5, by adding 1 bit of information P of output H-level bit failure or L-level bit failure for each word of output k bits to form a (k + 1) -bit PROM cell, 1
A 1-bit H-level bit defect or L-level bit defect is corrected for each word. Here, the inverted output of the information P is P ^* .

In the embodiment of FIG. 5, the information P is set to the H level when the H level bit is defective and is set to the L level when the L level bit is defective. Therefore, the AND gates, NOR gates, logic synthesized P · C _i by a logic circuit composed of the inverter from the information P and correction signal C _i, P ^* · C _i are all in the case the correction signal C _i is at L level Also becomes L level. Therefore, the input signal S _i is output as the signal B _i without being corrected. When the correction signal C _i is H level and the information P is H level, the H level signal B _i is output. Therefore, the input signal S _i (L level) having the H level bit defect is corrected. Further, when the correction signal C _i is at the H level and the information P is at the L level, the L level signal B _i is output. Therefore, the input signal S _i (H level) having the L level bit defect is corrected. Thus, when there is a bit defect for a 1 word, the correction signal C _i to H level, when the information P is at H level, the signal of the H level correcting the input signal S _i of H level bit defects B _i There is outputted, the information P is at L level, L level of the signal B _i correcting the input signal S _i of L level bit failure is output. It may be combined into one without creating P · C _i and P ^* · C _i output bits of k min of the logically synthesized signal information P and correction signal C _i. If there are defects of 2 bits or more for one word, and H level bit defects and L level bit defects coexist, FIG.
It cannot be corrected by the circuit of. Although the case of correcting one word has been described with reference to FIG. 5, it is also possible to correct a plurality of output words having continuous addresses as one block.

FIG. 6 is a diagram showing a circuit example of the PROM block. In FIG. 6, the address of the defective bit is "A _{0.
= L, A 1 = H,} A 2 = L, ......, and A _m = L ", the other with H level only A ₁ will be described for the case all at the L level. The inverted output at this time, A _m Assuming A _m ^* , the polysilicon fuses of the transistors in the decoder section whose base inputs are A ₀ ^* , A ₁ , A ₂ ^* , ..., A _m ^* are blown to be in an open state. When an address is input, the output X _i becomes H level and the PROM cell of X _i is selected.The output corresponding to the above address is O ₁
Then, the polysilicon fuse of the transistor at the intersection of X _i and D _{1 of the} cell portion is blown to open. Thus, only the inner C ₁ of the correction signal C which is the output of the sense amplifier corresponding to the transistor becomes H level, all others to L level.

[0027]

According to the present invention, in repairing a bit defect,
Since only the defective bit portion is corrected in units of one output word, it is possible to effectively repair the defective bit with a small number of bits.

Further, since only the portion corresponding to the defective bit is written and corrected, the writing portion can be reduced, that is, the writing failure and the writing time can be shortened.

Further, since the bit defects generated in a partial area of the cell array due to dust and defects can be replaced in block units corresponding to the bit arrangement of the layout, the defective bit cluster portion can be replaced. Can be corrected and the correction can be simplified.

From the above, a defect can be effectively remedied with a small number of bits, so that the bit capacity can be reduced and the increase in chip size can be suppressed by 1 to 2%.
Relieving a bit defect has an effect that a yield improvement of about 10 to 20% can be expected.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a mask ROM device to which the present invention is applied.

FIG. 2 is a diagram showing a correction circuit element for correcting an input signal having an L level bit defect.

FIG. 3 is a diagram showing a correction circuit element for correcting an input signal having an H level bit defect.

FIG. 4 is a diagram showing a correction circuit element capable of correcting both an input signal having an H level bit defect and an L level bit defect.

FIG. 5 is a diagram showing an example of a forced correction circuit for H level or L level of output.

6 is a diagram showing a circuit example of the PROM block in FIG. 1;

FIG. 7 is a block diagram showing an embodiment of a conventional mask ROM device with a relief function.

[Explanation of symbols]

 10, 111 Address buffer 11 X-decoder 12 Y-decoder 13, 116 Mask ROM 14 Y-selector 15, 18, 117, 122 Sense amplifier 16, 123 PROM 17 PROM decoder 19 Correction circuit 20 Output buffer 112 Command means 113 Redundancy determination Circuits 114, 120 Row decoder 115, 121 Column decoder 119 Write control circuit 125 Selection circuit 126 Output circuit

Claims (10)

[Claims] 1. A mask RO having a mask ROM including a defective cell, the address of which is known in advance.
A mask ROM device with a repair function, which is an M device and outputs a correct signal in which a defective bit due to a defective cell is corrected, having a programmable repair memory, a programmable decoder, and a correction circuit. A correction signal for instructing correction of a defective bit caused by the defective cell is written in advance at an address of the relief memory corresponding to the address of the defective cell, and the decoder includes a word including the defective bit. When the address of the mask ROM in which is written is previously written as a defective address and an address signal designating the address is input, the decoder of the relief memory cell in which the correction signal for correcting the defective bit is written. A decode signal for selecting a word line is output, and the correction circuit outputs the mask ROM output signal. And a mask ROM device with a relief function, wherein the defective bit is corrected in response to a correction instruction indicated by the correction signal. 2. When the bit originally supposed to be at the first logic level is at the second logic level due to a defect in the mask ROM, the defective bit is regarded as the first defective bit, and the second defective bit is supposed to be originally the second defective bit. The bit that should be at the logical level is the mask RO
When the defective bit is the second defective bit at the first logic level due to the defect of M, a signal designating whether to correct the first defective bit or the second defective bit. The mask ROM device with a relief function according to claim 1, wherein is set in advance in the relief cell. 3. When the address area of a plurality of words written in consecutive addresses in the mask ROM is used as a block, writing of a defective address to the decoder and writing of a correction signal to the relief memory are performed in block units. The mask ROM device with a relief function according to claim 1, which is performed. 4. Each cell of the programmable relief memory has a MOSFET, the gate of each MOSFET is connected to a word line selected by a decode signal, and the drain current of each MOSFET is the output of a mask ROM. It is supplied via the bit line corresponding to each bit of the signal, and a program cutting section is provided in the drain current flow path of each MOSFET to program the cell at the address corresponding to the address of the defective cell in the mask ROM. The mask ROM device with a relief function according to claim 1, wherein a correction signal is written in the cutting section. 5. The programmable decoder has, for each programmable word line, a logical product circuit for applying a decode signal to the word line, and the logical product circuit includes:
It has a plurality of MOSFETs connected in parallel to a constant current source, the connecting portion of which is connected to the word line,
A cutting section for programming is provided in the flow path of the drain current of the FET, and the gate of each MOSFET has a mask RO
The program cutting unit is connected to each bit of the address signal and its inverted signal input to M,
2. The mask ROM device with a relief function according to claim 1, which is programmed to activate a word line when an address signal instructing reading of an output signal including a defective bit of an OM is input. 6. The correction circuit has a correction logic circuit for each bit of an output signal of the mask ROM, and the correction logic circuit uses the bit of the output signal of the mask ROM as a first input signal, and the bit concerned. Is used as a second input signal, and when the second input signal has a first logic level instructing correction of a defective bit, the first input signal is corrected and output, The mask ROM device with a relief function according to claim 1, wherein the first input signal is output when the input signal of 1 is at the second logic level. 7. The correction logic circuit outputs a second logic level when the second input signal is at the first logic level, and outputs a first logic level when the second input signal is at the second logic level. 7. The mask ROM device with a relief function according to claim 6, which is a logical product gate circuit that outputs the input signal. 8. The correcting logic circuit outputs a first logic level when the second input signal is at the first logic level, and outputs a first logic level when the second input signal is at the second logic level. 7. The mask ROM device with a relief function according to claim 6, which is a logical sum gate circuit that outputs the input signal. 9. The correcting logic circuit is turned on when the second input signal is at the first logic level, and is turned on when the second input signal is at the second logic level. A second transfer gate, the first and second
Transfer gates are connected in parallel, the first transfer gate receives the inverted signal of the first input signal,
7. The mask ROM device with a relief function according to claim 6, wherein the second transfer gate receives the first input signal. 10. The correction logic circuit defines a bit failure in which a bit for outputting a first logic level outputs a second logic level due to a defect in a mask ROM as a first bit failure, and a second bit failure. If the bit defective in outputting the first logic level is the second defective bit due to the defect in the mask ROM, the bit whose logical level is to be output becomes the first logical level in the case of the first defective bit. , A second logic level when the second bit failure occurs, a third input signal is input, and a first logical combined signal which is a logical product of the third input signal and the second input signal, A logic synthesis circuit for generating a second logic synthesis signal which is a logical product of an inverted signal of the third input signal and the second input signal; a first input signal;
A second logic composite signal is input, the first input signal is output when the second input signal is at the second logic level, and the second input signal is at the first logic level. When the third input signal indicates the first bit defect, the first logic level is output, and when the second input signal is the first logic level, the third input signal indicates the second bit defect. 7. The mask ROM device with a relief function according to claim 6, further comprising a logical sum gate circuit that outputs a second logical level when indicating.