JPH03252841A - Transfer data checking system - Google Patents

Abstract

PURPOSE:To detect the hardware fault in a data transfer state by performing the collation between the data on a transfer bus and the data stored in a holding means and the check of the data length while a direct memory access is carried out to a main memory from a circuit correspondence control part. CONSTITUTION:A timer 143 receives the data of the prescribed length (equal to the data length generating) a bus using request at a circuit correspondence control part 13) via a common circuit data reception control part 14. If a bus using grant signal is not inputted within a fixed time after the timer 143 is started, the part 13 decides the occurrence of a fault where the data of the prescribed length is not received yet. Thus the hardware fault of the part 13 can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a transfer data inspection method in a communication processing device including a plurality of line compatible control units having a direct memory access function, two main memory units, and a processing unit.

The purpose of this invention is to provide a transfer data inspection method that can detect hardware failures in a line-compatible control unit during transfer using direct memory access.

Data from all lines is received in parallel with each line corresponding control unit and held in the holding means, and when direct memory access is executed from the single line corresponding control unit to the main memory unit, the data on the transfer bus and the holding means are received. The configuration includes a common line data reception control unit that collates the data and checks the data length.

[Industrial Field of Application] The present invention relates to a transfer data inspection method in a communication processing device that includes a plurality of line compatible control units having a direct memory access function, a main memory unit, and a processing unit.

2. Description of the Related Art In information processing systems, communication processing devices that transmit and receive data by connecting to remote processing devices and terminals via multiple lines are widely used.

The line-compatible control unit connected to each line of such a communication processing device uses a direct memory access (DMA) function to transfer received data to the main memory, but if one line-compatible control unit malfunctions, an error occurs. There is a possibility that data may be written to main memory, and improvements are desired.

[Conventional technology] FIG. 4 is a configuration diagram of a conventional example.

In FIG. 4, 30 represents a CPU, 31 a main memory section, 32 a bus contention control section, 33 a plurality of line correspondence control sections, and 34 a line.

To explain the operation of the conventional example, when each line correspondence control unit 33 receives data from a partner device via nine lines 34, each line correspondence control unit 33 serially receives data of a fixed length (
When receiving data of, for example, 1 byte, the line correspondence control section 33 issues a use request to the bus contention control section 32. When the bus contention control unit 32 gives a notification of usage permission to the line correspondence control unit 33 that has generated the request, the 5 line correspondence control unit 33 uses an internal direct memory access (
DMA) function transfers the received data to the main memory section via the bus.

During this transfer, there is a possibility that incorrect data may be written to the main memory section due to a failure of the single-line compatible control section 33.
As a preventive measure, a conventional method has been adopted in which a parity bit is added to the data from the three-line compatible control section 33, and a parity check is performed in the main memory section 31, which is the transfer destination.

[Problem to be Solved by the Invention] According to the above-mentioned conventional technology, an l-bit error that occurs during transfer can be detected by a parity check, but in the case of a hardware failure, two-bit errors occur simultaneously. There is also a probability, and parity checks cannot detect the occurrence of errors. Also, if data longer or shorter than the received data is transferred to the main memory section due to a hardware failure in the single-line compatible control section.

There was a problem in that no matter what kind of check code was added, it could not be detected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a transfer data inspection method capable of detecting a hardware failure in a line compatible control unit during transfer using direct memory access.

“Means to solve problems” FIG. 1 is a basic configuration diagram of the present invention.

10 is a main memory section, 11 is a bus control section, 12 is a bus, 13 is a line correspondence control section provided corresponding to each of a plurality of lines, 14 is a common line data reception control section, 14
1 is a collation means, 142 is a storage means, 143 is a timer, 1
5 represents the CPU.

In the present invention, data for multiple lines is received by each line corresponding control unit, data for all lines is simultaneously received by a common line data reception control unit, and data is transferred from the single line corresponding control unit to the main memory unit on the bus. The data is compared with the data of the common line data reception control unit, and a timer is used to perform the check.

[Function] Each line corresponding control unit 13 receives data from each line, and the common line data reception control unit 14 receives the received data of all lines and stores the data for each line in its respective storage means by high-speed operation. 142. When the received data of the line correspondence control section 13 reaches a predetermined length, a bus use request is issued to the bus control section 11. On the other hand, the common line data reception control section 14 starts the timer 143 when a predetermined length of data is stored in the storage means 142.

When a usable signal is generated from the bus control unit 11 in response to a request, that signal is input to the common line data reception control unit 14 at the same time as the line correspondence control unit 13 that generated the request, and this signal causes the common line data to be received. In the control unit 14, the verification means 141 is activated.

At the same time, timer 143 stops.

DMAl of the line corresponding control unit 13 by the bus usable signal.
1 function, the received data is transferred on the bus 12 to the main memory section 1.
0, the data is also input to the common line data reception control section 14 via the bus, and the verification means 1
At 41, the data is compared with the data in the storage means 142. If the two match, there is no problem, but if they do not match (including the case where the transferred data is longer), an output operation such as an error display is performed.

The above-mentioned timer 143 is the common line data reception control unit 14
After receiving data of a predetermined length (same as the data length that generates a bus use request in the line compatible control unit),
If a bus availability signal is not input within a certain time after starting the timer, the single-line correspondence control unit 13 determines that a failure has occurred in that data of a predetermined length has not yet been received (the data length is short).

By performing such a test, it is possible to detect a hardware failure in the line corresponding control section.

[Embodiment] FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 shows the operation timing of the embodiment.

FIG. 2 shows the bottom of the tank related to the common line data reception control section, and in FIG. is a byte register (storage means 142 in Figure 1)
, 23 is a timer, 24 is a multiplex reception circuit, 25 is a bus usable signal line, 26 is a bus power line, and 27 is a reception signal line for each line. Note that 21 of 9 common line data reception control section 20
A plurality of tank bottoms 23 to 23 are provided corresponding to each line corresponding control section.

In FIG. 3, ■ and ■ are serial data 1. input from the line operator and line n. n, ■ and ■ are the contents of the byte register (22 in FIG. 2) in which the data of line 1 and line n detected by the multiplex reception circuit 24 of the common line data reception control unit 20 are stored, and ■ is the verification operation. Verification 1 represents the timing of the data verification operation of line 1, and verification n represents the timing of the data verification operation of line n.

To explain the operation of FIG. 2, received data from each line is received by a byte register (not shown) of each line corresponding control unit and input to the multiplex reception circuit 24 of the common line data reception control unit 20. The common line data reception control unit 20 samples data from a large number of lines at n times the data rate of the lines (the number of lines is 0), extracts each bit data, and extracts each bit data. The data is stored in each byte register 22 (only one line is shown in the figure). When one byte of data is stored in the byte register 22, the timer 23 is activated by an output that detects that all data has been stored in the byte register 22.

On the other hand, when 1 byte of data is received in the 2nd line control unit (not shown) (13 in Figure 1), the bus control unit (13 in Figure 1) receives 1 byte of data.
When a bus use request is generated for 11) in the figure and a bus available signal is generated from the bus control unit in response, the signal is input from the bus available signal line provided corresponding to each line corresponding control unit. .

When this signal is supplied to the verification circuit 21, it starts the verification operation and resets the timer 23 at the same time.

When the verification operation starts, the data is transferred onto the bus, which is input to the bus! It is fetched from #126 and compared with the contents of the byte register 22. If a mismatch occurs in this comparison, 1 interrupt is generated and 2 is input to a CPU (not shown).

By repeating this operation, a large number of bytes are sequentially transferred to the main memory section, but if the common line data reception control section 2
If the data is received at 0, but the data is not received by the 1-line compatible control unit (due to a hardware failure, etc.), the timer 23, which is started after being stored in the byte register 22, receives the 3-bus available signal. (because it does not issue a bus use request), it generates a time-over output. This output is also supplied to the CPU as an interrupt signal. In this way, it is possible to detect that the received data length in the line correspondence control section is short.

Also, if the data length received by the single line compatible control unit is longer (due to software or hardware failure),
Since the data not received by the common line data reception control unit 20 is compared (activated when the bus availability signal is input), a mismatch occurs and an interrupt occurs.

[Effects of the Invention] According to the present invention, equipment failures (hardware failures) can be detected more reliably than conventional inspection methods that add various check codes, and data length inspection can be performed. This can improve system reliability.

12: Bus 13: Line compatible control section 14: Common line data reception control section 141: Verification means 142: Storage means 143: Timer 15: CPU

Claims (1)

[Claims] In a communication processing device that includes a plurality of line-compatible control units having a direct memory access function, a main memory unit, and a processing unit, data from all lines is received in parallel with each line-compatible control unit. and a common line data reception control unit that collates the data on the transfer bus with the data in the holding unit and checks the data length when executing direct memory access from the line correspondence control unit to the main memory unit. A transfer data inspection method comprising: