JPH03250976A - Synchronizing signal processing circuit for picture printer - Google Patents

Abstract

PURPOSE:To prevent a succeeding normal input signal from being eliminated by adding a pseudo synchronizing signal to a position with a missing synchronizing signal through self-excitation oscillation at no input state when the synchronizing signal is missing and using a noise elimination circuit to limit the input signal till lapse of a prescribed time. CONSTITUTION:When a horizontal synchronizing signal S11 including noise signals N1, N3 and a missing part N2 of the synchronizing signal is inputted to a retriggerable multivibrator 11, only the edge of the horizontal synchronizing signal S11 is valid to the multivibrator 11 and a pulse S12 with a sufficiently short setting time is outputted. However, when the synchronizing signal is missing (N2), an output of a retriggerable multivibrator 10 goes to logical 1 after lapse of a prescribed time and a pseudo synchronizing signal is outputted to a position of missing synchronizing signal. In this case, since an additional circuit 4 triggers a retriggerable multivibrator 16, an AND gate element 12 is closed by a prescribed time t10. Thus the noise N3 after the pseudo synchronizing signal is added is eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronization signal processing circuit for a video printer that receives a video signal as input and obtains a hard copy of the video. The present invention relates to a synchronization signal processing circuit capable of obtaining accurate synchronization signals.

C. Prior Art] FIG. 3 is a circuit diagram showing the configuration of a synchronization signal processing circuit of a conventional image printer described in Japanese Patent Application Laid-Open No. 123372/1982. It has an input terminal 2 for input, and a noise removal circuit 3 for removing noise from the synchronization signal is connected to the input terminal 2.

The noise removal circuit 3 is connected to an additional circuit 4 which performs self-oscillation when there is no input due to lack of a synchronization signal and outputs a pseudo synchronization signal at the position where the synchronization signal is missing. A single shot multivibrator 5 is connected to adjust the output pulse width.

The noise removal circuit 3 also includes an AND gate element 6 to which a horizontal synchronizing signal is input to one input, and an AND gate element 6 to which a horizontal synchronizing signal is input.
62 for horizontal sync period 63.5 LI3 connected to
Between g5 and 63g5 (T1) is constituted by a single shot multivibrator 7 which outputs logic "0", and the output of the single shot multivibrator 7 is connected to the other input of the AND gate element 6.

Further, the additional circuit 4 includes a NOR gate element 8 to which the output of the AND gate element 6 is inputted to one input, an EXOR gate element 9 to which the output of the NOR gate element 8 is inputted to one input, and an EXOR gate element 9. The other input of the NOR gate element 8 is a retriggerable multivibrator 10 that outputs a logic rOJ for a period T2 (65 μs from 64 LIS) that is slightly longer than the horizontal synchronization period. The output of the bull multivibrator 10 is input, and the other input of the EXOR gate element 9 is input with a system reset signal.

Next, the operation of this conventional circuit will be explained with reference to the timing chart of FIG.

When the horizontal synchronizing signal S1 containing the noise N and the missing synchronizing signal N2 is input, the single shot multivibrator 7 has a synchronization period of 62 to 63 μs for a synchronization period of 63.5 μs.
During us (T1) outputs logic “0”; during this period (T,
), AND gate element 6 does not accept any signals,
Noise is removed. However, FIG. 4 shows a conventional example in which N is not removed.

Then, when the synchronization signal S3 from which noise has been removed is input to the NOR gate element 8, if the input becomes "1", the output S8 of the NOR gate element 8 will always become logic "0", and the EXOR
The output S5 of the gate element 9 becomes logic "1".

As a result, the retriggerable multivibrator 10 operates, and at this time, unlike when it oscillates using its own output as input, the retriggerable multivibrator 10 is always given a trigger due to the horizontal synchronization signal, and becomes a logic rOJ. It remains as it is.

However, when the synchronization signal is missing, the output of the retriggerable multivibrator 10 becomes logic "1" after a predetermined period of time, and a pseudo synchronization signal is output at the position where the synchronization signal is missing.

Note that the pulse width is adjusted by the single shot multivibrator 5.

[Problems to be Solved by the Invention] Since the conventional synchronization signal processing circuit 1 is configured as described above, if there is a deficiency N2 in the horizontal synchronization signal S1 (the fourth
), the addition circuit 4 adds a pseudo synchronization signal to the position where the synchronization signal is missing, but if there is noise N after the position where the pseudo synchronization signal should be added, the single shot multivibrator of the noise removal circuit 3 Since the single shot multivibrator 7 does not operate, the noise N is not removed, and furthermore, the single shot multivibrator 7 operates due to the noise N1, and the next normal input signal is removed. .

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a synchronization signal processing circuit for an image printer that can remove noise after a horizontal synchronization signal is missing or missing.

[Means for Solving the Problems] A synchronous signal processing circuit for an image printer according to the present invention has the following features:
A noise removal circuit that removes noise on the input synchronization signal, and an additional circuit that performs self-oscillation when the synchronization signal is missing and when there is no input, and outputs a pseudo synchronization signal at the position where the synchronization signal is missing.
The present invention is characterized by comprising an addition-time noise removal circuit that limits the input signal until a predetermined time has elapsed after the addition of the pseudo synchronization signal by the additional circuit.

It is also preferable to include an input determination circuit that detects the presence or absence of an input signal and prohibits the operation of the addition noise removal circuit if there is no input signal or synchronization signal for two or more cycles.

[Operation] The synchronous signal processing circuit of the image printer according to the present invention has the following features:
Noise on the input synchronization signal is removed by a noise removal circuit, and when there is no input when the synchronization signal is missing, self-oscillation is performed and a pseudo synchronization signal is output from the additional circuit at the position where the synchronization signal is missing. The input signal is limited by the addition noise removal circuit until a predetermined time has elapsed after the synchronization signal is added.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the synchronization signal processing circuit 100 has an input terminal 2 into which a horizontal synchronization signal is input. A retriggerable multivibrator 11 to be taken out is connected.

And, the retriggerable multivibrator 11 has AN
A D gate element 12 is connected to the AND gate element 12, and a noise removal circuit 3 for removing noise from the synchronization signal is connected to the AND gate element 12.

An additional circuit 4 is connected to the noise removal circuit 3, which performs self-oscillation when there is no input when the synchronization signal is missing, and outputs a pseudo synchronization signal at the position where the synchronization signal is missing. A single shot multivibrator 5 for adjusting the pulse width is also connected.

The noise removal circuit 3 also includes an AND gate element 6 to which a horizontal synchronizing signal is input to one input, and an AND gate element 6 to which a horizontal synchronizing signal is input.
62~ for a horizontal synchronization period of 63.5 μs connected to
During 63 μs (T1), the single shot multivibrator 7 outputs a logic “0”, and the output of the single shot multivibrator 7 is A.
It is connected to the other input of the ND gate element 6.

Furthermore, the additional circuit 4 is composed of a NOR gate element 8 which receives the output of the AND gate element 6 as one input, and a triggerable multivibrator 10 which inputs the output of the NOR gate element 8. Gate element 8
The other input has a period T2 slightly longer than the horizontal synchronization period.
(64 to 65 μs), the logic “0” is outputted, or the output of the triggerable multivibrator 10 is input.

A retriggerable multivibrator 13 is connected to the output side of the AND gate element 6, and one input of an ANDNO gate element 8 is connected to the output side of the retriggerable multivibrator 13. The output of the retriggerable multivibrator 10 is input to the other input of the retriggerable multivibrator 14, and the retriggerable multivibrator 13 and the AND gate element 14 constitute an input determination circuit 15.

Further, a retriggerable multivibrator 16 is connected to the output side of the AND gate element 14, and the output of the retriggerable multivibrator 16 is connected to the output side of the AND gate element 1.
It is designed to be input to one input of 2, and
Gate element 12 and retriggerable multi-by-break 16
An addition noise removal circuit 17 is configured by the above.

Next, the operation of this embodiment will be explained using the timing whipyard shown in FIG.

When a horizontal synchronizing signal Sl+ containing noise N, , N3 and missing synchronizing signal N2 is input, the retriggerable multi-byte break 11 generates a sufficiently short pulse (S+2 ) is output.

This makes it possible to eliminate the influence of the width of the horizontal synchronizing signal Sl+.

Then, the AND gate element 12 ANDs the pulse S12 and the output s2° of the retriggerable multivibrator 16, and outputs an output S+3.

On the other hand, the retriggerable multivibrator 7 has a synchronization period of 6
The logic rOJ is output between 62 and 6:3 ps (t,) for 3.5 μS, and during this period (+5), the AND gate element 6 accepts all signals and the noise N1 is removed.

Then, when the synchronization signal 514 from which the noise N1 has been removed is input to the NOR gate element 8, if the input becomes "1", the NO
The output S17 of the R gate element 8 always becomes logic "0".

As a result, the retriggerable multi-high break 10 operates, and at this time, unlike the case where the retriggerable multi-high break 10 oscillates using its own output as input, the retriggerable multi-high break 10 is always given a trigger due to the horizontal synchronization signal, and the logic "0" ” remains.

However, when the synchronization signal N2 is missing, the output of the retriggerable multivibrator 10 becomes logic "1" after a predetermined period of time, and a pseudo synchronization signal is output at the position where the synchronization signal is missing.

At this time, since the retriggerable multivibrator 16 is triggered by the additional circuit 4, the predetermined time t
,. The AND gate element 12 is closed, thereby eliminating the noise N3 after adding the pseudo synchronization signal.

Note that the time tl for closing the AND gate element 12.

is set in the range of t+o<2H-t6, where t6 is the setting time of the retriggerable multivibrator 10.

In addition, the retriggerable multivibrator 13 operates for a predetermined period of time (IH<
t<2H) becomes "0" and operates the additional time signal sound removal circuit 17. If the input signal is not 2H or more, it becomes "1" and does not operate the additional time signal sound removal circuit 17. As a result, the input determination circuit 15 An additional time signal sound that operates the additional time signal removal circuit 17 by the free running of the additional circuit 4 when the input signal disappears, and when the input r= signal comes again, this input signal is determined to be noise and is removed. Runaway of the removal circuit 17 is prohibited.

Note that it is set as IH<<t8<2H.

In the above-described embodiment, the horizontal synchronization signal is used as an example of the synchronization signal, but the present invention is not limited to this, and a vertical synchronization signal may also be used. In this case, set the time according to the period of the vertical synchronization signal.

[Effects of the Invention] As explained above, according to the present invention, when there is no input when the synchronization signal is missing, self-oscillation is performed and a pseudo synchronization signal is added to the position where the synchronization signal is missing, and the pseudo synchronization signal is added. Since the additional time signal removal circuit is configured to limit the input signal until a predetermined time has elapsed after the addition of the pseudo synchronization signal, the noise after the position where the pseudo synchronization signal should be added is removed, and the next normal input signal is removed. It is possible to prevent the signal from being removed.

In addition, the system is configured to detect the presence or absence of an input signal and prohibit the operation of the additional time signal removal circuit if there is no input signal or synchronization signal for two cycles or more, so when the input signal comes again, the input signal It is possible to prevent the additional time signal sound removal circuit from running out of control.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a synchronous signal processing circuit of an image printer according to an embodiment of the present invention, and FIG. 2 shows signal timing of a synchronous signal processing circuit of an image printer according to an embodiment of the invention. FIG. 3 is a block diagram showing the configuration of a synchronous signal processing circuit of a conventional image printer. FIG. 4 is a timing chart showing problems of the synchronous signal processing circuit of a conventional image printer. 1... Image printer synchronous signal processing circuit 3...
・ Noise removal circuit 4 ... Addition circuit 15 ... Input judgment circuit 17 ... U-section of noise removal circuit at the time of addition)

Claims (2)

[Claims] (1) Equipped with a noise removal circuit that removes noise on the input synchronization signal, and an additional circuit that performs self-oscillation when there is no input when the synchronization signal is missing, and outputs a pseudo synchronization signal at the position where the synchronization signal is missing. , a synchronization signal processing circuit of an image printer which inputs a video signal and obtains a hard copy thereof, further comprising an addition noise removal circuit which limits the input signal until a predetermined time elapses after the pseudo synchronization signal is added by the additional circuit. A synchronous signal processing circuit for an image printer, characterized in that: (2) In the synchronization signal processing circuit of the image printer according to claim 1, the input determination detects the presence or absence of an input signal and prohibits the operation of the addition noise removal circuit when the input signal is absent for two or more cycles of the synchronization signal. A synchronous signal processing circuit for an image printer, characterized in that the circuit is provided with a synchronous signal processing circuit.