JPH03250497A - Shift register - Google Patents

Abstract

PURPOSE:To reduce current due to a clock signal to prevent the generation of noise by successively turning on and of switching elements by control clocks outputted from a ring counter. CONSTITUTION:In accordance with the counting off clock signals CLK synchronized with data DIN, output signals C1 to C6 are successively outputted from the ring counter CTR. A transistor(TR) Q1 is turned on by the output C1 and the 1st bit D1 of the data is stored in a latch circuit L1. Similarly, respective bits are stored in latch circuits L2 to L6. When the output C1 is obtained again, the data stored in the circuit L2 are outputted through a TR Q2 and data D7 are stored in the circuit L1. Thus, input data are delayed by 5 bits of the signal CLK and outputted by repeating the operation and the 5-bit shift register can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a shift register integrated into a digital integrated circuit.

(b) Conventional technology In recent years, development of digital signal processing devices using digital technology has progressed. Such digital signal processing devices are put into practical use as semiconductor integrated circuits, and include many built-in circuits for realizing functions specific to a target signal. For example, for image processing, a line memory for delaying one line of video signals and a delay line for a digital filter are often built-in.

Conventionally, shift registers are used as delay lines for line memories and digital filters. Normally, a shift register built into an integrated circuit is as shown in FIG.
A large number of F F (]) (10 in the case of 10 bits) are continuously connected, and a clock signal CLK which is the same as data (■) 0 and M is commonly applied to the clock input C.

(C) Problems to be Solved by the Invention However, in conventional shift registers, the D-FFs of all bits operate simultaneously based on the clock signal CI-K, so as the number of bits increases, the current flowing through each D-FF increases. This increases current consumption, and furthermore, noise increases due to a drop in power supply voltage, which poses a problem. Furthermore, as the number of bits increases, the number of elements constituting the D-FF (7) also increases, which has the drawback of increasing the area occupied by the integrated circuit.

(d) Means for Solving the Problems The present invention was created in view of the above-mentioned drawbacks, and includes a plurality of first switch elements whose ends are commonly connected to a data input terminal, and a plurality of first switch elements whose ends are commonly connected to a data input terminal. a plurality of data holding circuits each connected to the other end of the switching element; a plurality of second switch elements each having one end connected to the output of the plurality of data holding circuits and the other end commonly connected; By including a non-long counter that sequentially controls each of the first sinch element and the second sinch element, current consumption is small;
This provides a shift register with a small number of constituent elements.

(E) According to the double means for 11-Y, the first switch element is turned on and off in sequence by the control clock sequentially output from the ring counter, so that the data applied to the data input terminal is , is applied to only one data holding circuit through the first switch element that is turned on, and current flows only in the one data holding circuit to which the data is applied. Furthermore, since the second switch element is also turned on and off sequentially by the control clock of the ring counter, data is output from one data holding circuit, and current flows only through that data holding circuit. Therefore, among the plurality of data holding circuits forming the shift register, the number of data holding circuits that operate simultaneously is reduced, and current consumption is reduced. In addition, since the shift register consists of the first switch element, the data holding circuit, and the second switch element, the total number of constituent elements is reduced.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
Q is an N-channel MO which is the first switching element.
S transistors, L and ~L6 are latch circuits that are data holding circuits, Q and ~Qlt are N-channel MOS transistors that are second switching elements, L is a latch circuit for output, and CTR is 6 Bint's ring counter.

The drains (or sources) of the MOS transistors/transistors Q1 to Q are each commonly connected to the data input terminal D++i, and each source (or train) is connected to each latch circuit, ~
It is individually connected to the input of Lg.

Moreover, the outputs C1 to C of the ring counter CTR are applied to the gates of the MOS transistors Q1 to Q, respectively. The latch circuits L1 to L2, L are each C
-MOS inverter (1) and C-MOS inverter (
1) is connected between the input and power supply VDD, and the gate is connected to C-M.
It consists of a P-channel MO5) transistor (2) connected to the output of the OS inverter (1). The outputs of the latch circuits L1-L6 are individually connected to the drains (or sources) of the MO5+- transistors Q, -QIt, respectively, and are connected to the drains (or sources) of the MOS transistors Q7-Q1. The sources (or trains) of are commonly connected to the inputs of the launch circuit. Furthermore, the outputs C1-C6 of the ring counter CTR are applied to the dates of the MOS transistors Q, ~Q+2, respectively by 11A+, similarly to the MOS transistors Q1-Q6. The timing is controlled so that the transistors Q and Q12 operate one bit earlier than the timing.

Note that this circuit can be configured with 33 MOS transistors, excluding the number of constituent elements of the ring counter CTR.

Next, the operation of the shift register shown in FIG. 1 will be explained with reference to FIG. 2. As the ring counter CT R counts the clock signal CLK synchronized with the data DIN, the output signals C1 to C6 are sequentially outputted. Output C1
When is output, the MOS transistor Q1 is turned on, and the first bit of the data applied to the data input terminal DIN is held in the latch circuit L1. Similarly, output C
, -C are output, data D, to D are sequentially input to the latch circuit and held. Next, when the output C6 is output, the MOS transistor Q7 is turned on, and the data D held in the latch circuit L1 is output to the output latch circuit L7 and held there. On the other hand, output C
, turns on MO3I-transistor Q, so that data D is applied to and held in the latch circuit. Then, when the output C7 is output again, the data D held in the latch circuit is transferred to the MOS transistor Q.
The data D is held in the latch circuit L1.

By repeating the above operation, the data input terminal DI
) The data applied to I is output after being delayed by 5 bits of the clock signal CLK, forming a so-called 5-bit shift register.

Additionally, when shifting one bit, only two latch circuits are in operation: the latch circuit that inputs the data, and the latch circuit that outputs the held data, so current only flows through that latch circuit. becomes.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, in which two stages of the shift register shown in FIG.
The S transistors Q, ~Q are commonly connected to a ring counter CT.
Controlled by R.

FIG. 4 is a timing diagram showing the operation of the circuit shown in FIG. 3, and shows the output of the first stage shift register SR1.

As mentioned above, UTI is an output obtained by delaying the input data by 5 bits, and is the output of the second stage shift register SR2. U□ becomes an output that is further delayed by 5 bits. Therefore, the circuit shown in FIG. 3 becomes a lO bit shift register.

In this way, by continuously connecting 0 stages of the shift registers shown in FIG. 1, a 5×n bit shift register can be constructed. In this case, when a shift register with a large number of bits is configured, current consumption is significantly reduced compared to a conventional shift register.

In addition, since a D-FF is generally formed of eight MOS) transistors, a conventional 20-bit shift register requires 160 MOS) transistors, but the 20-bit shift register according to the present invention requires 160 MOS) transistors. In this case, it can be configured with 132 MOS transistors. In particular, since the ring counter CTR can be used in common for each stage of shift registers, the effect of reducing the number of constituent elements becomes more significant as the number of bits increases.

(g) Effects of the Invention As described above, according to the present invention, it is possible to reduce the current that flows at the rise and fall of a clock signal synchronized with data, thereby eliminating the possibility of a drop in the power supply voltage and reducing the generation of noise. This can be prevented and the overall current consumption can be reduced. In particular, the effect becomes greater in the case of a shift register with a large number of bits.

Furthermore, since the number of elements constituting the shift register can be significantly reduced, there is an advantage that the ratio of the area occupied by the shift register on the semiconductor integrated circuit can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of the invention. 4 is a timing diagram showing the operation of the embodiment shown in FIG. 3, and FIG. 5 is a circuit diagram showing the conventional example. Q1~Q,,Q,~Q1. ...MOS transistor,
L, ~L,,L,...Latch circuit, CTR...Ring counter, DIN...Data input terminal

Claims (3)

[Claims] (1) a plurality of first switch elements each having one end commonly connected to a data input terminal; a plurality of data holding circuits each connected to the other end of the plurality of first switch elements; One end of each is connected to the output,
A shift register comprising: a plurality of second switch elements whose other ends are commonly connected; and a ring counter that sequentially controls each of the plurality of first switch elements and second switch elements. (2) A shift register characterized in that the control timing of the plurality of first switch elements is delayed from the control timing of the plurality of second switch elements by one bit output of the ring counter. (3) A plurality of shift registers each having the plurality of first switches, the plurality of data holding circuits, and the plurality of second switches are continuously connected, and the first switch and the second switch of each stage are controlled by the common ring counter. The shift register according to claim 1, characterized in that: