JPH03249811A - Light-receiving amplifier - Google Patents

Light-receiving amplifier

Info

Publication number
JPH03249811A
JPH03249811A JP2047982A JP4798290A JPH03249811A JP H03249811 A JPH03249811 A JP H03249811A JP 2047982 A JP2047982 A JP 2047982A JP 4798290 A JP4798290 A JP 4798290A JP H03249811 A JPH03249811 A JP H03249811A
Authority
JP
Japan
Prior art keywords
offset
circuit
constant
receiving amplifier
light receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2047982A
Other languages
Japanese (ja)
Inventor
Yutaka Hayashi
豊 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2047982A priority Critical patent/JPH03249811A/en
Publication of JPH03249811A publication Critical patent/JPH03249811A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To set a DC offset constant in spite of an AGC control error by independently providing a circuit controlling the DC offset of an output and an AGO control circuit setting amplitude constant. CONSTITUTION:The DC offset control circuit and the AGC offset circuit are independently provided. A DC feedback circuit 8 feeds back the peak holding values of a positive phase SD and the negative phase SD so that they are kept constant. Thus, the DC offset becomes constant in spite of output amplitude being the AGC control error. Thus, a light-receiving amplifier where the DC offset is not shifted even if there is the AGC control error can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明qDCオフセット制御回路と五Gc制御回路を
備えた受光増幅器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a light receiving amplifier equipped with a qDC offset control circuit and a 5Gc control circuit.

〔従来の技術〕[Conventional technology]

第8図は従来の一般的なりCオフセット制御回路とAG
O制御回路を備えた受光増幅器の回路図である。
Figure 8 shows a conventional general C offset control circuit and an AG
FIG. 2 is a circuit diagram of a light receiving amplifier equipped with an O control circuit.

図において、Illは受光素子、1!1は受光素子11
1の電流を電圧に変換するプリアンプ、13Iは自動利
得制御回路(以下AGOアンプと呼ぶ)、(8D)H正
相出力、CBD)は逆相出力、(41は正相ピークホー
ルド回路、fat Fi逆相ピークホールド[ol路、
(61は正相逆相中間値検出回路、171は正相ピーク
ホールド141と正相、逆相中間値検回路(6)の差を
一定とするようフィードバックをかけたAGOフィード
バック回路、(8)は逆相ピークホールド+Ilと、正
相、逆相中間値検出回路161の差を一定とするようフ
ィードバックをかけたDCフィードバック回路である。
In the figure, Ill is a light receiving element, and 1!1 is a light receiving element 11.
1 is a preamplifier that converts current into voltage, 13I is an automatic gain control circuit (hereinafter referred to as AGO amplifier), (8D) H positive phase output, CBD) is a negative phase output, (41 is a positive phase peak hold circuit, fat Fi Reverse phase peak hold [OL path,
(61 is a positive phase and negative phase intermediate value detection circuit, 171 is an AGO feedback circuit that applies feedback to keep the difference between the positive phase peak hold 141 and the positive phase and negative phase intermediate value detection circuit (6) constant, (8) is a DC feedback circuit that applies feedback to keep the difference between the negative phase peak hold +Il and the positive phase and negative phase intermediate value detection circuit 161 constant.

次に動作につめて説明する。Next, the operation will be explained.

受光素子IIIの電Rtプリアンプ+71により電圧に
変換し、AGOアンプ;3)で増幅して出力し、その正
相出力(θD)逆相出力(8D)’にピークホールド回
路14+、lIlによりピークホールド値を検出し、又
正相逆相中間値検出検出回路16)で正相と逆相の中間
値を検出する。その正相ピークホールド値と中間値検出
値との差が一定となるようムGoフィードバック回路(
71によりAGOアンプimlへフィードバックされる
。又、逆相ピークホールド値と中間値検出値との差が一
定となるようDCフィードパンク回路(8)によりAG
Oアンプ13:ヘフィードバックされる。この2つのフ
ィードバックにより出力振幅DCオフセツトが一定に制
御される。
The electric current of the photodetector III is converted into a voltage by the Rt preamplifier +71, amplified by the AGO amplifier; The positive phase and negative phase intermediate value detection circuit 16) detects the intermediate value between the positive phase and the negative phase. The Go feedback circuit (
71, it is fed back to the AGO amplifier iml. In addition, the AG is controlled by the DC feed puncture circuit (8) so that the difference between the negative phase peak hold value and the intermediate value detection value is constant.
It is fed back to the O amplifier 13. These two feedbacks control the output amplitude DC offset to be constant.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のDCCオフセラ、AGo11111回路ヲ備えた
受光増幅器は以上のように構成されていたので、AGC
制御誤差である出力振幅の誤差があるとwi4図に示す
出力波形図のように、DCオフセット制御回路が逆相ピ
ークホールド値と中間検出値の差を一定としようと働く
ため、DCオフセットがずれてしまうという問題点があ
った。
Since the conventional DCC off-celler and the light receiving amplifier equipped with the AGo11111 circuit were configured as described above, the AGC
If there is an error in the output amplitude, which is a control error, the DC offset control circuit will work to keep the difference between the negative phase peak hold value and the intermediate detection value constant, as shown in the output waveform diagram shown in Figure wi4, and the DC offset will shift. There was a problem with this.

この発明は上記の様な問題点を解決する為になされたも
ので、ムGo制御誤差があってもDDオフセットがずれ
ない受光増幅器金得ることを目的とする。
This invention was made to solve the above-mentioned problems, and aims to provide a light receiving amplifier in which the DD offset does not shift even if there is a Go control error.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る受光増幅器は、DCオフセット制御回路
とムGoオフセット回路を独立させたものである。
The light receiving amplifier according to the present invention has an independent DC offset control circuit and a Go offset circuit.

〔作用〕[Effect]

この発明における受光増幅WAは、DCオフセット制御
回路とAGO制御回路を独立させることにより、DCオ
フセットはAGO制御誤差に関係なく一定となる。
In the light receiving amplification WA in this invention, the DC offset control circuit and the AGO control circuit are made independent, so that the DC offset is constant regardless of the AGO control error.

〔実施列〕[Implementation row]

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図にこの発明の一実施例である受光増幅器の回路図
で、図におhて、(8)はDCフィードバック回路で、
正相、逆相のピークホールド値を一定とするようにフィ
ードバックをかけている。
FIG. 1 is a circuit diagram of a light receiving amplifier which is an embodiment of the present invention. In the figure, (h) is a DC feedback circuit,
Feedback is applied to keep the peak hold values of the positive phase and negative phase constant.

尚図中前記従来のものと同一符号に同一または相当部分
を示しその説明は省略する。
In the drawings, the same reference numerals as in the prior art design indicate the same or corresponding parts, and the explanation thereof will be omitted.

次に動作について説明する。Next, the operation will be explained.

DCフィードバック回路(8)ヲ正相、逆相のピークホ
ールド値の差が一定となるようフィードバラフケかけて
いる為、第2図に示すようにA()0111J#誤差で
ある出力振幅に関係なくDCオフセットは一定となる〇 〔発明の効果〕 以上のようにこの発明によれば、DCオフセット制御回
路とムGo制御回路を独立させたので、AGO制御誤差
に関係な(Doオフセットは一定となシ、又、フィード
バック調整が簡単になるという効果がある。
Since the DC feedback circuit (8) is set to a feed balance so that the difference between the peak hold values of the positive phase and negative phase is constant, the A()0111J# error is related to the output amplitude as shown in Figure 2. According to the invention, as described above, since the DC offset control circuit and the Go control circuit are made independent, the DC offset remains constant regardless of the AGO control error. Moreover, there is an effect that feedback adjustment becomes easier.

【図面の簡単な説明】[Brief explanation of drawings]

$1!1図はこの発明の一実施例による受光増幅器の回
路図、[1図Fi111!1図の受光増幅器の出力波形
図、第3図は従来の受光増幅器の回路図、第1図は第3
図の出力波形図である。 図にお−て、1llFi受光素子、(!1はプリアンプ
、13)はAGO7/プ、 +41. l!ilはピー
クホールド回路、1g1中間値検出回路、It) Fi
ム()0フイ一ドバツク回路181FiDcフィードバ
ック(ロ)路を示す。 なお、図中、同一符号は同一 または相当部分倉示す。
Figure 1 is a circuit diagram of a light receiving amplifier according to an embodiment of the present invention, [Figure 1 is an output waveform diagram of the light receiving amplifier shown in Figure 1, Figure 3 is a circuit diagram of a conventional light receiving amplifier, and Figure 1 is a circuit diagram of a light receiving amplifier according to an embodiment of the present invention. Third
It is an output waveform diagram of the figure. In the figure, 1llFi light receiving element, (!1 is preamplifier, 13) is AGO7/pu, +41. l! il is a peak hold circuit, 1g1 intermediate value detection circuit, It) Fi
The feedback circuit 181FiDc shows the feedback path. In addition, in the figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 出力のDCオフセットを制御する回路と、振幅を一定に
するAGO制御回路を独立して備えたことを特徴とする
受光増幅器。
A light-receiving amplifier characterized by independently comprising a circuit for controlling the DC offset of the output and an AGO control circuit for keeping the amplitude constant.
JP2047982A 1990-02-27 1990-02-27 Light-receiving amplifier Pending JPH03249811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2047982A JPH03249811A (en) 1990-02-27 1990-02-27 Light-receiving amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2047982A JPH03249811A (en) 1990-02-27 1990-02-27 Light-receiving amplifier

Publications (1)

Publication Number Publication Date
JPH03249811A true JPH03249811A (en) 1991-11-07

Family

ID=12790522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2047982A Pending JPH03249811A (en) 1990-02-27 1990-02-27 Light-receiving amplifier

Country Status (1)

Country Link
JP (1) JPH03249811A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004072060A (en) * 2001-11-22 2004-03-04 Innotech Corp Transistor and semiconductor memory using the same, and method of driving the transistor
JP2006324343A (en) * 2005-05-17 2006-11-30 Nec Electronics Corp Nonvolatile semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004072060A (en) * 2001-11-22 2004-03-04 Innotech Corp Transistor and semiconductor memory using the same, and method of driving the transistor
JP2006324343A (en) * 2005-05-17 2006-11-30 Nec Electronics Corp Nonvolatile semiconductor memory

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