JPH03248569A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPH03248569A JPH03248569A JP4449490A JP4449490A JPH03248569A JP H03248569 A JPH03248569 A JP H03248569A JP 4449490 A JP4449490 A JP 4449490A JP 4449490 A JP4449490 A JP 4449490A JP H03248569 A JPH03248569 A JP H03248569A
- Authority
- JP
- Japan
- Prior art keywords
- film
- hydrogen concentration
- gate insulating
- silicon nitride
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 18
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000001257 hydrogen Substances 0.000 claims abstract description 34
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 34
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000009826 distribution Methods 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 146
- 239000000758 substrate Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 229910004205 SiNX Inorganic materials 0.000 description 18
- 239000007789 gas Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241001239379 Calophysus macropterus Species 0.000 description 1
- 229910016024 MoTa Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、スイッチング素子に用いられる薄膜トランジ
スタの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in thin film transistors used as switching elements.
（従来の技術）
近年、非晶質シリコン（ａ −Ｓ ｉ）膜を用いた薄膜
トランジスタをスイッチング素子として構成されたアク
ティブマトリックス型液晶表示装置が注目されている。(Prior Art) In recent years, active matrix liquid crystal display devices configured with thin film transistors using amorphous silicon (a-Si) films as switching elements have attracted attention.
これは、安価なガラス基板を用いることで大画面、高精
細、高画質なパネルデイスプレィを低コストで実現する
可能性があるからである。This is because by using an inexpensive glass substrate, it is possible to realize a panel display with a large screen, high definition, and high image quality at low cost.
第８図は、活性層にａ−Ｓｉ膜を用いた従来の表示駆動
装置用ＴＰＴの断面図である。先ず、ガラス板のような
透光性絶縁基板２１上に設けられたＭｏやＣｒのような
金属がバターニングされゲート電極２２が形成される。FIG. 8 is a cross-sectional view of a conventional TPT for a display driving device using an a-Si film as an active layer. First, a metal such as Mo or Cr provided on a transparent insulating substrate 21 such as a glass plate is patterned to form a gate electrode 22 .
このゲート電極２２上にはゲート絶縁膜２３である５ｉ
ｎ２膜２３ａ。On this gate electrode 22 is a gate insulating film 23 5i.
n2 film 23a.
ＳｉＮｘ膜２３ｂが順次積層されている。このゲ−ト絶
縁膜２３上のゲート電極２２上に位置するところに、活
性層としてａ−８ｉ膜２４の半導体膜が所定のパターン
に形成されている。このａＳｉＳｉ膜上４上ＳｉＮｘ膜
２５ａとＳｉＯｘ膜２５ｂとの１に層膜である保３膜２
５が形成されている。活性層にはオーミックコンタクト
層としてｎ″’ ａ−８Ｌ膜２６を介してソース電極２
７．ドレイン電極２８が形成されている。。ソース電極
２７、ドレイン電極２８と半導体膜２４との間には、オ
ーミックコンタクト層としてｎ”ａ−３ｉ膜２６が形成
されている。SiNx films 23b are sequentially stacked. A semiconductor film of an A-8I film 24 is formed as an active layer in a predetermined pattern on the gate insulating film 23 and above the gate electrode 22. As shown in FIG. A protective film 2, which is a layered film, is formed on the SiNx film 25a and the SiOx film 25b on this aSiSi film 4.
5 is formed. A source electrode 2 is connected to the active layer via an n''a-8L film 26 as an ohmic contact layer.
7. A drain electrode 28 is formed. . An n''a-3i film 26 is formed as an ohmic contact layer between the source electrode 27, the drain electrode 28, and the semiconductor film 24.
一般に、ａ−５ｉ膜の内部応力は圧縮応力。Generally, the internal stress of the a-5i film is compressive stress.
ＳｉＮｘ膜の内部応力は引張り応力そしてＳｉＯｘ膜の
内部応力は圧縮応力であるので、このような従来構造の
ＴＰＴでは、活性層の内部応力とこれに接するゲート絶
縁膜中のＳｉＮｘ膜の内部応力は逆になっている。さら
にゲート絶縁膜中で接するＳｉＮｘ膜とＳｉＯｘ膜の内
部応力もお互いに異なっている。したがって、このよう
な接合面では当然膜の剥離発生頻度が他の箇所に比べて
高くなる。その結果、ゲート絶縁層のリーク電流の増大
、スイッチング機能の消失などのようにＴＰＴ特性が不
良になり歩留まりが悪くなるという問題があった。Since the internal stress of the SiNx film is tensile stress and the internal stress of the SiOx film is compressive stress, in a TPT with such a conventional structure, the internal stress of the active layer and the internal stress of the SiNx film in the gate insulating film in contact with it are It's the other way around. Furthermore, the internal stresses of the SiNx film and the SiOx film that are in contact with each other in the gate insulating film are also different from each other. Therefore, the frequency of film peeling occurring at such a joint surface is naturally higher than at other locations. As a result, there have been problems in that the TPT characteristics are poor, such as an increase in leakage current in the gate insulating layer and loss of switching function, resulting in poor yield.
（発明が解決しようとする課８）
以上のように従来構造の薄膜トランジスタは、ゲート絶
縁膜とそれに接合する活性層の如く、内部応力が異なる
膜間での接合が存在するのでこれらの膜の剥離に起因す
るＴＰＴ特性の不良が見られた。(Issue 8 to be solved by the invention) As described above, in the thin film transistor of the conventional structure, there are bonds between films with different internal stress, such as the gate insulating film and the active layer bonded to it, so it is difficult for these films to peel off. Defects in TPT characteristics due to this were observed.
本発明はこのような膜の剥離を回避して信頼性向上を図
った薄膜トランジスタを提供することを目的としている
。An object of the present invention is to provide a thin film transistor with improved reliability by avoiding such film peeling.
［発明の構成］
（課題を解決するための手段）
上記の目的を達成するために、本発明は、基板と、この
基板上に所定パターンをもって形成されたａ−５ｉ膜と
、このａ−８ｔ膜にコンタクトするソースおよびドレイ
ン電極と、前記ａ−Ｓｉ膜の上部または下部にゲート絶
縁膜を介して配設されたゲート電極とを有する薄膜トラ
ンジスタにおいて、前記ゲート絶縁膜は少くとも前記ａ
Ｓｔ膜側に近い部分が窒化シリコン膜により形成され、
かつその窒化シリコン膜は前記ａ−５ｉ膜側では水素濃
度が低くなる膜厚方向の水素濃度分布を有することを特
徴とする。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a substrate, an a-5i film formed with a predetermined pattern on the substrate, and an a-8t film formed on the substrate with a predetermined pattern. In a thin film transistor having source and drain electrodes in contact with the a-Si film, and a gate electrode disposed above or below the a-Si film with a gate insulating film interposed therebetween, the gate insulating film includes at least the a-Si film.
A portion close to the St film side is formed of a silicon nitride film,
The silicon nitride film is characterized in that it has a hydrogen concentration distribution in the film thickness direction such that the hydrogen concentration is lower on the a-5i film side.
（作用）
不発者らか研究を重ねた結果、窒化シリコン膜の内部応
力は膜中の水素濃度に依存し、水素濃度が高くなるにし
たがい引張り応力が強くなることを確認した。(Function) As a result of repeated research conducted by those involved in the failure, it was confirmed that the internal stress of a silicon nitride film depends on the hydrogen concentration in the film, and as the hydrogen concentration increases, the tensile stress becomes stronger.
したがって本発明によれば、活性層であるａＳｉ膜と接
する窒化シリコン膜中の膜厚方向の水素濃度を変えるこ
とで、これら膜界面に働く応力を抑えることができ、剥
離が起こり難くなる。Therefore, according to the present invention, by changing the hydrogen concentration in the film thickness direction in the silicon nitride film that is in contact with the aSi film that is the active layer, it is possible to suppress the stress acting on the interface of these films, making it difficult for peeling to occur.
（実施例） 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図は、本発明の第１の実施例に係る薄膜トランジス
タの断面図である。これを製造工程に従い説明すると、
最初にガラス基板からなる透光性絶縁基板１上に厚さ約
２０００人のＴａあるいはＭ ｏ Ｔ ａ合金等の金属
膜をスパッタリング法を用いて堆積する。この金属膜を
ＣＦ、と０２を反応ガスとしたプラズマエツチングによ
りバターニングしてゲート電極２を形成する。次に光Ｃ
ＶＤ法のより第１．第２．第３のゲート絶縁膜３ａ、３
ｂ、３ｃであるＳｉＮｘをそれぞれ約１０００人、５０
０人、５００人の厚さで順次堆積して厚さ２０００人の
ゲート絶縁膜３を形成する。引き続き光ＣＶＤ法により
活性層となるａ−９ｉ膜４を３０００人形成し、その上
にＳｉＮｘ膜５ａ、ＳｉＯｘ膜５ｂを厚さ１０００人で
順次堆積して厚さ２０００人の積層膜を形成する。次に
この積層膜にエツチングを施して保護膜５を形成する。FIG. 1 is a cross-sectional view of a thin film transistor according to a first embodiment of the present invention. Explaining this according to the manufacturing process,
First, a metal film such as Ta or MoTa alloy is deposited to a thickness of about 2000 on a transparent insulating substrate 1 made of a glass substrate using a sputtering method. The gate electrode 2 is formed by patterning this metal film by plasma etching using CF and 02 as reaction gases. Next, light C
1. From the VD method. Second. Third gate insulating film 3a, 3
Approximately 1000 and 50 SiNx b and 3c, respectively.
A gate insulating film 3 having a thickness of 2,000 thick is formed by sequentially depositing the gate insulating film 3 to a thickness of 0 and 500 thick. Subsequently, a 3000 layer a-9i film 4, which will become an active layer, is formed by photo-CVD, and a SiNx film 5a and a SiOx film 5b are sequentially deposited thereon to a thickness of 1000 layers to form a laminated film with a thickness of 2000 layers. . Next, this laminated film is etched to form a protective film 5.
この後、保護膜５をマスクとしてａＳｉＳｉ膜面表面上
−ミックコンタクト層として厚さ５００人のｎ”ａ−５
ｉ膜６を形成する。最後に金属膜を形成し、これをバタ
ーニングすることによりソース電極７．ドレイン電極８
を形成して薄膜トランジスタが完成する。After that, using the protective film 5 as a mask, a layer of n"a-5 with a thickness of 500 nm is applied as a micro contact layer on the aSiSi film surface.
An i-film 6 is formed. Finally, a metal film is formed and patterned to form the source electrode 7. drain electrode 8
is formed to complete the thin film transistor.
なお、上記第１の絶縁膜３ａの原料ガスとして、２ＳＣ
ＣＭのシランと９８ＳＣＣＭのアンモニアとの混合ガス
を、第２の絶縁膜３ｂの原料ガスとして流ｊ１２ｓｃｃ
Ｍのシランと流量９８ＳＣＣＭのアンモニアとの原料ガ
スに流量５０５ＣＣＭの水素を混合したガスを、第３の
絶縁膜３ｃの原料ガスとして流ｆｉ２ Ｓ ＣＣＭのシ
ランと流ｆｆｉ９８３ＣＣＭのアンモニアとの原料ガス
に流量１１００３ＣＣの水素を混合したガスを採用した
。これによりゲート絶縁膜中の水素は膜厚方向に濃度分
布を持つことになる。第２図はこの絶縁膜中の原子水素
濃度を評価した結果であり、図中、横軸はＳｉＮｘ膜の
厚さ、縦軸はＳｉＮｘ膜中の原子水素濃度である。この
ように３つの絶縁膜からなるゲート絶縁膜３中の水素濃
度分布は、それぞれの絶縁膜中では一定濃度で、第３の
ゲート絶縁膜３ｃから第１のゲート絶縁膜３ａの順に膜
厚方向に濃度が低くなる分布を呈している。Note that 2SC is used as the raw material gas for the first insulating film 3a.
A mixed gas of CM silane and 98 SCCM ammonia is flowed as a raw material gas for the second insulating film 3b.
A gas obtained by mixing hydrogen at a flow rate of 505 CCM with a raw material gas of silane M and ammonia at a flow rate of 98 SCCM is used as a raw material gas for the third insulating film 3c. A gas mixed with 11,003 cc of hydrogen was used. As a result, hydrogen in the gate insulating film has a concentration distribution in the film thickness direction. FIG. 2 shows the results of evaluating the atomic hydrogen concentration in this insulating film. In the figure, the horizontal axis is the thickness of the SiNx film, and the vertical axis is the atomic hydrogen concentration in the SiNx film. In this way, the hydrogen concentration distribution in the gate insulating film 3 consisting of three insulating films is constant in each insulating film, and is distributed in the film thickness direction from the third gate insulating film 3c to the first gate insulating film 3a. It exhibits a distribution in which the concentration decreases.
第３図は本発明者らがＳｉＮｘ膜中に於ける水素の影響
にについて研究した結果である。図中、横軸はＳｉＮｘ
膜中の原子水素濃度、左縦軸はＳｉＮｘ膜の内部応力、
右縦軸はＳｉＮｘ膜中の欠陥密度、実線は内部応力と水
素濃度の関係を示し、破線は欠陥密度と水素濃度の関係
を示す。この図から分かるようにＳｉＮｘ膜の内部応力
は水素濃度が高いほど引張り応力が大きくなり、逆に欠
陥密度は水素濃度が高いほど小さくなっている。FIG. 3 shows the results of research conducted by the present inventors on the influence of hydrogen in the SiNx film. In the figure, the horizontal axis is SiNx
The atomic hydrogen concentration in the film, the left vertical axis is the internal stress of the SiNx film,
The right vertical axis shows the defect density in the SiNx film, the solid line shows the relationship between internal stress and hydrogen concentration, and the broken line shows the relationship between defect density and hydrogen concentration. As can be seen from this figure, as for the internal stress of the SiNx film, the higher the hydrogen concentration, the greater the tensile stress, and conversely, the higher the hydrogen concentration, the lower the defect density.
したがって、上記実施例のような構成の薄膜トランジス
タは、活性層とゲート絶縁膜３とが内部応力の差が小さ
いａ−３ｉ膜４と第３のゲート絶縁膜３ａとで接合して
いるので従来の薄膜トランジスタのようにこの界面で大
きな応力歪みを受けない。その結果、膜剥離の発生頻度
が非常に小さくなる。さらに高濃度の水素を含む第１．
第２のゲート絶縁膜３ａ、３ｂの存在により、第１のゲ
ート絶縁膜３ａ中の欠陥密度が高いことで絶縁膜として
の機能が低下しても、ゲート絶縁膜３全体として緻密な
絶縁膜として働く。Therefore, in the thin film transistor configured as in the above embodiment, the active layer and the gate insulating film 3 are joined by the a-3i film 4 and the third gate insulating film 3a, which have a small difference in internal stress. Unlike thin film transistors, this interface does not experience large stress strains. As a result, the frequency of occurrence of film peeling becomes extremely low. The first one contains even higher concentration of hydrogen.
Due to the presence of the second gate insulating films 3a and 3b, even if the function as an insulating film is reduced due to the high defect density in the first gate insulating film 3a, the gate insulating film 3 as a whole remains a dense insulating film. work.
第４図は、本発明に係る第２の実施例を示す薄膜トラン
ジスタの断面図である。なお第１図と同一機能部分には
同一符号を付し、詳しい説明は省略する。FIG. 4 is a cross-sectional view of a thin film transistor showing a second embodiment of the present invention. Note that the same functional parts as in FIG. 1 are denoted by the same reference numerals, and detailed explanations will be omitted.
この実施例が先に説明した第１の実施例と異なる点は、
透光性絶縁基板１上にゲート電極２を設けた後、光ＣＶ
Ｄ法を用いて第１．第２のゲート絶縁膜１３ａ、１３ｂ
であるＳｉＯｘ膜をそれぞれ５００人の厚さで順次堆積
し、さらにこのゲート絶縁膜１３ｂ上に第３．第４のゲ
ート絶縁膜１３ｃ、１３ｄとしてＳｉＮｘ膜を各々５０
０人の厚さで順次堆積して絶縁膜１３をＳｉＯｘ膜とＳ
ｉＮｘ膜との積層膜としたことである。This embodiment differs from the first embodiment described above as follows:
After providing the gate electrode 2 on the transparent insulating substrate 1, optical CV
First, using method D. Second gate insulating film 13a, 13b
A third SiOx film is sequentially deposited to a thickness of 500 nm each, and a third SiOx film is further deposited on this gate insulating film 13b. SiNx films are each used as the fourth gate insulating films 13c and 13d.
The insulating film 13 is formed by sequentially depositing SiOx film and S to a thickness of 0.
The reason is that it is a laminated film with an iNx film.
このゲート絶縁！ＩＩＢ中の原子水素濃度を測定したと
ころ第５図に示すような結果が得られた。すなわち、４
つの絶縁膜からなるゲート絶縁膜１３中の膜厚方向の水
素濃度分布は、それぞれの絶縁膜中では一定濃度で、活
性層に近い絶縁膜程濃度が低くなる分布を呈している。This gate insulation! When the atomic hydrogen concentration in IIB was measured, the results shown in FIG. 5 were obtained. That is, 4
The hydrogen concentration distribution in the thickness direction of the gate insulating film 13, which is made up of two insulating films, is such that each insulating film has a constant concentration, and the concentration becomes lower as the insulating film is closer to the active layer.
参考までに、ＳｉＯｘ膜中の水素濃度と内部応力の関係
は第６図に示すようになる。For reference, the relationship between hydrogen concentration and internal stress in the SiOx film is shown in FIG.
この実施例のような構成の薄膜トランジスタでも、第１
の実施例と同様にａ−Ｓｔ膜４は、４つのゲート絶縁膜
中で最も内部応力の差が小さい第１のゲート絶縁膜１３
ｄと接する。その結果、活性層とゲート絶縁膜３との接
合面での膜剥離は起こり難くなり、さらに第２．第３．
第４のゲート絶縁膜１３ｂ、１３ｃ、１３ｄにより絶縁
膜として強化されている。Even in a thin film transistor configured as in this example, the first
Similarly to the embodiment, the a-St film 4 is the first gate insulating film 13 which has the smallest difference in internal stress among the four gate insulating films.
Contact with d. As a result, film peeling at the bonding surface between the active layer and the gate insulating film 3 becomes less likely to occur. Third.
The fourth gate insulating films 13b, 13c, and 13d strengthen the insulating film.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、上記実施例のように水素濃度分布を段階的
に変化させるのではなく連続的に変化させても良い。す
なわち、第７図に示すように活性層から膜厚方向に対し
て遠ざかるにしたがい濃度が高くなるようにゲート絶縁
膜中の水素濃度分布を設定をしても良い。Note that the present invention is not limited to the embodiments described above. For example, the hydrogen concentration distribution may be changed continuously instead of being changed stepwise as in the above embodiment. That is, as shown in FIG. 7, the hydrogen concentration distribution in the gate insulating film may be set so that the concentration increases as the distance from the active layer in the film thickness direction increases.
また、ゲート絶縁膜中の水素濃度を制御するために用い
られる方法は上記実施例で用いた原料ガスの希釈法に限
らず、例えば、反応時の紫外線。Further, the method used to control the hydrogen concentration in the gate insulating film is not limited to the method of diluting the source gas used in the above embodiments, but also, for example, using ultraviolet rays during reaction.
赤外線などの光照射量の増減、膜形成後のＨ２プラズマ
処理等で行なっても良い。This may be carried out by increasing or decreasing the amount of light irradiation such as infrared rays, or by H2 plasma treatment after film formation.
さらにまた、ゲート絶縁膜の形成方法は光ＣＶＤ法に限
らず、例えばプラズマＣＶＤ法、熱ＣＶＤ法、もしくは
スパッタリング法を用いてもかまわない。Furthermore, the method for forming the gate insulating film is not limited to the photo-CVD method, and for example, a plasma CVD method, a thermal CVD method, or a sputtering method may be used.
なお、本発明はゲート絶縁膜のみならず、例えば保護膜
に適用しても良い。要するに本発明は、Ｓ ｉＮｘ膜ま
たはＳｉＯｘ膜とそれらの膜の内部応力と異なる膜との
接合箇所であれば種々変形して実施することができる。Note that the present invention may be applied not only to the gate insulating film but also to, for example, a protective film. In short, the present invention can be implemented with various modifications as long as it is a joint between an SiNx film or a SiOx film and a film that has a different internal stress.
［発明の効果コ
以上述べたように本発明によれば、内部応力差に起因す
る膜剥離が防止できるので信頼性が向上して優れた特性
のＴＰＴを得ることができる。[Effects of the Invention] As described above, according to the present invention, film peeling caused by internal stress differences can be prevented, so reliability can be improved and a TPT with excellent characteristics can be obtained.
第１図は本発明の第１の実施例に係る薄膜トランジスタ
の断面図、第２図は第１実施例に係るゲート絶縁膜中の
水素濃度を示す図、第３図はＳｉＮｘ膜の内部応力と水
素濃度との関係を示す図、第４図は第２の実施例に係る
薄膜トランジスタの断面図、第５図は第２実施例に係る
ゲート絶縁膜中の水素濃度を示す図、第６図はＳｉＮｘ
膜の内部応力と水素濃度との関係を示す図、第７図はゲ
ート絶縁膜中の水素濃度を示す図、第８図は従来の薄膜
トランジスタの断面図である。
１・・・透光性絶縁基板、２・・・ゲート電極、３゜３
ａ、３ｂ、３ｃ、１３，１３ａ、１３ｂ。
１３ｃ、１３ｄ−・・ゲート絶縁膜、４ ・＝ ａ −
Ｓ ｉ膜、５．５ａ、５ｂ−・・保護膜、６−ｎ” ａ
−Ｓ ｉ膜。
７・・・ソース電極、８・・・ドレイン電極。FIG. 1 is a cross-sectional view of a thin film transistor according to the first embodiment of the present invention, FIG. 2 is a diagram showing the hydrogen concentration in the gate insulating film according to the first embodiment, and FIG. 3 is a diagram showing the internal stress of the SiNx film. 4 is a cross-sectional view of the thin film transistor according to the second embodiment, FIG. 5 is a diagram showing the hydrogen concentration in the gate insulating film according to the second embodiment, and FIG. 6 is a diagram showing the relationship with hydrogen concentration. SiNx
FIG. 7 is a diagram showing the relationship between internal stress of a film and hydrogen concentration, FIG. 7 is a diagram showing hydrogen concentration in a gate insulating film, and FIG. 8 is a cross-sectional view of a conventional thin film transistor. 1... Transparent insulating substrate, 2... Gate electrode, 3゜3
a, 3b, 3c, 13, 13a, 13b. 13c, 13d--gate insulating film, 4.=a-
Si film, 5.5a, 5b--protective film, 6-n"a
-Si membrane. 7... Source electrode, 8... Drain electrode.
Claims (2)
された非晶質シリコン膜と、この非晶質シリコン膜にコ
ンタクトするソースおよびドレイン電極と、前記非晶質
シリコン膜の上部または下部にゲート絶縁膜を介して配
設されたゲート電極とを有する薄膜トランジスタにおい
て、前記ゲート絶縁膜は少くとも前記非晶質シリコン膜
に近い部分が窒化シリコン膜により形成され、かつその
窒化シリコン膜は前記非晶質シリコン膜側では水素濃度
が低くなる膜厚方向の水素濃度分布を有することを特徴
とする薄膜トランジスタ。(1) A substrate, an amorphous silicon film formed in a predetermined pattern on the substrate, source and drain electrodes in contact with the amorphous silicon film, and a gate on the top or bottom of the amorphous silicon film. In a thin film transistor having a gate electrode disposed through an insulating film, at least a portion of the gate insulating film close to the amorphous silicon film is formed of a silicon nitride film, and the silicon nitride film is A thin film transistor characterized by having a hydrogen concentration distribution in the film thickness direction where the hydrogen concentration is lower on the silicon film side.
有する窒化シリコン膜と酸化シリコン膜との積層膜を有
することを特徴とする請求項１記載の薄膜トランジスタ
。(2) The thin film transistor according to claim 1, wherein the gate insulating film has a laminated film of a silicon nitride film and a silicon oxide film having a hydrogen concentration distribution in the film thickness direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4449490A JP2885458B2 (en) | 1990-02-27 | 1990-02-27 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4449490A JP2885458B2 (en) | 1990-02-27 | 1990-02-27 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03248569A true JPH03248569A (en) | 1991-11-06 |
| JP2885458B2 JP2885458B2 (en) | 1999-04-26 |
Family
ID=12693110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4449490A Expired - Fee Related JP2885458B2 (en) | 1990-02-27 | 1990-02-27 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2885458B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134712A (en) * | 2005-11-07 | 2007-05-31 | Samsung Electronics Co Ltd | Semiconductor device and manufacturing method of the same |
| JP2012099847A (en) * | 2012-01-13 | 2012-05-24 | Sony Corp | Method for manufacturing thin film transistor substrate |
| JP2013254950A (en) * | 2012-05-10 | 2013-12-19 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP2017228800A (en) * | 2012-05-10 | 2017-12-28 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
1990
- 1990-02-27 JP JP4449490A patent/JP2885458B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134712A (en) * | 2005-11-07 | 2007-05-31 | Samsung Electronics Co Ltd | Semiconductor device and manufacturing method of the same |
| JP2012099847A (en) * | 2012-01-13 | 2012-05-24 | Sony Corp | Method for manufacturing thin film transistor substrate |
| JP2013254950A (en) * | 2012-05-10 | 2013-12-19 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US9711652B2 (en) | 2012-05-10 | 2017-07-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2017126794A (en) * | 2012-05-10 | 2017-07-20 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP2017228800A (en) * | 2012-05-10 | 2017-12-28 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US9966475B2 (en) | 2012-05-10 | 2018-05-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2018201047A (en) * | 2012-05-10 | 2018-12-20 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP2019125809A (en) * | 2012-05-10 | 2019-07-25 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2885458B2 (en) | 1999-04-26 |
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