JPH03248537A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form wirings flat by opening a contact hole at a gate electrode in a self-alignment manner, and burying a polycrystalline silicon in the hole. CONSTITUTION:A gate electrode 6 formed with a first insulating film 4 and a first polycrystalline silicon film 5 on the upper surface is formed on the main surface of a substrate 1 through a gate insulating film 2, and with the electrode 6 as a mask an interlayer insulating film 8a is flatly deposited. Then, the film 8 existing on the contact hole 15 forming region between adjacent gate electrodes 6 is selectively removed by etching to open a self-alignment contact hole 15 at the electrode 6, a sidewall insulating film 11 is formed on the side of the hole 15, a second polycrystalline silicon 12 is deposited, and etched back to allow a second polycrystalline silicon film 13 to remain only on the buried part of the hole 15. Thus, when aluminum wirings 14 are formed, the step coverage of the wiring 14 at the part of the hole 15 is improved, and discontinuity can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a self-aligned contact hole in a gate electrode of a MOS type semiconductor device.

[Conventional technology]

Typical examples of conventional techniques related to the method of forming self-aligned contact holes on gate electrodes are shown in longitudinal cross-sectional views in FIGS. 3(a) to 3(e).
).

First, as shown in FIG. 3(a), an N-type gate electrode polycrystalline silicon film 3 is deposited on one main surface of a P-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. A first insulating film 4 is deposited on the upper surface of the polycrystalline silicon film 3.

Next, as shown in FIG. 3(b), the first insulating film 4 and the polycrystalline silicon film 3 for gate electrode are simultaneously patterned to form a gate electrode 6, and ions are formed using the gate electrode 6 as a mask. An N-type impurity diffusion layer 7 is formed by implantation.

Next, as shown in FIG. 3(c), a second insulating film 8 is deposited on the entire surface.

Subsequently, as shown in FIG. 3(d), the edge of the pattern of the photoresist 9 for opening the contact hole is placed on the upper surface of the second insulating film 8 on the two adjacent gate electrodes 6. Form a photoresist as shown and perform RIE using this as a mask.
Contact hole 1 is made by (reactive ion etching) method.
5 is opened, and at the same time, a sidewall insulating film 11 made of the second insulating film 8 is formed on the side surface of the contact hole.

Next, as shown in FIG. 3(e), after removing the photoresist 9, an aluminum wiring 14 is connected to the N-type impurity diffusion layer 7 through the contact hole sandwiched between the two gate electrodes 6. form.

[Problem to be solved by the invention]

The conventional method of forming a contact hole in a self-aligned manner between adjacent gate electrodes has been described above. The aspect ratio, which represents the ratio to the depth, increases, and when forming aluminum wiring,
This has the disadvantage that the step coverage of the aluminum wiring at the contact hole becomes poor, resulting in wire breakage.

The above-mentioned conventional example is an example of a gate electrode with a single layer structure, but
This tendency is particularly noticeable when the gate electrode has a two-layer structure like a nonvolatile semiconductor memory element.

[Means to solve the problem]

A method of forming a self-aligned contact hole in a gate electrode of a MOS type semiconductor device according to the present invention includes forming a first insulating film on the main surface of a semiconductor substrate via a gate insulating film, a first insulating film on the upper surface in a self-aligned manner, A gate electrode is formed with a polycrystalline silicon film formed on it, an impurity diffusion layer is formed using this as a mask, an interlayer insulating film is deposited flatly, and then an interlayer insulating film is formed until the polycrystalline silicon film above the gate electrode is exposed. Etching back the insulating film, and then selectively etching away the interlayer insulating film existing in the contact hole formation region between adjacent gate electrodes to open a self-aligned contact hole in the gate electrode; After depositing the second insulating film over the entire surface, a sidewall insulating film made of the second insulating film is formed on the side surface of the contact hole by reactive ion etching, a second polycrystalline silicon film is deposited, and a second polycrystalline silicon film is deposited. The method includes a step of etching back the first polycrystalline silicon film to leave the second polycrystalline silicon film only in the portion buried in the contact hole.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(j) are longitudinal sectional views of a first embodiment of the present invention.

First, as shown in FIG. 1(a), an N-type gate electrode polycrystalline silicon film 3 is deposited on the entire surface of a P-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. A first insulating film 4 is deposited on the upper surface of the crystalline silicon film 3,
A first polycrystalline silicon film 5 is deposited on the upper surface of the first insulating film 4 .

Next, as shown in FIG. 1(b), a first polycrystalline silicon film 5. The first insulating film 4 and the polycrystalline silicon film 3 for gate electrode are simultaneously patterned to form a gate electrode 6, and N is implanted by ion implantation using the gate electrode 6 as a mask.
A type impurity diffusion layer 7 is formed.

Next, as shown in FIG. 1(c), an interlayer insulating film 8 is formed over the entire surface.
A is deposited and its upper surface is made flat by heat treatment.

Subsequently, as shown in FIG. 1(d), the interlayer insulating film 8a is etched back until the first polycrystalline silicon film 5 is exposed.

Next, as shown in FIG. 1(e), the edge of the photo resist pattern for opening the contact hole is placed on the upper surface of the first polycrystalline silicon film 5 on the two adjacent gate electrodes 6. A photoresist 9 is formed so that the end is covered, and using this as a mask, the interlayer insulating film 8a is etched to open a contact hole 15.

Next, as shown in FIG. 1(f), a second insulating film 10 is deposited over the entire surface.

Subsequently, as shown in FIG. 1(g), the contact hole 15 is
The second insulating film 10 is etched by RIE until the N-type impurity diffusion layer 7 on the bottom surface of the contact hole 1 and the first polycrystalline silicon film 5 on the top of the gate electrode 6 are exposed.
A sidewall insulating film 11 made of a second insulating film 10 is formed on the side surface of 5.

Next, as shown in FIG. 1(h), a second polycrystalline silicon film 12 having a thickness approximately equal to the depth of the contact hole 15 is deposited over the entire surface.

Subsequently, as shown in FIG. 1(i), the contact hole 15 is
Etching back of the polycrystalline silicon is performed to remove the polycrystalline silicon film 12 other than the inside and the first polycrystalline silicon film 5 above the gate electrode 6, thereby forming the contact hole 1.
A buried polycrystalline silicon film 13 is formed by leaving the second polycrystalline silicon film 12 only inside the polycrystalline silicon film 5 . Thereafter, N-type impurities are introduced into the buried polycrystalline silicon 13.

Finally, as shown in FIG. 1(j), aluminum wiring 14 is formed.

FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention.

In the first embodiment, the gate electrode has an 11-layer structure, but in this embodiment, the gate electrode has two layers, the first gate electrode 17 and the second gate electrode 19. A second gate electrode is provided between the first gate electrode 17 and the second gate electrode 19.
A gate insulating film 18 is present, and a first gate electrode 17 is formed on the P-type semiconductor substrate 1 with the first gate insulating film 16 interposed therebetween.

In the manufacturing method shown in FIG. 2, a first
gate insulating film 16. A film constituting the first gate electrode,
Second gate insulating film 18. Film constituting the second gate electrode, first insulating film 4. After passing through the steps of sequentially forming the first polycrystalline silicon film, the manufacturing method of the first embodiment is followed.

〔Effect of the invention〕

As explained above, the present invention is capable of opening a contact hole in a self-aligned manner with respect to a gate electrode formed through a gate insulating film on one main surface of a semiconductor substrate, and also having polycrystalline silicon buried in the contact hole. Therefore, even if a contact hole is formed between adjacent gate electrodes and a wiring is connected thereto, the level difference at the top of the contact hole is extremely small due to the presence of buried polycrystalline silicon in the contact hole. The step coverage of the wiring there is extremely good,
Furthermore, since the wiring can be formed almost flat, disconnection of the wiring does not occur.

Therefore, when forming a contact hole between adjacent gate electrodes, the gap between the gate electrodes can be narrowed to the limit of lithography technology, which is effective in miniaturizing semiconductor devices.

[Brief explanation of drawings]

FIGS. 1(a) to (j>) are longitudinal sectional views of the first embodiment of the present invention, FIG. 2 are longitudinal sectional views of the second embodiment of the present invention, and FIGS. 3(a, ) to ( e) is a vertical cross-sectional view of the conventional technology. 1... P-type semiconductor substrate, 2... gate insulating film, 3...
... Polycrystalline silicon film for gate electrode, 4... First insulating film, 5... First polycrystalline silicon film, 6... Gate electrode, 7... N-type impurity diffusion layer, 8 , 10... Second insulating film, 8a... Interlayer insulating film, 9 Photoresist, 11... Sidewall insulating film, 12... Second polycrystalline silicon film, 13... Embedded polycrystalline Silicon, 14... Aluminum wiring, 15... Contact hole, 16... First gate insulating film, 17... First gate electrode, 18...
- Second gate insulating film, 19... second gate electrode.

Claims (2)

[Claims] (1) A step of sequentially forming a gate insulating film, a film constituting a gate electrode, a first insulating film, and a first polycrystalline silicon film on one main surface of a semiconductor substrate of a first conductivity type; simultaneously patterning a polycrystalline silicon film, the first insulating film, and a film constituting the gate electrode to form a gate electrode made of the film constituting the gate electrode, using the gate electrode as a mask; By using ion implantation method,
forming an impurity diffusion layer of a second conductivity type on the surface of the semiconductor substrate; forming an interlayer insulating film with a flat surface; etching back the interlayer insulating film to expose the first polycrystalline silicon film above the gate electrode; forming a contact hole between adjacent gate electrodes. opening a self-aligned contact hole in the gate electrode by selectively etching and removing the interlayer insulating film existing in the region; the first polycrystalline silicon film above the gate electrode; depositing a second insulating film covering the entire exposed surface of the contact hole and forming a sidewall insulating film made of the second insulating film on the side surface of the contact hole by reactive ion etching; depositing a second polycrystalline silicon film that covers the entire exposed surface of the upper first polycrystalline silicon film and the interlayer insulating film and fills the contact hole;
The second polycrystalline silicon film that has been etched back to cover the entire exposed surface of the first polycrystalline silicon film above the gate electrode and the interlayer insulating film, and the first polycrystalline silicon film above the gate electrode. A method for manufacturing a semiconductor device, comprising the steps of: completely removing the second polycrystalline silicon film and burying the second polycrystalline silicon film only inside the contact hole. (2) A first gate insulating film, a film forming the first gate electrode, a second gate insulating film, and a film forming the second gate electrode on one main surface of the semiconductor substrate of the first conductivity type. , a step of sequentially forming a first insulating film and a first polycrystalline silicon film; a film constituting the first polycrystalline silicon film, the first insulating film, and the second gate electrode; The gate insulating film and the film forming the first gate electrode are simultaneously patterned to form the film forming the first gate electrode, the second gate insulating film, and the second gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a gate electrode having a two-layer structure made of a film comprising: