JPH0324820A - Output circuit - Google Patents

Abstract

PURPOSE:To suppress ringing to shorten an access time by generating a one-shot pulse before the fall of an output voltage to 0V or lower at the time of outputting the low level, and turning on an n-channel transistor TR having a low threshold voltage for a moment to apply the voltage from VCC to the output. CONSTITUTION:When a signal OEM goes to the high level, a node (c) goes to the low level and a node (d) goes to the high level, and a TR 9 is turned off and a TR 10 is turned on, and the low level is outputted to an output Dout. Since the signal OEM goes to the high level, a node N1 goes to the low level, and a node N2 goes to the high level after a short delay. Both of nodes N1 and N2 go to the low level for a moment, and this low level is outputted to a NOR gate 16 to generate the one-shot pulse, which goes to the high level for a moment, in the output of the NOR gate 16. A TH 19 is turned on for the moment, when the pulse of a node N3 goes to the high level, to supply the voltage to the output Dout, and the negative voltage of the output Dout is cancelled. Thus, ringing is eliminated.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to an output circuit for a semiconductor device. [Prior Art] Fig. 3 is a circuit diagram of a conventional output circuit. (1
)～(4)． (7), (8) are inverters, (5)
, (6) is a NAND game} , (9), (lO) PaD
Channel is a transistor. However, the dark value voltage of the transistor (9) is set lower than that of the transistor (10). In addition, RD is a signal OaV from the output preamplifier, a signal that determines the output state of the output circuit, C11) is a parasitically shaped resistance, (l2) is a parasitically shaped inductance, (13) is a parasitically formed capacitance. FIG. 4 is a timing chart of each signal and each node when the output is Low.

Next, the operation will be explained. The signal RD taken from the output preamp is sent to inverters (1), (2), (3) (
4), the signals are converted into complementary signals and transmitted to nodes a and b.

Here, when the OEM signal is Low, both nodes c and d are Low.
ow, and the output goes into a high impedance state. O
When the EM signal becomes Eiigh, if the HD signal is High, the HiEl. h is transmitted to node C, Low of node b is transmitted to node d, and transistor (9)
is on, Tofunjinuta (10) is off, and DOut
When the 5RD signal that outputs a High value is Low, the Low of node a goes to node C, and the liigh of node b
is transmitted to node d, transistor (9) is turned off,
Transistor (10) turns on and goes low to D out
The value of is output. At this time, when outputting 111gh, D out immediately becomes OV due to the charge charged in the parasitically shaped capacitance (13), the parasitically shaped resistance (11) and the inductance (12). O after several oscillations in the output voltage called ringing
It becomes v.

[Problem J that Hatsuo is trying to solve Since the conventional output circuit was constructed as described above, there was a problem in that it caused a voltage gimp.

This invention was made to solve the above-mentioned r#lJM point, and aims to provide an output circuit that suppresses degradation and speeds up access time.

[Means for Solving the Problems] When the output circuit according to the present invention outputs Low, it generates a one-shot balne before the output voltage becomes lower than OV, and momentarily activates the p-channel transistor with a low threshold ffl voltage. It is turned on for a period of time, and a voltage is supplied to the output from Vcc.

[Effect]

The output circuit according to the present invention alleviates ringing by supplying a voltage from Vcc before the output voltage becomes below OV.

〔Example" An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an output circuit showing one embodiment of the present invention, and in the figure, (1) to (4) . (7), (8)
, (14), (15), (17), (l8) are inpertors, (5), (6) PANAeJD gates, (9), (1
0) and (19) are p-channel transistors. However, transistors (9) and (l9) are transistors (
lO) The transistor with low value voltage is also low (l9
) is set to have a shorter channel width than the transistor (9). (16) is a NOR gate. FIG. 2 is a timing chart of each signal and each node in FIG. 1.

Next, the operation of the output circuit according to the present invention at the time of Low output will be explained. The low level of the RD signal captured by the output preamplifier b is transferred to the D node a by inverters (1) to (4).
is Low, and node b becomes ligh. Here 01
, M signal becomes High, the node C becomes Low, and the node d becomes High, transistor (9) is turned off, transistor (10) is turned on, and Low is about to be output to Dout. On the other hand, due to the OEM signal being High, the υ node N- goes Low, and after a short delay, the node N2 goes Low.
Goes from OW to High. Here, there is a moment when both nodes N1%N20 become Low, and this node Nl%N2
By inputting the two Low values of υNOR game} (16), the output of υNOR game} (16) becomes High for a moment
A one-shot pulse of gh is generated. The transistor (19) is turned on for a moment when the pulse on the node level goes high, supplies voltage from Vcc to D out, and D
Cancels out negative voltage. In this way Dou
By canceling the first vibration of t, subsequent vibrations are eliminated and ringing can be eliminated. Imperter (1
7) and (18) are NOR gates in which the channel width W and channel length L are optimally set.} The pulse generated in (16) is delayed in time, and the voltage supply from VCC is DoutLy)! This is to turn on the transistor (19) as it does at the first oscillation of pressure.

The circuit that generates the one-shot pulse shown in Figure 1 is an inverter (11) (12) and a NOR gate (16)
However, a one-shot pulse can also be generated with a configuration consisting of a HAND gate, an inverter, a DOR gate, and an inverter 1, or an AND gate and an inverter. Inverters (8), (14) (15)
Alternatively, a timer that delays the waveform can be used instead of the inverters (17) and (18). Furthermore, the transistors (9), (lO), and (19) can also be made of P-channel transistors. [Effects of the Invention] As described above, according to the present invention, it is possible to suppress ringing during low output, and to improve access. Delays can be prevented.

[Brief explanation of drawings]

Figure 1 shows -5M! of the output circuit according to the present invention. A circuit diagram of the example, Fig. 2 is a timing chart of each signal and each node in Fig. 1, Fig. 3 is a circuit diagram of a conventional output circuit, and Fig. 4 is a timing chart of each signal and each node in Fig. 3. It is a chart. In the figure, (1) to (4), (7), (8), (l
4), (l5), (17), (18) are inperters, (
5), (6) are NAIID games}, (9), (10
), (19) Pp channel transistor (16) is N
It is an OR gate. In the figures, the same symbols indicate the same or corresponding parts.

Claims (1)

[Claims] First MOS that precharges the output voltage to V_c_c
In an output circuit in which a transistor and a second MOS transistor for discharging the output voltage to a GND potential are connected in series, a third MOS transistor is connected in parallel to the first MOS transistor and supplies a voltage during low output. An output circuit characterized by having a circuit that generates and delays a one-shot pulse that momentarily turns on a transistor and this third MOS transistor.