JPH0324773U - - Google Patents

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Publication number
JPH0324773U
JPH0324773U JP8466689U JP8466689U JPH0324773U JP H0324773 U JPH0324773 U JP H0324773U JP 8466689 U JP8466689 U JP 8466689U JP 8466689 U JP8466689 U JP 8466689U JP H0324773 U JPH0324773 U JP H0324773U
Authority
JP
Japan
Prior art keywords
transistor
video signal
collector
emitter
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8466689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8466689U priority Critical patent/JPH0324773U/ja
Publication of JPH0324773U publication Critical patent/JPH0324773U/ja
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例を示す回路図、第
2図は従来のクランプ回路を示す回路図、及び第
3図イ乃至ホは第2図の説明に供する為の波形図
である。 18……第1差動増幅器、21……第2差動増
幅器、24……信号源、26……第5トランジス
タ、27……第6トランジスタ、28……第7ト
ランジスタ、29……抵抗、30……コンデンサ
32……引算回路、33,34……第1及び第
2制御端子。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional clamp circuit, and FIGS. 3A to 3E are waveform diagrams for explaining FIG. . 18 ...First differential amplifier, 21 ...Second differential amplifier, 24...Signal source, 26...Fifth transistor, 27...Sixth transistor, 28...Seventh transistor, 29...Resistor, 30... Capacitor, 32 ... Subtraction circuit, 33, 34... First and second control terminals.

Claims (1)

【実用新案登録請求の範囲】 (1) エミツタが共通接続された第1及び第2ト
ランジスタから成る第1差動増幅器と、 エミツタが共通接続された第3及び第4トラン
ジスタから成る第2差動増幅器と、 映像信号を発生する信号源と、 該信号源からの映像信号がベースに印加される
とともにエミツタが前記第4トランジスタのコレ
クタに接続された第5トランジスタと、 前記信号源からの映像信号がベースに印加され
る第6トランジスタと、 一端が前記第5トランジスタのエミツタと前記
第4トランジスタのコレクタとの接続点に接続さ
れ、他端が前記第3トランジスタのコレクタに接
続された抵抗と、 ベースが前記抵抗の他端に、エミツタが前記第
1トランジスタのコレクタに接続された第7トラ
ンジスタと、 該第7トランジスタのエミツタに接続されたコ
ンデンサと、 前記第6トランジスタの出力映像信号から前記
コンデンサの電圧を引算する引算回路と、 から成り、前記第1及び第4トランジスタのベ
ースと前記第2及び第3トランジスタのベースに
互いに逆相のクランプ用パルスを印加し、前記引
算回路の出力端より一定レベルでクランプされた
映像信号を得るようにしたことを特徴とするクラ
ンプ回路。 (2) 前記第6トランジスタの出力端と前記引算
回路の入力端との間にレベルシフト手段を有する
ことを特徴とする請求項第1項記載のクランプ回
路。
[Claims for Utility Model Registration] (1) A first differential amplifier consisting of first and second transistors whose emitters are commonly connected; and a second differential amplifier consisting of third and fourth transistors whose emitters are commonly connected. an amplifier; a signal source that generates a video signal; a fifth transistor to which the video signal from the signal source is applied to its base and whose emitter is connected to the collector of the fourth transistor; and a video signal from the signal source. is applied to its base; a resistor having one end connected to a connection point between the emitter of the fifth transistor and the collector of the fourth transistor and the other end connected to the collector of the third transistor; a seventh transistor having a base connected to the other end of the resistor and an emitter connected to the collector of the first transistor; a capacitor connected to the emitter of the seventh transistor; and an output video signal of the sixth transistor being connected to the capacitor. a subtraction circuit for subtracting the voltage of the subtraction circuit; A clamp circuit characterized in that a video signal clamped at a constant level is obtained from an output end. (2) The clamp circuit according to claim 1, further comprising level shift means between the output terminal of the sixth transistor and the input terminal of the subtraction circuit.
JP8466689U 1989-07-19 1989-07-19 Pending JPH0324773U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8466689U JPH0324773U (en) 1989-07-19 1989-07-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8466689U JPH0324773U (en) 1989-07-19 1989-07-19

Publications (1)

Publication Number Publication Date
JPH0324773U true JPH0324773U (en) 1991-03-14

Family

ID=31633292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8466689U Pending JPH0324773U (en) 1989-07-19 1989-07-19

Country Status (1)

Country Link
JP (1) JPH0324773U (en)

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