JPH03242694A - System and device for calculating affine transformation and dot memory address for character generation - Google Patents

Abstract

PURPOSE:To perform highly accurate coordinate transformation with a small circuit scale by providing a font input FiFo means storing temporarily outline font coordinate data from a host interface and a font memory. CONSTITUTION:A leak memory source address LSAR 67 stored in a register LSAR is latched in latch LB 2 through a B bus. When a dot memory is the internal memory of OFP, the contents of the LSAR are zero, so zero is latched in the LB2. A dot memory address (2yXLSHWXx>3+LSAR) 68 is outputted from an ALU and outputted as the high-order and low-order data to 25 and an FiFo 27. A bit address is outputted from a register BA 18. Thus, affine transformation and dot memory address calculation are carried out by one hardware set fast with high accuracy and the scale of the hardware is reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a character generation device in the field of computer graphics, and in particular to character enlargement and reduction.

The present invention relates to a coordinate conversion device used to realize rotation, etc., and a dot memory address calculation device for line drawing.

[Conventional technology]

For characters composed of outlines, enlarging the characters,
In order to realize reduction nine rotations, etc., it is necessary to perform coordinate transformation, such as affine transformation, on the (x+y) coordinate data that constitutes the outline.

Affine transformation from coordinates (xt y) to coordinates (xey') is expressed by the following equation.

x'=ax+by+e y'=c x+d y+f...(1
) When considering affine transformation of these outline font data, since characters and figures in the conventional computer graphics field are expressed in dot format, image data such as the coordinate transformation circuit described in JP-A-61-13380 is used. A coordinate conversion device has been proposed for .

[Problem to be solved by the invention]

The conventional coordinate transformation techniques described above are intended for image data, and are not suitable for coordinate transformation of coordinate values such as outline font data. Also.

Coordinate transformation for outline font data.

In a device that processes outline drawing, filling, and BitBLT at high speed and converts it into heavy bitmanop data on the page memory, coordinate conversion is performed accurately and at high speed, and when drawing an outline by connecting the converted coordinate values. First, it is necessary to use a multiplier to calculate the address of the dot memory that stores the dot data with respect to the starting coordinate point of the outline font data loop.

Performing these two operations in independent processing blocks, that is, having two multipliers increases the hardware scale.

However, conventional coordinate conversion devices only execute coordinate conversion, and since there is no control to execute highly accurate coordinate conversion, other operations such as highly accurate coordinate conversion and dot memory address calculation are also performed. It has been difficult to perform high-speed processing with one small circuit.

One object of the present invention is to be able to perform highly accurate coordinate conversion with a small circuit scale in a device that performs a series of processes for converting outline font data onto a page memory as bitmap data, and to be able to perform highly accurate coordinate conversion when drawing outlines. An object of the present invention is to provide an affine transformation/dot memory address calculation device for character generation that can perform necessary dot memory address calculations.

Another object of the present invention is to provide an affine transformation/dot memory address calculation device for character generation that can process highly accurate coordinate conversion and dot memory address calculation at high speed with a single piece of hardware.

Another object of the present invention is to provide an affine transformation/dot memory address calculation device for character generation that can output data necessary for increasing interpolation accuracy when coordinate-converted data is used for curve interpolation, etc. Our goal is to provide the following.

[Means to solve the problem]

In order to achieve the above object, the affine transformation/dot memory address calculation method for character generation according to the present invention is a method and apparatus that performs a series of processing for converting outline font data into heavy sotomanop data on a page memory. The coordinate data X+ and Y are read in order from the font input FiFo, which temporarily stores the outline font coordinate data from the interface and font memory, and the font input FiFo, and the coordinate data x'
, Temporarily store the affine transformation block that performs affine transformation on y and the affine transformed coordinate data.
Coordinate data is read from FiFo Q and FiFo O, and for curve interpolation data, the curve interpolation block that performs curve interpolation and the coordinate data output from the curve interpolation block are temporarily stored (FiFo 1 and FiFo
A line generation block that reads coordinate data from 1 and generates a line between the coordinate data as a bit image, a dot memory that stores the bitmap data output from the line generation block, and a dot memory that reads bitmap data from the dot memory and generates a line inside the outline. A character generation method or device OFF (outline font processor) equipped with a fill/BUTBLT block and a page memory interface that transfers a bitmap data block onto a page memory, and in the above affine transformation, input coordinate data. For Xy3', coefficient data a9 b, c, d and coordinate axis movement amount e,
Define f, x' = ax + by + e and! '=cx+
Coordinate data X at the start of a loop that calculates dy+f and further configures outline font data. , yo, the line generation block is x0 after affine transformation
Vo' or, if no affine transformation, X Os
The affine transformation block calculates the dot memory address when expanding yo onto the dot memory using one piece of hardware that performs affine transformation, and the calculated address data, coordinate data and flag data are transferred to the line generation block through the same route. This is how it was done.

In the above affine transformation block, the 8-force coordinate data subjected to affine transformation or the input and output coordinate data not subjected to affine transformation are configured with m bits for the integer part and n bits for the decimal part.

In the above affine transformation block, the internal data bus configuration is such that during affine transformation, the integer part is divided into J bits and the decimal part is divided into bits, and when the dot memory address is calculated, the integer part (j 10k) bits are calculated. .

The affine transformation/dot memory address calculation device for character generation according to the present invention includes a coordinate register for storing coordinate data x, y, a coefficient register for storing coefficient data required for the above-mentioned affine transformation, and coordinate axis movement amount data. A coordinate axis movement amount register to store, an output size register to store the output character size, a work memory base address register to store the base address of the external output memory, and coordinates to store the data X', y' after affine transformation. register, dot memory address calculation register,
It is equipped with an arithmetic unit that performs affine transformation and dot memory address calculation.

In this device, for example, the bit address that is the bit information stored in the dot memory address is the Q bit, and the bit address in the tod memory address calculation is the coordinate data of the start of the loop constituting the outline font data. Output X coordinate data
. Alternatively, the lower S bits of xo' are decoded and output.

[Effect]

According to the present invention, in a method and apparatus that performs a series of processes for converting coordinate data constituting outline font data into bitmap data on a page memory, the coordinate data is converted into bitmap data on the page memory. In order, MPU interface, font input FiFo, affine transformation block, FiFo○
2 curve interpolation block.

Character generation method or device equipped with FiFol, line generation block, dot memory, fill/BitBLT block, page memory interface When generating a line in a dot image, the affine transformation block calculates the address at which to store the start coordinate data of each loop in the dot memory among the coordinate data that makes up one character, and stores it in the same path as other coordinate data. Can be passed to the line generation block. The address of newly generated bitmap data other than the loop starting frame data is managed by the line generation block when a line is generated, but there is no calculation that requires a multiplier. Also, when the line generation block requires a dot memory address, it is when a line is generated from the start coordinate data of each loop to the next coordinate data of the coordinate data that makes up one character, so the start coordinate data The dot memory address calculated in the previous affine transformation block can be output to the next FiFoO in the same way as the coordinate data.

In other words, the line generation block does not need to have a multiplier, there is no need for a dedicated bus to receive and receive dot memory addresses, and since the dot memory address is internally calculated from the coordinate data at the start of the loop, one character By affine transformation for generation and dot memory address calculation method,
In a device that performs a series of processes for converting outline font data into bitmap data on a page memory, the circuit scale can be significantly reduced and a series of processes can be performed at high speed.

According to the present invention, according to the affine transformation/dot memory address calculation method for character generation, output coordinate data that has undergone affine transformation or input and output coordinate data that has not been affine transformed is composed of m bits for the integer part and n bits for the decimal part. By doing this, when precision is required from the next curve interpolation block onwards, by adding a decimal part and outputting it, it is possible to achieve highly accurate character output.
Dot memory address calculation can be realized with one control.

According to the present invention, in the affine transformation/dot memory address calculation method for character generation, the configuration of the internal data bus is divided into j bits for the integer part and bits for the decimal part during affine transformation, and the integer part ( j
By calculating in terms of 10 k) bits, highly accurate affine transformation can be performed, and dot memory address calculation can be performed without adding new circuits or buses, so the overall scale of the device can be reduced.

〔Example〕

Examples of the present invention will be described in detail below.

FIG. 4 shows an example of a system configuration using a device OFF (outline font processor) that performs a series of processes for converting coordinate data constituting outline font data into bitmap data on a page memory. address bus, data bus.

A system bus 47 consisting of a control signal bus includes a host C
P U39. System memory 40. Outline font memory 41. DMA controller 42, 0FP43,
A page memory controller 44 is connected to OFF, a page memory controller is connected to OFF, a page memory 45 is connected to the page memory controller, and the page memory is connected to the printer and CRT system 46.
It is connected to the. This system is mainly used in page printer controllers and CRT systems. For example, when the DMAC is turned OFF, it is determined by a signal from the host CPU.
Coordinate data, which is outline font data, is received from the 1-line font memory using the 1-line font memory, and the page memory controller is used to convert it into bitmap data and write it onto the page memory.

FIG. 2 shows an internal block diagram of OFF. Here, ○
The FP 38 has a font input FiFo 28. which is inside the post interface 36 and the host interface. Affine transformation block 29, FiFo O33, curve interpolation block 30. FiFo 134. Line generation block 31, dot memory 35. Fill BitBLT
It consists of a block 32 and a page memory interface 37.

From the host interface, an address bus, a data bus, and a group of control signals connected to the system bus are output.

Further, an address bus, a data bus, and a group of control signals connected to the page memory controller are connected to the page memory interface.

Next, the OFF operation will be explained. The coordinate data read from the outline font memory is temporarily stored in the font input FiFo within the host interface. The affine transformation block sequentially reads the coordinate data Xly from the font input F, executes the affine transformation, and sends the coordinate data x, y' to FiFo O. Appear. The curve interpolation block reads the coordinate data x', y' temporarily stored in the FiFoO, and in the case of curve data, generates new coordinate data representing the curve and transfers it to the FiFoO.
Output to 1. The line generation block is FiF.

1, reads the temporarily stored coordinate data, generates a line between the coordinate points as a dot image, creates the outline of the character, and writes it to the dot memory as bitmap data. The fill-in BitBLT block reads bitmap data representing the outline of each character from the dot memory, fills the inside of the @ part, and writes the bitmap data onto the page memory via the page memory interface while transferring the bitmap data in blocks.

Here, when the line generation block reads the coordinate data from FiFo 1 and generates a line between the coordinate points as a dot image, the first of several loops made up of the coordinate data that makes up the outline font data. It is necessary to calculate the position of the coordinate data to be written into the dot memory as dot image data (referred to as dot memory address calculation). If this calculation is performed by the line generation block, one more multiplier is required in addition to the affine transformation block, and ○F
Since there are two multipliers in P38, the scale of the device increases. For example, if this calculation is done outside of OFF, such as by the host CPU, and set in an internal register, not only will the processing speed of OFF decrease, but also the
This results in a decrease in PU throughput. Furthermore, when considering the sharing of multipliers, a dedicated bus for multiplication and arbitration control of the multipliers and buses become necessary.

Therefore, in the OFF configuration shown in FIG. 2, the line generation block only needs to calculate the dot memory address immediately before generating a line between the first coordinate data and the second coordinate data of the loop. Therefore, it is sufficient to read the dot memory address immediately before reading the first coordinate data. In other words, the affine transformation unit that has a multiplier performs dot memory address calculation on the first coordinate data of the loop along with affine transformation, and outputs it to the FiFoO immediately before outputting the first transformed coordinate data. For example, the line generation block can receive dot memory addresses as well as coordinate data when needed. Therefore, in order to realize the above, the affine transformation block performs normal affine transformation and dot memory address calculation.

FIG. 6 explains dot memory address calculation. FIG. 6(a) shows the relationship between coordinate data and dot memory addresses when the line generation block reads coordinate data and generates lines between coordinate points. Part of the loop of outline font data that makes up one character is coordinate data, P 1 , P z
, P J , P , t ,' P 5 (=I), ). The line generation block generates a line from P to P2. At this time, the dot memory address storing P is read immediately before reading Pl. From P2 onwards, dot memory addresses are automatically calculated when lines are generated as dot images. Therefore, the affine transformation block performs the following dot memory address calculation only for P.

For example, when P□(36,7) is converted to a dot image and stored in the dot memory, the dot memory address is address 60. Here, the width of one address, that is, the bit address, which is bit information stored in a dot memory address, is assumed to be bytes. Expressing this calculation using the formula, dot memory address = y XLSHWX 2 +
x/8 remainder rounded down = 7X4X2X4 = 60 Furthermore, if the dot memory 35 is outside the FP 38, the dot memory address will be the sum of LSAR (H/L). That is, the driver 1 to memory addresses are calculated using the following formula.

Dot memory address = y XLSHWX2+ x )
3+LSAR (HLE○PF built-in dot memory,
Set LSAR(H/L) to 0.

Next, as shown in FIG. 6(b), the content written to node memory addresses 1 to 60, that is, the bit address, becomes 00001000, which is xPJ! Standard data: x = 36. When expressed in binary, the lower 3 bits of 00100100 are decoded and output.

FIG. 3 explains the operation of the affine transformation/dot memory address calculation device in which the affine transformation block executes the normal affine transformation and the dot memory address calculation described above in the OFF state of FIG. 2. The data input from the font input FiFo consists of 16-bit integers, for example, negative numbers are two's complement numbers. Alternatively, the most significant bit may be used as a flag data recognition bit. Here, it is determined whether the data read from the font input FiFo is flag data or coordinate data, and if it is flag data, it is output as is to FiFo Q.

For coordinate data, check the read of the Xs y pair, perform affine transformation, and convert X+3” to FiFo O
Output to. At this time, the output data format is 1
It has a length of 6 bits and outputs the input integer data with 3 decimal bits attached.This is so that it can be expected to improve accuracy in subsequent processing blocks, such as the curve interpolation block. Also, if XHy' is the coordinate data of the first loop (starting point of the loop) of the outline font data, calculate the dot memory address,
Dot memory address, bit address to FiFoO
After that, x' and y' are output to FiFo O.

Also, in a system like the one shown in Figure 4, OFF
If the host CPU reads the affine-transformed result once, processes the data, such as line width correction, and then inputs it again to OFF and develops it into bitmap data, as shown in Figure 5. The behavior shown is as follows. The data read from the font input FiFo is a 16-bit real number including 3 decimal bits, the same as the output data format. Similarly here.

If the input data x, y is the coordinate data of the first loop (starting point of the loop) of outline font data,
Calculate the dot memory address, output the dot memory address and bit address to FiFoO, and then x'
, y to FiFo Q.

FIG. 1 shows an example of the configuration of an affine transformation/dot memory address calculation device for character generation according to the present invention.
1 is a control unit (CNT) that controls affine transformation and dot memory address calculation. 2x and 2y are coordinate registers (XR, YR) in which the coordinate data x and y read from the font input FiFo are stored. be. Reference numeral 3 denotes, for example, a 16-bit system data bus (CPU data bus), which is a bus through which the host CPU sets set values in each register. 4 and 5 are 32-bit data buses (A, B). 6a, 6b, 6c.

6d is, for example, a register (AMMA) that stores the mantissa part of coefficient data required for affine transformation.

, A Li M B , A M M C, iλMMD
) and 7a.

7b, 7c, and 7d are registers (AMCA, AMCB, AMCC) that store the exponent part of coefficient data.

AMCD). 8x and 8y are coordinate axis movement amount registers (AC5x, AC5Y) that store coordinate axis movement amount data.
). Reference numeral 9 denotes an output size register (LSHW) that stores the number of horizontal words, which is the output character size. 10 is a work memory source address register (LS) that stores the source address of the external output memory (dot memory).
It is AR (H/L). 11 and 12 are latches. 1
3 is a 16×16 multiplier (MULT), and 14 is a 32-bit barrel shifter. 15 and 16 are latches. I7 is an ALU. I8 is a register (BA) for outputting a bit address, and the lower three bits of the X coordinate are decoded by DC19 and output.

20 and 22 are coordinate registers (XRI, YRI) that store data x', y' after affine transformation;
, 23 are dot memory address calculation registers (XR
5I, YR8I). A decoder (DC) 24 decodes the value of the exponent part of the affine matrix register to decode the shift amount.

25 and 26 separate the upper and lower parts of the 32-bit data bus and output them as 16 bits. 27 is F
iFoO.

Next, the operation of the character generation affine transformation/dot memory address calculation device of the present invention will be explained.

The operation of affine transformation will be explained with reference to FIG. 1 in FIG. 7(a). The coordinate data X48 integer stored in the register XR is latched into the latch LAI via the A bus. Affine matrix mantissa data A49 stored in register AMMA is sent to latch LB via B bus.
It is latched to I.

Here, Δ represents the position of the decimal point. This is represented by the value of affine matrix exponent part data A (AMCA). The multiplier MULT outputs AX50, and the barrel shifter BS shifts the decimal point to the center of 32 bits, and then resets the latch LA2. Next, the coordinate data Y52 integer stored in the register YR is as follows.

It is latched into latch LAI via the A bus.

The affine matrix mantissa data B53 stored in the register A M M B is sent to the latch LBI via the B bus.
latched to. By54 is output by the multiplier MULT, and the decimal point is changed to 32 by the barrel shifter BS.
It is shifted to the center of the bit and latched into latch LB2. ALU outputs A x + B y, which is further latched into latch LB2 via B bus. AC3X57 stored in the coordinate axis movement amount register AC5X is latched to latch LA2 via the A bus. At this time, since AC5X is an integer,
The AC5X is placed in the upper 16 bits of the 32 bits, and the lower 16 bits are set to eight and zero. The ALU outputs A x + B y + AC X , that is, affine-transformed data X'. Furthermore, as 16-bit data 59 including 3 decimal bits, the FiFo
Output to O. The affine-transformed data Y'=Cx+Dy+AC5Y is similarly output. Each of the affine-transformed data 59 is XRI.

Stored in the YRI register. Regarding 16-bit data including 3 decimal bits that have been re-input, XRI, YRI
Stored in register.

The operation of dot memory address calculation will be explained with reference to FIG. 1 in FIG. 7(b). Because dot memory address calculations are performed using integers, during affine transformation, the decimal point was located at the center of the 32-hit data bus, whereas when calculating dot memory addresses, the decimal point was located at the rightmost end. Yes, all 32 bits constitute the integer part.

The dot memory address is yXLSHVl/-
Since it is determined by X 2 +x>3+LSAR(H/L), 2y is stored in the register YR5123.

This means that registers XRI and YRI contain decimal 3
This is because 16-bit data (affine-transformed data or re-input data) containing bits is stored, and the necessary integer parts are extracted from these data and further added. Register XR5121
contains X)3. Register YR5I 2
y60 is latched to launch ALL via A lotus. LSHW61 stored in register LSHW
is latched into the launch LBI via the B bus.

The multiplier MULT outputs (2yxt, SHw)6z, which passes through the barrel shifter without shifting and is latched into the latch LA2. (X>3)64 stored in register XR5l is sent to latch LB2 via B lotus.
latched to. By ALU (2yXLSHW+x>
3) 65 is outputted and further latched into latch LA2 via the A bus. The work memory source address L□5AR67 stored in the register LSAR is launched into the latch LB2 via the B bus. If the dot memory is the built-in memory of the OFP, LSAR is zero, so zero is latched into LB2. From ALU to dot memory address (2yXLSHWXx>3+L
SAR) 68 is output, divided into upper/lower 25,
Output to FiFoO.

The bit address is output from register BA1g.

As described above, affine transformation and dot memory address calculation can be executed at high speed and with high precision using one bar 1~ware, and the scale of the hardware can also be reduced.

〔Effect of the invention〕

According to the present invention, in a device that performs a series of processing for converting outline font data into heavy bitmap data on a page memory, highly accurate coordinate conversion can be executed with a small circuit scale, and a line for drawing the outline of a character can be used. The address calculation of the dot memory required at the time of occurrence can be realized without causing a series of processing speed reductions.

Furthermore, since the multipliers, adders, and data buses are minimized, the scale of the device can be reduced.

Furthermore, by fixing the decimal point position of the bus and providing a register for dot memory address calculation, high-speed affine transformation and dot memory address calculation can be realized.

By adding decimal bits to the output data of affine transformation, highly accurate interpolation can be achieved in curve interpolation and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an affine transformation/dot memory address calculation device for character generation according to an embodiment of the present invention, and FIG. 2 is a block diagram of a device that converts outline font data into bitmap data onto a page memory. , FIG. 3, and FIG. 5 are diagrams for explaining the operation modes, and FIG. 4 is a diagram for explaining the operation mode.
Figure 6 is a diagram showing an example of a system configuration using OFF.
FIG. 7 is a diagram for explaining dot memory address calculation. FIG. 7 is a diagram for explaining operations of affine transformation and dot memory address calculation. 1... Affine transformation/dot memory address calculation control unit, 2... Coordinate register, 4, 5... Data bus. 6.7... Affine matrix register, 13... Multiplier, 14... Barrel shifter, 17... ALU,
20.22...Coordinate register, 21.23...
Register for dot memory address calculation. → Car diagram 7 off-top input FiF0 IFo O 浴子 稟 5 Figure 7 on-t input FiF0 iFQ 稟 6 Figure (0-) Convulsive data to I to memory at L again (b) Do... Rinzu (,,4') (α) Affine change] husband (1:)) Dot memory address needle) Eaves

Claims (1)

[Claims] 1. In a device that performs a series of processing to convert coordinate data constituting outline font data into bitmap data onto a page memory, outline font coordinate data is temporarily stored from a host interface and a font memory. A font input FiFo means to keep,
An affine transformation block that sequentially reads coordinate data x, y from the font input FiFo means and performs affine transformation into coordinate data x', y', a FiFo0 that temporarily stores the affine transformed coordinate data, and a A curve interpolation block that reads coordinate data and performs curve interpolation for curve interpolation data, and a FiF that temporarily stores the coordinate data output from the curve interpolation block.
o1, a line generation block that reads coordinate data from the FiFo1 and generates a line between the coordinate data as a bit image, a dot memory that stores bitmap data output from the line generation block, and a bitmap from the dot memory. A character generator comprising a fill/BitBLT block and a page memory interface for reading data, filling the inside of an outline, and transferring a bitmap data block onto a page memory. 2. In the character generating device according to claim 1, coefficient data a, b, c, d are generated for input coordinate data x, y.
, and determine the coordinate axis movement amounts e and f, x'=ax+b
y+e and y'=cx+dy+f are calculated, and for the coordinate data x_o, y_o at the start of the loop that constitutes the outline font data, the line generation block calculates x_o', y_o' after affine transformation or no affine transformation. In this case, the affine transformation block calculates the dot memory address when expanding x_o, y_o onto the dot memory using one piece of hardware that performs affine transformation, and the calculated address data follows the same route as the coordinate data and flag data. An affine transformation/dot memory address calculation method for character generation characterized by transferring data to a line generation block. 3. In the calculation method according to claim 2, the affine-transformed output coordinate data or the input and output coordinate data that is not affine-transformed is composed of m bits for an integer part and n bits for a decimal part. Conversion/dot memory address calculation method. 4. In the calculation method according to claim 2 or 3, the internal data bus has an integer part j bits,
An affine transformation/dot memory address calculation method for character generation characterized in that the decimal part is divided into k bits, and the integer part (j+k) bits are calculated when calculating the dot memory address. 5. In the circuit block for affine transformation, a coordinate register that stores coordinate data x, y, a coefficient register that stores coefficient data required for affine transformation, and a coordinate axis movement amount register that stores coordinate axis movement amount data. , an output size register that stores the output character size, a work memory source address register that stores the source address of external output memory, and data x' after affine transformation.
, y', a dot memory address calculation register, and an arithmetic unit that performs affine transformation and dot memory address calculation. 6. The bit address, which is the bit information stored in the above dot memory address, is 1 bit, and the bit address in the dot memory address calculation is x, which is the output coordinate data of the start of the loop that constitutes the outline font data. 6. The affine transformation/dot memory address calculation device for character generation according to claim 5, wherein the lower S bits of the coordinate data x_o or x_o' are decoded and output.