JP2005310051A - Digital signal processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale of an instruction decoder while reducing the number of instruction codes. <P>SOLUTION: A mode information holding part holds first or second mode information. A bit length converting part outputs by lengthening or shortening a bit length of input data. When the bit length is lengthened and the first mode information is held in the mode information holding part, the input data is closed up to a low-order side of an output bit length, and a highest-order bit value or 0 is input on a high-order side of the surplus output bit length. On the other hand, when the second mode information is held, the input data is closed up to the high-order side of the output bit length, and 0 is input on the low-order side of the surplus output bit length. When the bit length is shortened and the first mode information is held in the mode information holding part, a bit by the output bit length is extracted from a lowest-order bit of the input data, and on the other hand, when the second mode information is held in the mode information holding part, a bit by the output bit length is extracted from a highest-order bit of the input data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital signal processing apparatus capable of processing both integer data and real number data by a fixed point method.

Integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) (when the ^first bit is a sign bit) and fixed-point real data (-1 ≤ x <1) There is a type of signal processing apparatus that can execute both of the operations (when the first bit is a sign bit). In this type of signal processing apparatus, when data is input to an arithmetic circuit (for example, a multiplier) or when data is output from the arithmetic circuit, the type of data to be calculated (integer data or real number data) is set. A corresponding process is required. This will be described in detail below.

  FIG. 31 shows a notation example of integer data and real number data by the fixed-point method.

As shown in FIG. 31, when representing integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) in binary, the integer data is represented by padding the lower bits with respect to the bit length. Is done. On the other hand, when expressing real number data (-1 ≦ x <1), the real number data is expressed by padding upper bits with respect to the bit length.

Therefore, when operations for integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) and real number data (−1 ≦ x <1) are realized in the same digital signal processing device, In the input / output unit of the arithmetic circuit, it is necessary to control whether input data or output data is padded with upper bits or lower bits according to the type of data (integer or real number). Further details are as follows.

  FIG. 32 shows a multiplier and its peripheral circuit in a conventional digital signal processing apparatus.

As shown in FIG. 32, for example, when the configuration of the multiplier 102 is 10 bits * 10 bits = 20 bits, consider a case where input data is input from an 8-bit register (a register, b register). In the operation of integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ), the input data from the a register is padded to the lower bit side in the upper pad / bottom pad circuit 101, and the free upper bit 2 The sign is input to the multiplier 102 after the sign bit of the input data is expanded. On the other hand, in the calculation of real number data (-1 ≦ x <1), the upper / lower pad circuit 101 stuffs the input data to the upper bit side and stuffs the lower two bits with “0” data before inputting it to the multiplier 102. To do. The instruction decoder 103 controls the top / bottom pad circuit 101 as described above according to the type of input data. When the data is input from the b register to the multiplier 102, the same control is required for the upper / lower pad circuit 104.

On the output side of the multiplier 102, in the operation of integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ), the output of the multiplier 102 is the result, but real data (-1 ≤ In the calculation of x <1), the output from the multiplier 102 is not a fixed point notation (see the lower part of FIG. 31). For this reason, in the top / bottom justification circuit 105 arranged on the output side of the multiplier 102, it is necessary to shift the output of the multiplier 102 to the upper side by 1 bit and add “0” to the lower bits. This is shown in FIG. Such processing control is also performed by the instruction decoder 103.

As described above, integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) and real number data (-1 ≤ x <1) are calculated in the same digital signal processor using the fixed-point method. In this case, control according to the type of data is required in the input / output unit of the arithmetic circuit (multiplier in the above example). For this reason, instructions for integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) and real data (-1 ≤ x <1) operations for various operation instructions It was necessary to provide a cord.

On the other hand, integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) and real data (-1 ≤ x <1) are also used for data transfer between registers via a dedicated bus or general-purpose bus. ) Transfer differs in handling. That is, depending on the type of transfer data, it is necessary to control whether the transfer source bits are padded with upper bits or lower bits with respect to the bit length of the transfer destination. This will be described in detail with reference to FIG.

  FIG. 34 is a diagram for explaining a method of transferring data from the Half Word register to the Word register.

As shown in FIG. 34, when the data in the transfer source register is integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ), the transfer source data is stored in the lower bits of the transfer destination register. The sign bit of the data is expanded to the upper bits (if the transfer source data is unsigned integer data, “0” data is added instead of the sign bit). On the other hand, when the data in the transfer source register is real number data (-1 ≦ x <1), the transfer source data is packed in the upper bits of the transfer destination register, and “0” data is added to the lower bits. . In this way, when transferring between registers, transfer data depends on whether it is integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) or real number data (-1 ≤ x <1). It is necessary to control whether bits are padded or lower bits are padded. Therefore, when transferring data between registers, instruction codes corresponding to integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) and real number data (-1 ≤ x <1) It is necessary to prepare.

As can be seen from the above, in the past, since it was necessary to prepare instruction codes for each of integer data and real number data, the number of instruction codes increased, and the number of instruction bits also increased. As a result, the circuit scale of the circuit has increased, which in turn has resulted in circuit complexity.
JP 09-171454 A

  An object of the present invention is to provide a digital signal processing apparatus that can reduce the number of instruction codes and reduce the circuit scale of an instruction decoder.

  A first digital signal processing apparatus of the present invention receives a mode information holding unit that holds first mode information or second mode information, and first data having a first bit length, and inputs the inputted first data. A bit length conversion unit that converts and outputs second data having a second bit length longer than the first bit length, and the mode information holding unit holds the first mode information, The input first data is packed to the lower side of the second bit length, and the most significant bit value of the first data is extended to the upper side of the remaining second bit length as the second data On the other hand, when the second mode information is held in the mode information holding unit, the first data is packed to the upper side of the second bit length, and the remaining second Insert zero at the lower bit length It includes a bit length transformation unit for performing a second mode process and outputting through as the second data.

  The second digital signal processing apparatus of the present invention receives the first mode information or the mode information holding unit holding the second mode information and the first data having the first bit length, and the inputted first data A bit length conversion unit that converts and outputs second data having a second bit length longer than the first bit length, and the mode information holding unit holds the first mode information, Performing the first mode process of filling the input first data to the lower side of the second bit length and outputting the second data with zero input to the upper side of the remaining second bit length as the second data; On the other hand, when the second mode information is held in the mode information holding unit, the first data is packed to the upper side of the second bit length, and zero is added to the lower side of the remaining second bit length. The input is the second data It includes a bit length transformation unit for performing a second mode process of and outputting, a.

  The third digital signal processing apparatus of the present invention receives the mode information holding unit holding the first mode information or the second mode information, and the first data having the first bit length, and inputs the input first data. A bit length conversion unit that converts and outputs second data having a second bit length shorter than the first bit length, and the mode information holding unit holds the first mode information, First mode processing is performed to extract the bit corresponding to the second bit length from the least significant bit of the input first data and output the second data as the second data, while the mode information holding unit performs the second mode. A bit length conversion unit for performing a second mode process for extracting the bit corresponding to the second bit length from the most significant bit of the first data and outputting it as the second data when the information is held; Prepare.

  According to the present invention, the number of instruction codes can be reduced and the circuit scale of the instruction decoder can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(1) First Embodiment FIG. 1 is a diagram showing a configuration of a digital signal processing device according to a first embodiment of the present invention.

This digital processing device performs arithmetic processing for integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) by a fixed point method according to the type of data stored in the dedicated register 10. Or determining whether to perform arithmetic processing for real number data (−1 ≦ x <1) by a fixed-point method. The digital processing apparatus will be described in detail below.

  As shown in FIG. 1, the dedicated register 10 has integer information or real number information for performing processing for integer data or real number data.

  The combinational circuit 11 outputs a control signal (A) corresponding to the data content in the dedicated register 10. For example, the combinational circuit 11 outputs a high level as the control signal (A) when integer information is stored in the dedicated register 10, while the control signal (A) when real number information is stored. Output low level. The combinational circuit 11 outputs a control signal (A) in synchronization with the clock from the instruction decoder (see FIG. 11).

  Input data a is input to an upper justification / bottom justification circuit 12 arranged on the input side of a multiplier (arithmetic unit) 15. The input data a is input from, for example, a register, memory, decoder or the like. When the bit length of the input data a is shorter than the bit length of the input of the multiplier 15, the top / bottom pad circuit 12 performs top pad / bottom pad processing (bit length conversion) according to the content of the control signal (A). Process).

  In other words, when the control signal (A) for instructing processing for integer data is input (when integer information is stored in the dedicated register 10), the upper pad / bottom pad circuit 12 is the multiplier 15; The input data a is packed on the lower bit side of the input bit length, and the sign bit of the input data is expanded on the vacant upper bit side. However, if the integer data is unsigned integer data, zero is input to the vacant upper bit side.

  On the other hand, when the control signal (A) instructing processing for real number data is input to the upper / lower circuit 12 (when real number information is stored in the dedicated register 10), the multiplier 15 The input data a is packed to the upper bit side of the input bit length of “1”, and “0” data is added to the empty lower bit side.

  In the above, the top / bottom filling process for the input data a has been described. However, the top / bottom filling process is similarly performed for the input data b by the top / bottom filling circuit 13. FIG. 2 shows the format of the input data to the top / bottom justification circuits 12 and 13 and the format of the output data from the top / bottom justification circuits 12 and 13 (input data of the multiplier 15).

  The top / bottom justification circuits 12 and 13 output the input data a and b as they are when the bit length of the input data a and b is the same as the input bit length of the multiplier 15.

  Returning to FIG. 1, the multiplier 15 performs a multiplication process using the output data of the upper / lower pad circuits 12 and 13 and outputs the multiplication result.

  The top / bottom pad circuit 14 arranged on the output side of the multiplier 15 performs processing for integer data or processing for real number data according to the content of the control signal (A) from the combinational circuit 11.

  More specifically, the top / bottom pad circuit 14 outputs the output of the multiplier 15 as it is when processing for integer data, while the output of the multiplier 15 is output when processing for real number data is performed. Shift one bit up and output "0" data added to the lower bits. This is shown in FIG. In the figure, MSB is the first (first) bit, and 2MSB is the second bit from the beginning. The output data is stored in a register or a memory, for example.

  What has been described so far will be described in more detail using specific examples.

  In FIG. 1, for example, it is assumed that input data a and input data b are 8-bit data, respectively, and the multiplier 15 calculates 16 bits × 16 bits = 32 bits.

In the above,
When calculating integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ): 100 × −50 = −5000, the input data a is 0110_0100b and the input data b is 1100_1110b. In advance, the dedicated register 10 stores integer information. At this time, the input / output of the multiplier 15 is
0000_0000_0110_0100 × 1111_1111_1100_1110 = 1111_1111_1111_1111_1110_1100_0111_1000
It becomes. Since the operation result is integer data, the output of the top / bottom pad circuit 14 is the output of the multiplier 15 as it is, that is,
1111_1111_1111_1111_1110_1100_0111_1000b.

On the other hand, when calculating real number data (−1 ≦ x <1): 0.5 × −0.25 = −0.125, the input data a is 0100_0000b and the input data b is 1110_0000b. The real number information is stored in the dedicated register 10 in advance. At this time, the input / output of the multiplier 15 is
0100_0000_0000_0000 × 1110_0000_0000_0000 = 1111_1000_0000_0000_0000_0000_0000_0000
It becomes. Since the operation result is real number data, the output of the upper pad / bottom pad circuit 14 is obtained by shifting the output of the multiplier 15 by 1 bit to the upper side and adding “0” data to the lower bit.
1111_0000_0000_0000_0000_0000_0000_0000b.

  In the above description, the first bit of the bit string of integer data and real number data is treated as a sign bit, but the present invention naturally includes a case where the first bit is not a sign bit. The same applies to the second to eighteenth embodiments described below.

  As described above, according to the present embodiment, whether to perform multiplication processing for integer data or multiplication processing for real number data is determined based on the data (integer information or real number information) in the dedicated register. Therefore, it is not necessary to include information relating to integer data and real number data in the instruction code relating to the multiplication instruction. That is, the same instruction can be used as a multiplication instruction for integer data and real data. As a result, the number of bits in the instruction set and the instruction decoder circuit can be reduced.

  Since the same multiplication instruction can be used for integer data and real number data in this way, when creating software in which integer data processing and real number data processing are mixed, the same code (subroutine, etc.) is used for each process. Can be used. That is, the code can be unified (shared). This will be described in more detail with reference to FIG.

  FIG. 30 is an example of a flowchart showing processing steps of software in which integer data processing and real number data processing are mixed.

  First, it is determined whether the type of data to be processed is integer data or real number data (step S1). If it is integer data, integer information is set in the dedicated register 10 (step S2), that is, a control signal ( A) is set for integer data processing. On the other hand, if it is real number data, real number information is set in the dedicated register 10 (step S3), that is, the control signal (A) is set for real number data processing. Thereafter, for example, a routine including a multiplication instruction is executed (step S4). This routine is the same for integer data processing and real number data processing. That is, conventionally, it was necessary to create a routine for integer data processing and a routine for real number data processing, respectively. On the other hand, in this embodiment, the processing for integer data and the processing for real number data can be switched by the data operation in the dedicated register, so that the routines for each processing can be shared. Therefore, the number of codes can be reduced as compared with the conventional case, and software in which both processes are mixed can be easily created.

(2) Second Embodiment FIG. 4 is a diagram showing a configuration of a digital signal processing device according to a second embodiment of the present invention.

In the first embodiment, whether processing for integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) or processing for real number data (−1 ≦ x <1) is performed. Is controlled by setting of the dedicated register 10, but in this embodiment, it is controlled by setting of the external terminal 16 of the chip as shown in FIG. That is, the combinational circuit 11 outputs a control signal (A) corresponding to the set potential of the external terminal 16. For example, when the external terminal 16 is set to the first reference potential, the combinational circuit 11 outputs a signal for integer data processing as the control signal (A) and is set to the second reference potential. In this case, a signal for real data processing is output as the control signal (A).

  In this way, as in the first embodiment, the same instruction code can be used for the multiplication instruction for integer data and the multiplication instruction for real number data. Therefore, the number of bits in the instruction set and the instruction decoder circuit can be reduced. I can do it.

(3) Third Embodiment FIG. 5 is a diagram showing a configuration of a digital signal processing device according to a third embodiment of the present invention.

  In the first and second embodiments described above, a multiplier is used as an arithmetic unit. However, in this embodiment, an adder / subtracter / logical arithmetic unit (hereinafter referred to as ALU) 17 is used. Hereinafter, this embodiment will be described in detail.

  As shown in FIG. 5, the combinational circuit 11 outputs a control signal (B) corresponding to the setting contents of the dedicated register 10.

  The top / bottom justification circuit 12 arranged on the input side of the ALU 17 controls the input data a when the bit length of the input data a is shorter than the input bit length of the adder / subtractor / logical operation unit (hereinafter referred to as ALU) 17. According to the content of the signal (B), the top / bottom filling process is performed.

That is, when the control signal (B) for instructing processing for integer data is input, the upper pad / bottom pad circuit 12 is configured so that the input data a is integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x < 2 ^(n-1) ), the input data is packed to the lower bit side, and the sign bit of the input data a is extended to the upper bit side. On the other hand, when the control signal (B) for instructing processing for real number data is input, that is, when the input data a is real number data (−1 ≦ x <1), the input data a is transferred to the upper bit side. "0" data is added to the lower bit side. Although the input data a has been described above, the same applies to the input data b. The relationship between the input data (input data a or input data b) and the input of the ALU 17 is shown in FIG.

  What has been described above will be described using a specific example.

  In FIG. 5, for example, it is assumed that input data a and input data b are 8-bit data, and each input / output of the ALU 17 is 16 bits.

In the above,
When calculating integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ): 10 + 30 = 40, the input data a is 0000_1010b and the input data b is 0001_1110b. Integer information is stored in advance in the dedicated register 10. At this time, the input / output of the ALU 17 is
0000_0000_0000_1010 + 0000_0000_0001_1110 = 000_000_0010_1000
It becomes. Therefore, the calculation result is 000_000_0010_1000b.

On the other hand, when calculating real number data (-1 ≦ x <1): 0.5 + 0.25 = 0.75, the input data a is 0100_0000b and the input data b is 0010_0000b. Real number information is stored in the dedicated register 10 in advance. At this time, the input / output of the ALU 17 is
0100_0000_0000_0000 + 0010_0000_0000_0000 = 0110_000_0000_0000
It becomes. Therefore, the calculation result is 0110_0000_0000_0000b.

  As described above, according to the present embodiment, it is determined whether to perform addition / subtraction / logical operation processing for integer data or addition / subtraction / logical operation processing for real data based on data in the dedicated register. Therefore, it is possible to set an instruction code relating to an addition / subtraction / logical operation instruction without involving information relating to integer data or real number data. That is, the same code can be used for integer data addition / subtraction / logical operation instructions and real number data addition / subtraction / logical operation instructions. Therefore, it is possible to reduce the number of bits in the instruction set and the instruction decoder circuit. When integer data processing and real number data processing are mixed in software, a code portion (such as a routine) including addition / subtraction / logical operation instructions can be shared in each processing. As a result, the number of codes can be reduced, and software in which both processes are mixed can be easily created.

(4) Fourth Embodiment FIG. 7 is a block diagram showing a configuration of a digital signal processing apparatus according to a fourth embodiment of the present invention.

In the third embodiment, whether processing for integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) or real number data (-1 ≤ x <1) is performed. However, in this embodiment, it is controlled by setting the external terminal 16 as shown in FIG.

  As in the third embodiment, the same instruction code can be used for addition / subtraction / logical operation of integer data and addition / subtraction / logical operation of real number data as in the third embodiment. Circuits can be reduced.

(5) Fifth Embodiment FIG. 8 is a block diagram showing a configuration of a digital signal processing device according to a fifth embodiment of the present invention.

  In the present embodiment, data transfer between registers via a dedicated bus or a general-purpose bus will be described. However, the bit length of the transfer source and the transfer destination is different, more specifically, the bit length of the transfer source is shorter than the bit length of the transfer destination, and the bit length of the transfer destination register and the bit length of the bus connected to this register Are the same.

  As shown in FIG. 8, the combinational circuit 11 outputs a control signal (C) corresponding to the setting contents of the dedicated register 10.

  When the control signal (C) instructing processing for integer data is input, the upper / lower circuit 21 converts the transfer source data in the transfer source register (register a0 or a1 or a2) to the transfer destination bit. It is packed on the lower side with respect to the length, and the sign bit is expanded on the upper side and output to the bus.

  On the other hand, when the control signal (C) for instructing processing for real number data is input, the upper pad / bottom pad circuit 21 packs the transfer source data on the upper side with respect to the bit length of the transfer destination, "0" data is added to and output to the bus.

  The transfer destination register (register X0 or register Y0) inputs the data from the bus as it is. Thereby, transfer between registers is performed.

  FIG. 9 shows data in the transfer source register described above, data on the bus, and transfer destination register data, respectively.

  In the present embodiment described above, the data transfer source and the transfer destination are used as registers, respectively, but one or both of them may be used as a memory area. Also in other embodiments described below, a memory area may be used instead of a register as a part for storing data.

  As described above, according to the present embodiment, it is determined whether to perform transfer processing for integer data or transfer processing for real number data based on the setting contents of the dedicated register. It is not necessary to include information on real number data and integer data in the instruction code. That is, the same instruction code can be used for the real data transfer instruction and the integer data transfer instruction. Thereby, it is possible to reduce the number of bits of the instruction set and the instruction decoder circuit. When integer data processing and real number data processing are mixed in software, a code (routine or the like) including a transfer instruction can be shared by each processing. . Thereby, the number of codes can be reduced, and software in which both processes are mixed can be easily created.

(6) Sixth Embodiment FIG. 10 is a block diagram showing a configuration of a digital signal processing device according to a sixth embodiment of the present invention.

In the fifth embodiment, whether processing for integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) or real number data (-1 ≤ x <1) is performed. Is controlled by setting the dedicated register 10, but in this embodiment, it is controlled by setting the external terminal 16, as shown in FIG.

  As with the fifth embodiment, this also allows the same data code for real data and integer data to be used as the instruction code related to data transfer, thereby reducing the number of bits in the instruction set and the instruction decoder circuit. I can plan.

(7) Seventh Embodiment FIG. 11 is a diagram showing a configuration of a digital signal processing device according to a seventh embodiment of the present invention.

  In the fifth embodiment, the case where the bit length of the transfer source is shorter than the bit length of the transfer destination in the data transfer between the registers has been described. However, in this embodiment, the bit length of the transfer source is the bit of the transfer destination. A case where the length is longer than the length will be described.

  As shown in FIG. 11, the combinational circuit 11 outputs a control signal (D) corresponding to the setting of the dedicated register 10.

When the control signal (D) instructing processing for integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) is input, the upper / lower selection circuit 22 receives the transfer source data. Bit data corresponding to the transfer destination bit length is extracted from the least significant bit and input to the transfer destination register X0. Data input to the transfer destination register X0 is performed in synchronization with an instruction (clock) from the instruction decoder 23 shown in the figure. On the other hand, when the control signal (D) for instructing processing for integer data (-1 ≦ x <1) is input, the upper / lower selection circuit 22 starts from the most significant bit of the transfer source data to the transfer destination bit length. Extract the minute bit and input it to the transfer destination register. FIG. 12 shows the relationship between the data in the transfer source register and the data in the transfer destination register.

More specifically, the example of FIG. 11 shows data transfer between registers when the bit length of the bus and the bit length of the transfer source register a0 are 32 bits, respectively, and the bit length of the transfer destination register X0 is 16 bits. When outputting the 32-bit data in the transfer source register a0 to the bus, the 32-bit data is output as it is. On the other hand, when data is input from the bus to the transfer destination 16-bit register X0, selection processing by the upper / lower selection circuit 22 is performed. That is, when the transfer data is integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ), the upper / lower selection circuit 22 extracts and transfers the lower 16 bits of the data on the bus. Input to the destination register X0. On the other hand, when the transfer data is real number data (-1 ≦ x <1), the upper / lower selection circuit 22 extracts the upper 16 bits of the data on the bus and inputs the extracted data to the transfer destination register X0.

  As described above, according to the present embodiment, whether to perform transfer processing for integer data or transfer processing for real number data is determined based on the setting contents (integer information or real number information) of the dedicated register. Therefore, it is not necessary to include information on the type of data in the instruction code. Further, unlike the prior art, it is not necessary for the software to divide the data in the transfer source register for each bit length of the transfer destination register and assign an address to each divided data. As a result, the instruction code can be reduced, the number of bits in the instruction set can be reduced, and the instruction decoder circuit can be simplified. In addition, even when integer data processing and real number data processing are mixed in the software, the codes for each processing including data transfer processing can be unified, so that the number of codes can be reduced, thereby mixing both processing. Software can be created easily.

(8) Eighth Embodiment FIG. 13 is a diagram showing a configuration of a digital signal processing device according to an eighth embodiment of the present invention.

In the seventh embodiment, whether processing for integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) or real number data (-1 ≤ x <1) is performed. However, in this embodiment, it is controlled by setting the external terminal 16, as shown in FIG.

  This also makes it possible to reduce the instruction code, reduce the number of bits in the instruction set, and simplify the instruction decoder circuit, as in the seventh embodiment.

(9) Ninth Embodiment FIG. 14 is a diagram showing a configuration of a digital signal processing device according to a ninth embodiment of the present invention.

  In the present embodiment, data transfer between registers in a digital signal processing apparatus in which a register dedicated to storing integer data and a register capable of handling both integer data and real number data are mixed will be described.

  As illustrated in FIG. 14, the instruction decoder 24 outputs a register selection signal (Regster_sel) that specifies a transfer source register when executing an inter-register transfer instruction. The transfer source register (for example, the register 28 or 29) indicated by the register selection signal outputs the internal data to the upper / lower pad circuit 25. The register 28 is a register that exclusively stores integer data, and the register 29 is a register that can handle both integer data and real number data.

  The detection circuit 27 outputs an integer signal (Int_signal) to the combinational circuit 26 when the register selection signal is input from the instruction decoder 24 and the register selection signal indicates the register 28 dedicated to integer data. When an integer signal is input, the combinational circuit 26 outputs a control signal (E) for instructing processing for integer data to the upper / lower pad circuit 25 regardless of the setting contents of the dedicated register 10. In other words, when the combinational circuit 26 receives an integer signal, even if real number information is stored in the dedicated register 10, the combinational circuit 26 supplies the control signal (E) for instructing the processing for integer data to the upper / lower padded circuit. To 25. The top / bottom pad circuit 25 performs top pad / bottom pad processing on the transfer source data input from the register 28 or register 29 and inputs it to the transfer destination register X0 or register Y0. Note that the data fetching into the transfer destination registers X0 and Y0 is performed in synchronization with the clocks Clock_x0 and Clock_y0 from the instruction decoder 24, as shown in FIG.

  As described above, according to the present embodiment, when the transfer source register is a register dedicated to integer data, transfer processing for integer data is performed regardless of the setting contents of the dedicated register. There is no need to provide a code dedicated to the integer register as an instruction code for inter-transfer. Thereby, the number of bits of the instruction set can be reduced and the instruction decoder circuit can be simplified.

  Also, when it is necessary to handle registers dedicated to integer data in the middle of the processing flow of real number data in software, switching of the processing flow before and after handling the register dedicated to integer data (real data processing → integer Data processing, integer data processing → real number data processing) can be omitted, thereby reducing the burden of software creation and the number of steps.

(10) Tenth Embodiment FIG. 15 is a diagram showing a configuration of a digital signal processing device according to a tenth embodiment of the present invention.

In the ninth embodiment, processing for integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) or real number data (-1 ≤ x <1) is performed. Is controlled by setting the dedicated register 10, but in this embodiment, it is controlled by setting the external terminal 16 as shown in FIG.

  This also makes it possible to reduce the number of bits in the instruction set and simplify the instruction decoder circuit, as in the ninth embodiment. In addition, even if it is necessary for software to handle registers dedicated to integer data in the middle of the processing flow of real number data, switching of the processing flow can be omitted, and the burden of creating software and the number of steps can be reduced. I can do it.

(11) Eleventh Embodiment FIG. 16 is a diagram showing a configuration of a digital signal processing device according to an eleventh embodiment of the present invention.

  In the present embodiment, data transfer between registers in a digital signal processing apparatus in which a register 31 dedicated to storing real number data and a register 32 capable of handling both integer data and real number data are mixed will be described.

  As shown in FIG. 16, the instruction decoder 24 outputs a register selection signal (Regster_sel) for specifying a transfer source register when executing an inter-register transfer instruction. When the register selection signal indicates the register 31 dedicated to real number data, the detection unit 30 outputs a real number signal (Fixed__signal) to the combinational circuit 33. When a real number signal is input, the combinational circuit 33 outputs a control signal (F) for instructing processing for real number data to the top / bottom justification circuit 25 regardless of the setting contents of the dedicated register 10. That is, when the combinational circuit 33 receives a real number signal, even if integer information is stored in the dedicated register 10, the combinational circuit 33 supplies a control signal (F) for instructing processing for real number data to an upper / lower order circuit. To 25.

  As described above, according to the present embodiment, when the transfer source register is a register dedicated to real number data, the transfer process for real number data is performed regardless of the setting contents of the dedicated register. It is not necessary to provide a code dedicated to the real number register as an inter-transfer instruction code. Thereby, the number of bits of the instruction set can be reduced and the instruction decoder circuit can be simplified.

  In addition, when it is necessary to handle registers dedicated to real data in the middle of the processing flow of integer data in software, the processing flow is switched before and after the register dedicated to real data (integer data processing → real number). Data processing, real number data processing → integer data processing) can be omitted, thereby reducing the burden of software creation and the number of steps.

(12) Twelfth Embodiment FIG. 17 is a diagram showing a configuration of a digital signal processing device according to a twelfth embodiment of the present invention.

In the eleventh embodiment, processing for integer data (-2 ^(n-1) ≤x <2 ^(n-1) ) or real number data (-1≤x <1) is performed. Is controlled by setting the dedicated register 10, but in this embodiment, it is controlled by setting the external terminal 16 as shown in FIG.

  This also makes it possible to reduce the number of bits in the instruction set and simplify the instruction decoder circuit as in the tenth embodiment. In software, even if it is necessary to handle registers dedicated to real data in the middle of the integer data processing flow, switching of the processing flow can be omitted, and the burden of creating software and the number of steps can be reduced. .

(13) Thirteenth Embodiment FIG. 18 is a diagram showing a configuration of a digital signal processing device according to a thirteenth embodiment of the present invention.

  In this embodiment, a case will be described in which an operation result is transferred to a register at the same time as an ALU operation. Hereinafter, this embodiment will be described in detail.

  As shown in FIG. 18, the combinational circuit 11 outputs a control signal (G) corresponding to the setting content of the dedicated register 10 to the upper / lower justification circuits 12 and 13 and the upper / lower selection circuit 22.

When the control signal (G) for instructing processing for integer data is input, the top / bottom pad circuit 12 means that the input data a is integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ^{(n -1) In} the case of), the input data is packed to the lower bit side, and the sign bit of the input data is extended to the upper bit side. On the other hand, when a control signal (G) for instructing processing for real number data is input, that is, when the input data a is real number data (−1 ≦ x <1), the input data is sent to the upper bit side. "0" data is added to the padded lower bit side. This is shown in FIG. The top / bottom pad circuit 12 has been described above, but the same applies to the top / bottom pad circuit 13.

  The ALU 35 performs arithmetic processing using the output data of the top / bottom pad circuits 12 and 13.

  The upper / lower selection circuit 22 transfers the output result of the ALU 35 to the register (register X or Y) via the bus. More specifically, when a control signal (G) instructing processing for integer data is input, the upper / lower selection circuit 22 extracts data corresponding to the bit length of the transfer destination register from the least significant bit of the output result. And transfer. On the other hand, when the control signal (G) for instructing processing for real number data is input, the upper / lower selection circuit 22 extracts data corresponding to the bit length of the transfer destination register from the most significant bit of the output result. Forward. FIG. 20 shows the relationship between input data (input data a or input data b) and data in the transfer destination register (register X or Y).

  What has been described above will be described using a specific example.

  In FIG. 18, for example, it is assumed that input data a and input data b are each 16-bit data, each input / output of ALU 35 is 32 bits, and transfer destination registers X and Y are each 16 bits.

In the above,
When calculating integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ): 10 + 30 = 40
Input data a: 000Ah, input data b: 001Eh. Integer information is stored in advance in the dedicated register 10. At this time, the input / output of the ALU 35 is
0000_000Ah + 0000_001Eh = 0000_0028h
It becomes. That is, the output result of the ALU 35 is 0000_0028h. Simultaneously with this calculation, the upper / lower selection circuit 22 transfers the calculation result. That is, data transfer to the register X or the register Y is performed. Since the upper / lower selection circuit 22 performs processing for integer data, the transfer result is 0028h.

On the other hand, when calculating real number data (−1 ≦ x <1): 0.5 + 0.125 = 0.625, the input data a is 4000h and the input data b is 1000h. Real number information is stored in the dedicated register 10 in advance. At this time, the input / output of the ALU 35 is
4000_0000h + 1000_0000h = 5000_0000h
It becomes. That is, the output result of the ALU 35 is 5000_0000h. Simultaneously with this calculation, the upper / lower selection circuit 22 transfers the calculation result. That is, data transfer to the register X or the register Y is performed. Since the upper / lower selection circuit 22 performs processing for real number data, the transfer result is 5000h.

  As described above, according to the present embodiment, any of integer data arithmetic processing and arithmetic result transfer processing, real data arithmetic processing and arithmetic result transfer processing is performed based on the setting contents of the dedicated register. Since it is determined whether to execute, the ALU instruction code can be set without including information on the data type. Thereby, it is possible to reduce the setting of the instruction code, the number of bits of the instruction set, and the instruction decoder circuit. In addition, when creating software in which integer data processing and real number data processing are mixed, codes for each processing including calculation processing and calculation result transfer processing can be unified, and therefore the number of codes can be reduced. Software in which integer data processing and real data processing are mixed can be easily created.

(14) Fourteenth Embodiment FIG. 21 is a diagram showing a configuration of a digital signal processing device according to a fourteenth embodiment of the present invention.

In the thirteenth embodiment, processing for integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) or processing for real number data (−1 ≦ x <1) is performed. This is controlled by setting the dedicated register 10, but in this embodiment, it is controlled by setting the external terminal 16, as shown in FIG.

  As in the thirteenth embodiment, this also makes it possible to reduce instruction code settings, reduce the number of bits in the instruction set, and reduce the instruction decoder circuit, reduce the number of codes, and process integer data. And real number data processing can be easily created.

(15) Fifteenth Embodiment FIG. 22 is a diagram showing a configuration of a digital signal processing device according to a fifteenth embodiment of the present invention.

  In this embodiment, a case will be described in which arithmetic processing by an ALU and transfer processing between registers are executed simultaneously. Hereinafter, this embodiment will be described in detail.

  As shown in FIG. 22, the combinational circuit 11 outputs a control signal (H) corresponding to the setting contents of the dedicated register 10 to the upper / lower-order circuits 12 and 13 and the upper / lower-order selection circuit 22.

When the control signal (H) for instructing processing for integer data is input, the top / bottom pad circuit 12 indicates that the input data a is integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ^{(n -1) In} the case of), the input data is packed to the lower bit side, and the sign bit of the input data is extended to the upper bit side. On the other hand, when the control signal (H) instructing processing for real number data is input to the upper / lower pad circuit 12, that is, when the input data a is real number data (-1 ≦ x <1). The input data is packed to the upper bit side and “0” data is added to the lower bit side. The top / bottom pad circuit 12 has been described above, but the same applies to the top / bottom pad circuit 13. The relationship between the input data (input data a or input data b) and the input of the ALU 35 is shown in FIG.

  The ALU 35 performs arithmetic processing using the output data from the top / bottom pad circuits 12 and 13. The calculation result of the ALU 35 is written to the register Acc. Simultaneously with the writing to the register Acc, the data in the register Acc is transferred to the register X or the register Y via the bus. This is shown in FIG. In this transfer, when the control signal (H) instructing processing for integer data is input, the upper / lower selection circuit 22 receives data corresponding to the bit length of the transfer destination register from the least significant bit of the transfer source data. Extract and output to the transfer destination. On the other hand, when the control signal (H) instructing processing for real number data is input, the upper / lower selection circuit 22 extracts data corresponding to the bit length of the transfer destination register from the most significant bit of the transfer source data. To the destination. This is shown in FIG.

  What has been described above will be described using a specific example.

  In FIG. 22, for example, it is assumed that input data a and input data b are 16-bit data, and each input / output of the ALU 35 is 32 bits. Further, it is assumed that 1234_5678h has already been input to the register Acc, and the registers X and Y each have 16 bits.

In the above,
When calculating integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ): 200 + 60 = 260,
Input data a: 00C8h, input data b: 003Ch. Integer information is set in the dedicated register 10 in advance. At this time, the input / output of the ALU 35 is
0000_00C8h + 0000_003Ch = 0000_0104h
It becomes. That is, the output result of the ALU 35 is 0000_0104h, which is written to the register Acc. At the same time, transfer from the register Acc to, for example, the register X is also executed. Since the upper / lower selection circuit 22 performs processing for integer data, the lower 16 bits 5678h in the register Acc are transferred to the register X.

On the other hand, when real number data (-1 ≦ x <1) is calculated: 0.25 + 0.125 = 0.375, the input data a is 2000h and the input data b is 1000h. Real number information is stored in the dedicated register 10 in advance. At this time, the input / output of the ALU 35 is
2000_0000h + 1000_0000h = 3000_0000h
It becomes. That is, the output result of the ALU 35 is 3000_0000h, which is written into the register Acc. At the same time, transfer from the register Acc to, for example, the register Y is also executed. Since the upper / lower selection circuit 22 performs processing for real number data, the upper 16 bits 1234h in the register Acc are transferred to the register Y.

  As described above, according to the present embodiment, any one of arithmetic processing for integer data and inter-register transfer processing, arithmetic processing for real number data, and inter-register transfer processing is executed based on the setting contents of the dedicated register. Therefore, the instruction code for the ALU instruction and the transfer instruction can be set without including information on the data type. Thereby, it is possible to reduce the setting of the instruction code, the number of bits of the instruction set, and the instruction decoder circuit. In addition, when creating software in which integer data processing and real number data processing are mixed, codes for each processing including arithmetic processing and transfer processing between registers can be unified, so that the number of codes can be reduced, and integer data Software in which processing and real number data processing are mixed can be easily created.

(16) Sixteenth Embodiment FIG. 26 is a diagram showing a configuration of a digital signal processing device according to a sixteenth embodiment of the present invention.

In the fifteenth embodiment, processing for integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) or processing for real number data (−1 ≦ x <1) is performed. This is controlled by setting the dedicated register 10, but in the present embodiment, it is controlled by setting the external terminal 16, as shown in FIG.

  As in the fifteenth embodiment, this also makes it possible to reduce the setting of the instruction code, thereby reducing the number of bits in the instruction set and the instruction decoder circuit, and reducing the total number of codes, so that the integer data It is also possible to easily create software in which the above processing and real number data processing are mixed.

(17) Seventeenth Embodiment FIG. 27 is a diagram showing a configuration of a digital signal processing device according to a seventeenth embodiment of the present invention.

  In this embodiment, a case will be described in which data is input to a register by a so-called immediate instruction (data is directly input by an instruction code). Hereinafter, this embodiment will be described in detail.

  As shown in FIG. 27, when executing the immediate instruction, the instruction decoder 23 outputs the input data to the register 43 to the upper / lower pad circuit 42 via the bus. For example, when the instruction decoder 23 executes an instruction code (immediate instruction) having the lower 10 bits as input data and the upper 10 bits as a data input instruction to a 16-bit register, 10 bits as input data are padded up / down. It outputs to the filling circuit 42.

  The combinational circuit 11 outputs a control signal (I) corresponding to the setting contents of the dedicated register 10 to the upper / lower pad circuit 42.

  The upper padding / bottom padding circuit 42 performs top padding / bottom padding processing on the input data according to the content of the control signal (I).

That is, when the control signal (I) instructing the processing for integer data (−2 ⁽ⁿ⁻¹⁾ ≦ x <2 ⁽ⁿ⁻¹⁾ ) is input, the upper / lower circuit 42 receives an instruction. The input data from the decoder 23 is packed to the lower bit side, and the sign bit of the input data is extended to the register 43 to the upper bit side. On the other hand, when the control signal (I) instructing processing for real number data (−1 ≦ x <1) is input, the upper / lower pad circuit 42 converts the input data from the instruction decoder 23 to the upper bit side. The lower bit side is added with “0” data to the register 43. FIG. 28 shows input data from the instruction decoder 23 and input data actually stored in the register 43.

  As described above, according to the present embodiment, it is determined whether to perform immediate data processing for integer data or real data for real data based on the setting contents in the dedicated register 10, so that real data and integer data The same immediate command can be used for data. That is, there is no need to provide different immediate instructions for real data and integer data. As a result, the number of bits in the instruction set and the instruction decoder circuit can be reduced. In addition, when creating software in which integer data processing and real number data processing are mixed, the codes for each process including immediate value processing can be unified, so that the overall code can be reduced, and integer data processing and real numbers can be reduced. Software that mixes data processing can be easily created.

(18) Eighteenth Embodiment FIG. 29 is a diagram showing a configuration of a digital signal processing device according to an eighteenth embodiment of the present invention.

In the seventeenth embodiment, processing for integer data (-2 ^(n-1) ≤ x <2 ^(n-1) ) or real number data (-1 ≤ x <1) is performed. However, in this embodiment, it is controlled by setting the external terminal 16 as shown in FIG.

  As in the seventeenth embodiment, this also makes it possible to reduce the setting of the instruction code, thereby reducing the number of bits in the instruction set and the instruction decoder circuit, reducing the total code, Software in which processing and real number data processing are mixed can be easily created.

It is a figure which shows the structure of the digital signal processing apparatus according to the 1st Embodiment of this invention. In the first embodiment, the formats of the input data to the top / bottom justification circuit and the output data from the top / bottom justification circuit are shown. It is a figure explaining the process performed on the output side of a multiplier in the said 1st Embodiment. It is a figure which shows the structure of the digital signal processing apparatus according to the 2nd Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 3rd Embodiment of this invention. In the said 3rd Embodiment, it is a figure explaining the upper pad / bottom pad process with respect to input data. It is a block diagram which shows the structure of the digital signal processing apparatus according to the 4th Embodiment of this invention. It is a block diagram which shows the structure of the digital signal processing apparatus according to the 5th Embodiment of this invention. In the fifth embodiment, data in the transfer source register, data on the bus, and transfer destination register data are shown. It is a block diagram which shows the structure of the digital signal processing apparatus according to the 6th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 7th Embodiment of this invention. In the said 7th Embodiment, it is a figure explaining the selection process with respect to transfer source data. It is a figure which shows the structure of the digital signal processing apparatus according to the 8th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 9th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 10th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 11th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 12th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 13th Embodiment of this invention. In the 13th Embodiment, it is a figure explaining the upper padding / bottom padding process with respect to input data. In the 13th Embodiment, it is a figure explaining the selection process with respect to the output data of ALU. It is a figure which shows the structure of the digital signal processing apparatus according to the 14th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 15th Embodiment of this invention. In the 15th Embodiment, it is a figure explaining the upper padding / bottom padding process with respect to input data. In the fifteenth embodiment, a state in which operation result writing by the ALU and inter-register transfer are simultaneously performed is shown. In the 15th Embodiment, it is a figure explaining the selection process with respect to the output data of ALU. It is a figure which shows the structure of the digital signal processing apparatus according to the 16th Embodiment of this invention. It is a figure which shows the structure of the digital signal processing apparatus according to the 17th Embodiment of this invention. In the 17th embodiment, it is a figure explaining how the input data from the instruction decoder is stored in the register. It is a figure which shows the structure of the digital signal processing apparatus according to the 18th Embodiment of this invention. It is an example of the flowchart which shows the process step of the software with which the process of integer data and the process of real number data were mixed. An example of notation of integer data and real number data in the fixed point system is shown below. 1 shows a multiplier and its peripheral circuits in a conventional digital signal processing apparatus. It is a figure explaining the process in the output side of a multiplier. It is a figure explaining the method of transferring data from a Half Word register to a Word register.

Explanation of symbols

10 dedicated register 11, 26, 33 combinational circuit 12, 13, 14, 21, 25, 42 top / bottom pad circuit 15 multiplier 16 external terminal 17, 35 ALU
22 Upper / Lower Selection Circuits 23, 24 Instruction Decoders 27, 30 Detection Circuit 28 Integer Data Dedicated Register 31 Real Number Data Dedicated Register

Claims (5)

A mode information holding unit holding the first mode information or the second mode information;
A bit length conversion unit that receives first data having a first bit length, converts the input first data into second data having a second bit length that is longer than the first bit length, and outputs the second data. ,
When the first mode information is held in the mode information holding unit, the input first data is packed to the lower side of the second bit length, and the upper side of the remaining second bit length is Performing a first mode process of outputting an extension of the most significant bit value of the first data as the second data;
On the other hand, when the second mode information is held in the mode information holding unit, the first data is packed to the upper side of the second bit length, and zero is added to the lower side of the remaining second bit length. A bit length conversion unit for performing a second mode process for outputting the input as the second data;
A digital signal processing apparatus. A mode information holding unit holding the first mode information or the second mode information;
A bit length conversion unit that receives first data having a first bit length, converts the input first data into second data having a second bit length that is longer than the first bit length, and outputs the second data. ,
When the first mode information is held in the mode information holding unit, the input first data is packed to the lower side of the second bit length, and the upper side of the remaining second bit length is zero. Performing a first mode process for outputting the input as the second data,
On the other hand, when the second mode information is held in the mode information holding unit, the first data is packed to the upper side of the second bit length, and zero is added to the lower side of the remaining second bit length. A bit length conversion unit for performing a second mode process for outputting the input as the second data;
A digital signal processing apparatus. A mode information holding unit holding the first mode information or the second mode information;
A bit length conversion unit that receives first data having a first bit length, converts the input first data into second data having a second bit length shorter than the first bit length, and outputs the second data. ,
When the first mode information is held in the mode information holding unit, the bits corresponding to the second bit length are extracted from the least significant bits of the input first data and output as the second data Perform the first mode processing,
On the other hand, when the second mode information is held in the mode information holding unit, the second bit length is extracted from the most significant bit of the first data and is output as the second data. A bit length conversion unit for performing two-mode processing;
A digital signal processing apparatus. A plurality of the bit length conversion units;
4. The digital signal processing apparatus according to claim 1, further comprising an arithmetic unit that performs arithmetic processing using the second data output from each of the bit length conversion units.   When the bit length conversion unit receives a signal indicating that the transmission source of the first data is a first mode dedicated register or a second mode dedicated register, the bit length conversion unit stores the information stored in the mode information holding unit. 5. The digital signal processing apparatus according to claim 1, wherein the first mode process or the second mode process is executed regardless of contents. 6.

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