JPS62165280A - Setup apparatus for graphic/vector generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION This invention relates to graphic display systems, and more particularly to techniques for setting up vector generators used in such systems.

B. Prior Art IBM Systems Journal published in 1965
Vol. 4, pages 25 to 30 of Nα1, J. E. Presentham (J, E, Br.
esenham)'s paper "Algorithm for computer control of digital plotter" (AI4orithm fo
rComputer Control of Digi
tal Plotter), and ``Fundamentals of Graphics'' by J. T. Fotey and others published in 1982.
mentals ofInteractive Com
pntcr Graphics) 433rd to 436th
In the case of the truly disclosed Beresenham vector generation technique, multiple computational processes are required before starting line generation. It is called.

PROBLEM SOLVED BY THE C0 INVENTION Conventional backup generator setups typically require 4 or 5 clock cycles. The present invention aims to further reduce the operating time for this setup.

Means for Solving Problem D6 The present invention provides a means for determining a difference function value regarding an X coordinate displacement value and a Y coordinate displacement value for a vector to be drawn, and a difference function value and A storage means for storing the code, and a value based on the X coordinate displacement value and a Y value based on the code stored in the storage means.
It is characterized by providing means for exchanging values based on coordinate displacement values, and means for holding information for controlling the number of repetitions of vector generation.

E. EXAMPLE FIG. 2 shows a graphics display system. The system includes a system control processor 1, a host communication interface 2, a display processor 3, a vector generator (hardware rasterizer) 4, a monitor 5, a video pixel memory 6, and a system memory 7. These components may be those used in conventional display systems commercially available. However, vector generator 4 includes a configuration according to the present invention.

The system control processor 1 is a general-purpose processor that performs central control of the system, and provides services for all connected graphic I10 devices. System control processor 1 also coordinates processing operations associated with display processor 3 and communicates with the host via host communication interface 2 . This interface 2 is a serial interface.

The display processor 3 has the role of executing the graphic instructions of the display storage program residing in the system memory 7, and is primarily responsible for generating images to be displayed on the monitor 5. To be specific.

The functions of the display processor 3 include (a) decoding and executing graphic commands and non-graphic commands such as bookkeeping and control;
(b) Performing transformation and clipping operations on basic figures such as lines, characters, polygons, etc.; (d) Preprocessing data and supplying it to the vector generator 4 and video pixel memory 6 to form lines, characters, polygons, and signs; Including preparation for display of etc.

The vector generator 4 is hardware that implements the Presentation Ham line generation algorithm, receives the start and end points of a vector (line) as input, generates an output representing a pixel to be displayed, and supplies the generated output to the video pixel memory 6 .

The video pixel memory 6 consists of 8 planes each having 6 bits of IKXIK bits, making it possible to display 256 colors simultaneously via a color lookup table. Based on the image data stored in this memory, the monitor 5
The image is displayed.

The present invention provides a technique for efficiently setting up the vector generator 4, and from now on, FIGS.
This will be explained in detail with reference to the figures.

In FIG. 1, the center of the BACK1HEL generator 4 is an arithmetic logic unit (ALU) 110t'. ALUIIO is input bus 1 from multiplexer (MPX) 112 and 114.
06 and 108 and an output bus 116. Also, ALU
A sign bit line 120 is connected to the N output terminal of IIO. Line 120 becomes active when the calculated result (SUM) is less than zero.

ΔX and ΔY representing the X and Y coordinate displacement values for the vector are the inputs of the vector generator 4 and are provided via the bus 102 to the multiplexer (MPX) 122. Initially, 1MPX 122 passes data on bus 102 to absolute value logic circuit 124 under control of the display processor's sequence control circuit (not shown). Absolute value logic circuit 1
24 are ΔX and ΔY given sequentially via the bus 102
Find the absolute value of. The output bus of MPX 122 includes a code bit line 123 leading to an X code flip-flop (FF) 126 and a Y code flip-flop (FF) 128. These FFs 126 and 128 are operated at appropriate times under the control of the sequence control circuit. The output of absolute value logic circuit 124 is provided via bus 130 to delta-X register 132, delta-X register 134, and MPX 112. However, the absolute value of ΔX is loaded into register 132, and the absolute value of ΔY is loaded into register 13.
4 is loaded.

The ΔX output from register 132 is provided via bus 136 to multiplexer (MPX) 140 and hardwired multiplier 142. The ΔY output from register 134 is provided to MPX 140 and hardwired multiplier 144 via bus 138.

In the first cycle, the 1 multiplier 142 produces 2ΔX and the multiplier 144 produces 2ΔY.

In vector generator setup, XLTY (
x<Y) Flip-flop 150 is initially set to produce an O level output on XLTY output line 158. The O level of output line 158 indicates that ΔX is 67 or more. The level of output line 158 controls swap circuit 146 and MPX 140. In the initial state, line 158
is at the 0 level, so the swap circuit 146 does not perform a swap operation. Therefore, the output of the 1 multiplier 142 is MPX
114 and the output of the 1 multiplier 144 is the MPX112
given to.

At this point, the MPX 140 produces a ΔX output and M
PX 114 and repetition counter 154. ALUII
The first operation that O should perform is 2ΔY-2ΔX. Therefore, MPX 114 initially passes 2ΔX of the leftmost bus. The subtraction is controlled by a signal applied to control line 104 from the sequence control circuit. The output of ALUllo, representing 2ΔY-2ΔX, is sent via bus 116 to RB register 156 and stored therein.

Also, the code regarding this calculation result is FF through the line 120.
150 and the level of its output line 158 controls swap circuit 146 and MPX 140. That is, if line 158 is Lebel, give 2ΔX to MPX 112,
Since 2AY is given to MPX 114, 2ΔX-2ΔY is calculated instead of 2ΔY-2ΔX. Of course, A.L.
UIIO simply performs the specified calculations on the inputs it receives via input buses 106 and 108.

In the next cycle, 2ΔY passes through MPX112 to AL
At the same time as is provided to UIIO, ΔX from MPX 140 is provided to ALUllo via MPX 114, resulting in an output on bus 116 representing 2ΔY-ΔX;
It is stored in the RC register 162. RC register 162
The output of is given to MPX114.

At this point, the vector generator set amplifier is complete. In two cycles during setup, A
LULIO only performs subtraction.

The setup operation according to the present invention will now be described in more detail with reference to FIG.

In state STO, the vector generator is in an idle state and moves to state ST1 when it receives a start signal.

In state STI, calculation of 2ΔY−2ΔX is performed in ALUIIO like a multiplication, and the result is stored in the RB register 156. Further, FF 150 is set according to the signal level of line 120. The system then moves unconditionally to state ST2 and a second setup step is performed.

That is, 2ΔY from MPX112,! =ALUIIO which takes ΔX from MPX140 and 114 is 2ΔY
RC register 162 uses the calculation result of -ΔX as an error term.
give to At this time, ΔX is set in the repetition counter 154.

The setup of the vector generator according to the invention is completed in states STI and Sr1. States ST3 and Sr1, which will now be described, relate to well-known presentation Ham line generation techniques. If 20 on the line is the active level (SUM<
O), the system moves from state ST2 to state ST3, adds the next 2ΔY and the error term in RC register 162, loads the result into RC register 162, and decrements the count of iteration counter 154 by one. Line 12o is at an active level and repeat counter 154 counts 0.
If it is above, it means that there are still pixels to be drawn in the X direction without stepping in the Y direction, so
The system remains in state ST3 and continues line generation operations.

line 120 is no longer active and repeat counter 154
If the count of ST is greater than or equal to 0, the system is in state ST
3 to state ST4, the contents of the RB register 156 are subtracted from the error term of the RC register 162, and the result is set to R.
Return to C register 162. Also, the Y coordinate value is incremented and the count in repeat counter 154 is decremented by one.

If line 120 is still not at the active level, indicating that it is necessary to further increase the Y coordinate value, the system remains in state ST4 and increases the Y coordinate value. When line 120 becomes active level again, state ST3
Return to , and continue generating pixels as described above. Repetition counter 1
When the count of 54 becomes less than O, the operation ends;
Idle status 7! ! Move to S T O.

If the line 120 goes out of active level in the aforementioned state ST2, indicating an increase in the Y coordinate value, the system moves directly from state ST2 to state ST4, and the first pixel to be drawn is controlled in state ST4 instead of in state ST3. ,
The operations described above then continue.

Setup of the effect vector generator of the F0 invention can be done in two clock cycles. According to the present invention, the setup time is reduced to about half that of the prior art, whereas the prior art required four to five clock cycles.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of a vector generator implementing the setup technique of the present invention, FIG. 2 is a block diagram of a graphic display system including the vector generator of FIG.
FIG. 3 is a diagram illustrating the interrelationship of operating states for the vector generator setup technique of the present invention. 110... Arithmetic logic circuit, 112, 114.122
．． 140...Multiplexer, 124...Absolute value logic circuit, 126...X code flip-flop,
128... Y-code flip-flop, 132...
・Delta X register, 134... Delta X register, 142 and 144... Multiplier, 146... Swap circuit, 150... XLTY flip-flop, 154... Repetition counter, 156...RB register, 162...RC register. Applicant International Business Machines Corporation Representative Patent Attorney Oka 1) Tsugi Sei (1 other person) -ffi2In 7゛Graphics 6, System

Claims (1)

[Scope of Claims] Means for determining a difference function value regarding an X-coordinate displacement value and a Y-coordinate displacement value for a vector to be drawn; a storage means for storing the difference function value and its sign; A graphics vector generator setup device comprising: means for exchanging a value based on an X-coordinate value and a value based on a Y-coordinate value according to a code; and means for holding information for controlling the number of iterations of vector generation.