JPH03241802A - Chip type electronic parts - Google Patents
Chip type electronic partsInfo
- Publication number
- JPH03241802A JPH03241802A JP2038674A JP3867490A JPH03241802A JP H03241802 A JPH03241802 A JP H03241802A JP 2038674 A JP2038674 A JP 2038674A JP 3867490 A JP3867490 A JP 3867490A JP H03241802 A JPH03241802 A JP H03241802A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- cutting
- electrode
- type electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920005989 resin Polymers 0.000 claims abstract description 41
- 239000011347 resin Substances 0.000 claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 238000005520 cutting process Methods 0.000 claims abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 14
- 238000005476 soldering Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000000052 comparative effect Effects 0.000 description 5
- 239000003985 ceramic capacitor Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Details Of Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、積層型フィルムコンデンサ等のチップ型電子
部品に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to chip-type electronic components such as multilayer film capacitors.
従来の技術
チップ型電子部品は、プリント基板に直接端子を半田付
けされ、かつ非常に小型であるために電子回路の高集積
化設計に適している。チップ型電子部品の外装としては
樹脂モールド型のタイプ、樹脂塗膜で被覆したタイプ、
釦よび無外装タイプ等がある。Conventional chip-type electronic components have terminals soldered directly to printed circuit boards and are extremely small, making them suitable for highly integrated designs of electronic circuits. The exterior of chip-type electronic components includes resin mold type, resin coating type,
There are button and non-exterior types.
また、電極の形状については、第７図に示すような、例
えばチップ型積層セラミ、クコンデンサやチップ型抵抗
器釦よび積層フィルムコンデンサでは、素子１１の両端
の電極２が素子端面だけではなく、素子端面近傍の上下
面及び左右面（側面）にも形成されている。樹脂モール
ド型のタイプは、電極がリードフレームによυ形成され
ているので、素子１３０両端の電極２は素子端面と素子
端面近傍の下面にのみ形成されている。この状態をタン
タル電解コンデンサを例にとって第８図に示す。Regarding the shape of the electrodes, for example, in chip-type laminated ceramics, capacitors, chip-type resistor buttons, and laminated film capacitors as shown in FIG. They are also formed on the upper and lower surfaces and the left and right surfaces (side surfaces) near the end faces of the element. In the resin mold type, the electrodes are formed by a lead frame, so the electrodes 2 at both ends of the element 130 are formed only on the element end face and the lower face near the element end face. This state is shown in FIG. 8 using a tantalum electrolytic capacitor as an example.
発明が解決しようとする課題
チップ型電子部品はフロー法、リフロー法等により半田
付け（表面実装）されているが、近年、高集積化される
につれて半田付けが難しくなってきている。すなわち、
回路パターンが微細になってきているために、半田付け
する際に余分な半田が不必要な部分に付着して、短絡不
良が発生しやすいという課題がある。Problems to be Solved by the Invention Chip-type electronic components are soldered (surface mounted) by a flow method, a reflow method, etc., but in recent years, soldering has become more difficult as the degree of integration has increased. That is,
As circuit patterns have become finer, there is a problem in that during soldering, excess solder adheres to unnecessary parts, making short circuits more likely to occur.
この課題は、チップ型積層セラミ、クコンデンサやチッ
プ型抵抗器釦よびチップ型積層フィルムコンデンサのよ
うに電極が素子端面だけではなく、素子端面近傍の上下
面及び左右面（側面）にも形成されているタイプの電子
部品では、特に発生しやすい、、
この課題について’＄”ｌ ：涌を用いて説明する。第
９図ａ、ｂにふ・いで、１１は従来の積層セラミ、クコ
ンデンサ、１２は基板上に形成されているランド（銅箔
製）である。説明のためランドの幅を素子幅と同じとす
る。第ｇ Ｌｊ！ ａのように高密度でない場合は、余
分な半田が残ったとしても素子間の間隔が広いので短絡
しないが、第９図すのように高密度の場合は、余分の半
田が素子側面の電極の半田濡れ性によってつながって短
絡しやすい。This problem arises because electrodes are formed not only on the element end face, but also on the top, bottom, left and right (side) faces near the element end face, such as chip-type laminated ceramic capacitors, chip-type resistor buttons, and chip-type laminated film capacitors. This problem is particularly likely to occur in electronic components of the type that is used.This problem will be explained using a '$'l :waku.Referring to Figures 9a and b, 11 is a conventional laminated ceramic, capacitor, Reference numeral 12 indicates a land (made of copper foil) formed on the board.For the sake of explanation, the width of the land is assumed to be the same as the element width.If the density is not as high as in No. gLj!a, excess solder will be removed. Even if some residual solder remains, it will not cause a short circuit because the spacing between the elements is wide, but in the case of high density as shown in Figure 9, the excess solder is likely to connect due to the solder wettability of the electrodes on the side of the element, causing a short circuit.
本発明の目的は、高密度に表面実装した場合でも、半田
による短絡のないチップ型電子部品を提供することにあ
る。An object of the present invention is to provide a chip-type electronic component that does not cause short circuits due to solder even when surface-mounted at high density.
課題を解決するための手段
上記課題を解決するために本発明のチップ型電子部品は
、電極を形成した母素子を切断して個別の素子とされる
チップ型電子部品本体の、前記切断により形成された両
切断面釦よび両切断面以外の切断面近傍を樹脂によう被
覆したことを特徴とするものである。Means for Solving the Problems In order to solve the above problems, the chip-type electronic component of the present invention is formed by cutting a chip-type electronic component main body into individual elements by cutting a mother element on which electrodes are formed. The button is characterized in that both cut surfaces of the button and the vicinity of the cut surfaces other than both of the cut surfaces are coated with resin.
作用
本発明のチップ型電子部品は、電極の素子側面部ふ・よ
び電極端面の一部が樹脂により被覆されているので、半
田付は時に電極の素子側面部に半田が付着したり、素子
側面部に半田を呼び込むことがなく、短絡不良となるこ
とを防止することができる。したがっで、高密度の表面
実装に対応するチップ型電子部品を実現することができ
る。Function In the chip-type electronic component of the present invention, the element side surface of the electrode and a part of the electrode end surface are coated with resin, so when soldering, sometimes the solder adheres to the element side surface of the electrode or the element side surface is coated with resin. There is no need to introduce solder into the parts, and it is possible to prevent short-circuit failures. Therefore, a chip-type electronic component compatible with high-density surface mounting can be realized.
実施例
以下、本発明の実施例について図面を参照しながら説明
する。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.
（実施例１）
本発明の一例と＋＝、て、チップ型積層フィルムコンデ
ンサについて説明する。(Example 1) An example of the present invention and a chip-type multilayer film capacitor will be described.
積層フィレムコンデンサはその製造工程に釦いて第２図
に示すように、母素子１４を切断刃１６により切断して
個別のコンデンサ素子１を形成する。切断によや形成さ
れた切断面４は、電極端面が露出し、ているので、コン
デンサ特性を劣下させないように樹脂等で外装される。As shown in FIG. 2, the manufacturing process of the multilayer film capacitor is such that the mother element 14 is cut by a cutting blade 16 to form individual capacitor elements 1. The cut surface 4 formed by cutting has the electrode end surface exposed and is therefore covered with resin or the like so as not to deteriorate the capacitor characteristics.
第３図は、チ。Figure 3 shows Chi.
プ型積層フィルムコンデンサの切断面に紫外線硬化樹脂
を用いて外装する工程の一例を示す斜視図である。第３
図にかいて、１は積層フィルムコンデンサ素子、２はコ
ンデンサの電極引き出し端面に、金属溶射法により形成
された後、半田めっきを施してなる電極である。積層フ
ィルムコンデンサ素子１の切断面４の上に、金属ローラ
８を用いて紫外線硬化樹脂９Ｃを所定の厚さに塗布する
。FIG. 2 is a perspective view showing an example of a step of packaging a cut surface of a double-layered multilayer film capacitor with an ultraviolet curing resin. Third
In the figure, 1 is a laminated film capacitor element, and 2 is an electrode formed by metal spraying and solder plating on the electrode extension end face of the capacitor. On the cut surface 4 of the laminated film capacitor element 1, ultraviolet curing resin 9C is applied to a predetermined thickness using a metal roller 8.
ここで、紫外線硬化樹脂９ａはかき上げローラ７と中間
転写ローラ６によって金属ローラ８上に運ばれ、塗布膜
厚及び塗布領域を制御するために余分な樹脂９ｂはドク
ターブレード６によってかき落とされる。金属ローラ８
の表面には膜厚を制御された樹脂層９Ｃが形成される。Here, the ultraviolet curing resin 9a is carried onto the metal roller 8 by the scraping roller 7 and the intermediate transfer roller 6, and the excess resin 9b is scraped off by the doctor blade 6 in order to control the coating film thickness and coating area. metal roller 8
A resin layer 9C with a controlled thickness is formed on the surface of the resin layer 9C.
第４図に示すように前記樹脂層９Ｃに、コンデンサ素子
１の切断面４が接触することにより、切断面４の全体、
釦よび電極端面と電極上下面の切断面近傍部分に均一に
塗布される。樹脂の塗布膜厚及び塗布領域は、ドクター
ブレード６により制御された樹脂層９Ｃの厚さ、樹脂粘
度、樹脂温度、塗布速度等種々の条件により制御するこ
とが可能である。本実施例では塗布領域（片側）は切断
輻に対して１０肇、塗布膜厚ば０．０５ｍｍとした。塗
布された紫外線硬化樹脂９Ｃは、紫外線ランプ１ｏによ
って紫外線を照射して硬化し、必敬に応じて恒温槽など
で熱硬化する。As shown in FIG. 4, when the cut surface 4 of the capacitor element 1 comes into contact with the resin layer 9C, the entire cut surface 4,
It is evenly applied to the button, the electrode end surface, and the area near the cut surface of the upper and lower surfaces of the electrode. The resin coating thickness and coating area can be controlled by various conditions such as the thickness of the resin layer 9C controlled by the doctor blade 6, resin viscosity, resin temperature, and coating speed. In this example, the coating area (on one side) was 10 degrees with respect to the cutting radius, and the coating film thickness was 0.05 mm. The applied ultraviolet curable resin 9C is cured by irradiating ultraviolet rays with an ultraviolet lamp 1o, and if necessary, is thermally cured in a constant temperature bath or the like.
こつようにして得られた本発明のチップ型積層フィルム
コンデンサは、第１図に示すように切断面が樹脂９によ
り外装されてあ・す、かつ切断面と同一面内にある電極
の側面（第１（Ｂ３ Ｂ 、 Ｂ’で示す）も外装され
、を極端面（第６図ム、Ａ′で示す）の切断面近傍にも
樹脂１６ａ 、１５ｂが塗布さｔ′してお・す、切断面
近傍ｔ、） １１１：面にも樹脂１７ａｇ１７ｂが改布
されている１、
本発明のチ、２プ型ｆｌフィルムフンデンサ１００個を
、側面の間隔が０ 、５ ｒｒｒｍ ：’こなるように
１列に１０個ずつ、１０列に基板に並べて、フロー法に
より半田付けした。なふ・、ランドの幅は素子の幅とＩ
Ｍ−にした。比較例として前記樹脂外装を施していない
チップ型積層フィルムコンデンサを同時に半田付けした
。、半田付は後の状態を観察すると、比較例では、短絡
が７箇所見られたが、本発明のコンデンサ素子では短絡
箇所が１つも発生していなかった。The chip-type multilayer film capacitor of the present invention thus obtained has a cut surface covered with resin 9 and a side surface of the electrode (in the same plane as the cut surface) as shown in FIG. The first part (B3 B, shown as B') is also covered, and resins 16a and 15b are also applied near the cut surface of the extreme face (Fig. 6, shown as A'). Near the cut surface t,) 111: Resin 17ag17b is also modified on the surface. They were arranged on a board in 10 rows, 10 in each row, and soldered using the flow method. Nafu, the width of the land is the width of the element and I
I changed it to M-. As a comparative example, a chip-type multilayer film capacitor without the resin sheath was soldered at the same time. When observing the state after soldering, seven short circuits were observed in the comparative example, but no short circuit occurred in the capacitor element of the present invention.
さらに本発明のコンデンサ素子の間隔金０咽（密着状態
）に、かつ、ランドの幅を素子の切断幅より小さく、素
子−を１列に１０個ずつ、１０列に基板に並べて、前記
試験と同様にフロー法により半田付けした。半田付は後
の状態を観察すると、短絡の発生は皆無であった。比較
例とし２て前記の試験と同様に樹脂外装を施していない
チップ型積ＦｆＪフィルムコンデンサを同時に半田付け
した。比較例ではすべての素子が第５図に示すような短
絡状態となったが、本発明品では第６図に示すように短
絡状態は全くなかった。Furthermore, the capacitor elements of the present invention were arranged in 10 rows on the board with 10 elements in each row, with the spacing between the metals zero (in close contact) and the width of the land being smaller than the cutting width of the elements, and the above test was carried out. Soldering was performed in the same manner using the flow method. When observing the state after soldering, there was no occurrence of short circuit. As Comparative Example 2, a chip type FfJ film capacitor without a resin sheath was soldered at the same time as in the above test. In the comparative example, all the elements were in a short-circuited state as shown in FIG. 5, but in the product of the present invention, there was no short-circuited state as shown in FIG.
以上のように本発明のフィルムコンデンサは、隣接する
素子の電極間で半田による短絡が生じにくいので、コン
デンサ素子の側面の間隔をつめて高密度の表面実装をす
ることができる。As described above, in the film capacitor of the present invention, short circuits due to solder do not easily occur between the electrodes of adjacent elements, so that high-density surface mounting can be performed by reducing the spacing between the side surfaces of the capacitor elements.
（実施例２）
本発明の第２の実施例を以下に説明する。実施例１と同
様に本発明のチ、・プ型積層フィルムコンデンサを作成
したが、このとき電極端面が樹脂で塗布される領域（第
１図の１６ａ、ｂで示す）の大きさを変えて６種類作威
した。前記の塗布される領域の大きさは切断幅に対する
塗布領域の片側の１幅の大きさの割合で示す。これらの
素子を実施例１の第２の試験に用いた基板（コンデンサ
素子が互いに接触するタイプ）に実施例１と同様に（１
列に１０個、１０列計重００個）実装して、フロー法に
より半田付けし、第６図に示すような短絡の発生数と、
半田付は強度を測定した。その結果を第１表に示す。(Example 2) A second example of the present invention will be described below. A chip-type multilayer film capacitor of the present invention was prepared in the same manner as in Example 1, but the size of the area (indicated by 16a and 16b in FIG. 1) where the electrode end surface was coated with resin was changed. I created 6 types. The size of the area to be coated is expressed as the ratio of one width on one side of the coated area to the cutting width. These elements were placed on the substrate used in the second test of Example 1 (of the type in which the capacitor elements are in contact with each other) in the same manner as in Example 1 (1
10 pieces in a row, 10 rows weighing 00 pieces) were mounted and soldered using the flow method, and the number of short circuits as shown in Figure 6 was determined.
The soldering strength was measured. The results are shown in Table 1.
第 １ 表 ＊はんだ付は強度はＸＩムＪ規格に準拠。Chapter 1 Table *Soldering strength complies with XIMJ standard.
以上の結果より、本発明は短絡不良の発生が少なく、半
田付は強度も１貯ｆ以上で良好であることがわかる。な
ふ・、第１表から塗布領域の大きさは１０から３０係の
範囲が望ましいことがわかる。From the above results, it can be seen that the present invention has a low occurrence of short-circuit defects and has good soldering strength of 1 f or more. From Table 1, it can be seen that the size of the coating area is preferably in the range of 10 to 30 mm.
なか、前記実施例では積層フィルムコンデンサの例を示
したが、本発明の適用はこれに限るものではなく、電極
が素子端面だけではなく、素子端面近傍の上下面及び左
右面（側面）にも形成されているチップ型積層セラミッ
クコンデンサやチ。In the above embodiment, an example of a laminated film capacitor is shown, but the present invention is not limited to this, and the electrodes are not only on the element end face but also on the upper and lower surfaces and left and right faces (side surfaces) near the element end face. Chip-type multilayer ceramic capacitors and chips are formed.
プ型抵抗器などにも適用できる。また外装樹脂や外装方
法も本実施例に限るものではなく、熱硬化型の樹脂等、
電子部品の外装に一般的に用いられる樹脂であれば用い
ることができる。外装方法にはタンボ方式、オフセット
印刷方式、デイ、ピング方式などが適用できる。筐た、
電極表面の金属も半田に限るものではなく、半田付は性
を向上させることが期待できる。例えば錫を含む金属で
被覆されていれば本発明の目的にかなう。It can also be applied to double-type resistors. Furthermore, the exterior resin and exterior method are not limited to those in this example; thermosetting resins, etc.
Any resin commonly used for the exterior of electronic components can be used. As the packaging method, the tanbo method, offset printing method, day printing method, ping method, etc. can be applied. Cabinet,
The metal on the electrode surface is not limited to solder, and soldering can be expected to improve properties. For example, the object of the present invention can be achieved if it is coated with a metal containing tin.
発明の効果
以上のように本発明によれば、電極を短絡させることな
く、高密度で表面実装可能なチップ型電子部品を実現す
ることができる。Effects of the Invention As described above, according to the present invention, a chip-type electronic component that can be surface-mounted at high density can be realized without shorting the electrodes.
第１図は本発明の一実施例のチップ型積層フィルムコン
デンサを示す外観斜視図、第２図はチップ型積層フィル
ムコンデンサの切断工程を示す斜視図、第３図は同コン
デンサの切断に紫外線硬化樹脂を用いて外装する工程の
一例を示す斜視図、第４図は同チップ型積層セラミ、ク
コンデンサの樹脂外装工程の詳細金示す要部の上面図、
第５図は比較例のコンデンサ素子を高密度（間隔０＋＋
ａ＋＋）に実装して短絡不良となった状態を示す斜視図
、第６図は本発明のコンデンサ素子を高密度（間隔０ｒ
ａｎ）に実装した状態を示す斜視図である。第７図は従
来のチップ型積層セラミックコンデンサの外観斜視図、
第８図は従来の樹脂モールドタイプのチップ型タンタル
電解コンデンサの外観斜視図、第９図ａ、ｂはコンデン
サの面実装後の状態を示す斜視図である。
１・・・・・・チップ型積層フィルムコンデンサ、２・
・・・・電極、９・・・・・・外装樹脂、１６＆ 、１
６ｂ・・・・・・電極端面が樹脂で塗布される領域、１
７１Ｌ、１７ｂ・・・・・・素子表面が樹脂で塗布され
る領域。Fig. 1 is an external perspective view showing a chip-type multilayer film capacitor according to an embodiment of the present invention, Fig. 2 is a perspective view showing the cutting process of the chip-type multilayer film capacitor, and Fig. 3 is an ultraviolet curing process for cutting the capacitor. A perspective view showing an example of the process of encasing the same chip-type laminated ceramic capacitor with resin;
Figure 5 shows a comparative capacitor element with high density (spacing 0++
Fig. 6 is a perspective view showing a state in which the capacitor element of the present invention is mounted in a high-density (spacing 0 r
FIG. Figure 7 is an external perspective view of a conventional chip-type multilayer ceramic capacitor.
FIG. 8 is an external perspective view of a conventional resin molded chip type tantalum electrolytic capacitor, and FIGS. 9a and 9b are perspective views showing the state of the capacitor after surface mounting. 1... Chip type multilayer film capacitor, 2.
... Electrode, 9 ... Exterior resin, 16 & , 1
6b...A region where the electrode end surface is coated with resin, 1
71L, 17b...A region where the element surface is coated with resin.
Claims (4)
れるチップ型電子部品本体の、前記切断により形成され
た両切断面および切断面以外の切断面近傍を樹脂により
被覆したことを特徴とするチップ型電子部品。(1) Both cut surfaces formed by the cutting and the vicinity of the cut surfaces other than the cut surfaces of the chip-type electronic component main body, which is made into individual elements by cutting the mother element on which the electrodes are formed, are coated with resin. Features of chip-type electronic components.
電極部分で片端より切断幅方向の電極幅の５０％未満で
あることを特徴とする請求項（１）に記載のチップ型電
子部品。(2) The chip type electronic device according to claim (1), wherein the resin coating in the vicinity of the cut surface other than the cut surface containing the electrode is less than 50% of the electrode width in the cutting width direction from one end at the electrode portion. parts.
サであることを特徴とする請求項（１）または（２）に
記載のチップ型電子部品。(3) The chip-type electronic component according to claim (1) or (2), wherein the chip-type electronic component main body is a multilayer film capacitor.
溶射法により形成され、かつ電極表面が半田もしくは少
なくともすずを含む金属で被覆されていることを特徴と
する請求項（３）に記載のチップ型電子部品。(4) The chip according to claim (3), wherein the base layer of the electrode of the multilayer film capacitor is formed by a metal spraying method, and the electrode surface is coated with solder or a metal containing at least tin. type electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2038674A JP2599478B2 (en) | 1990-02-20 | 1990-02-20 | Chip type electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2038674A JP2599478B2 (en) | 1990-02-20 | 1990-02-20 | Chip type electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03241802A true JPH03241802A (en) | 1991-10-29 |
| JP2599478B2 JP2599478B2 (en) | 1997-04-09 |
Family
ID=12531821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2038674A Expired - Fee Related JP2599478B2 (en) | 1990-02-20 | 1990-02-20 | Chip type electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2599478B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014103223A (en) * | 2012-11-19 | 2014-06-05 | Ngk Insulators Ltd | Piezoelectric element |
| US8773840B2 (en) | 2009-12-11 | 2014-07-08 | Murata Manufacturing Co., Ltd. | Monolithic ceramic electronic component |
| US8773839B2 (en) | 2009-12-11 | 2014-07-08 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component |
| JP2014138144A (en) * | 2013-01-18 | 2014-07-28 | Ngk Insulators Ltd | Ceramic component and method for manufacturing the same |
| US9082556B2 (en) | 2009-12-11 | 2015-07-14 | Murata Manufacturing Co., Ltd. | Monolithic ceramic capacitor |
| JP2015188111A (en) * | 2015-06-25 | 2015-10-29 | Tdk株式会社 | Electronic part |
| US9245688B2 (en) | 2009-12-11 | 2016-01-26 | Murata Manufacturing Co., Ltd. | Monolithic ceramic capacitor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS646029U (en) * | 1987-06-30 | 1989-01-13 | ||
| JPH0243718A (en) * | 1988-08-04 | 1990-02-14 | Matsushita Electric Ind Co Ltd | Exterior coating process of capacitor |
-
1990
- 1990-02-20 JP JP2038674A patent/JP2599478B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS646029U (en) * | 1987-06-30 | 1989-01-13 | ||
| JPH0243718A (en) * | 1988-08-04 | 1990-02-14 | Matsushita Electric Ind Co Ltd | Exterior coating process of capacitor |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8773840B2 (en) | 2009-12-11 | 2014-07-08 | Murata Manufacturing Co., Ltd. | Monolithic ceramic electronic component |
| US8773839B2 (en) | 2009-12-11 | 2014-07-08 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component |
| US9082556B2 (en) | 2009-12-11 | 2015-07-14 | Murata Manufacturing Co., Ltd. | Monolithic ceramic capacitor |
| US9245688B2 (en) | 2009-12-11 | 2016-01-26 | Murata Manufacturing Co., Ltd. | Monolithic ceramic capacitor |
| JP2014103223A (en) * | 2012-11-19 | 2014-06-05 | Ngk Insulators Ltd | Piezoelectric element |
| US9530954B2 (en) | 2012-11-19 | 2016-12-27 | Ngk Insulators, Ltd. | Piezoelectric element |
| JP2014138144A (en) * | 2013-01-18 | 2014-07-28 | Ngk Insulators Ltd | Ceramic component and method for manufacturing the same |
| US9950965B2 (en) | 2013-01-18 | 2018-04-24 | Ngk Insulators, Ltd. | Ceramic element and method of manufacturing the same |
| JP2015188111A (en) * | 2015-06-25 | 2015-10-29 | Tdk株式会社 | Electronic part |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2599478B2 (en) | 1997-04-09 |
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