JPH03241745A - Formation of wiring pattern - Google Patents

Formation of wiring pattern

Info

Publication number
JPH03241745A
JPH03241745A JP3732390A JP3732390A JPH03241745A JP H03241745 A JPH03241745 A JP H03241745A JP 3732390 A JP3732390 A JP 3732390A JP 3732390 A JP3732390 A JP 3732390A JP H03241745 A JPH03241745 A JP H03241745A
Authority
JP
Japan
Prior art keywords
metal film
melting point
high melting
wiring pattern
point metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3732390A
Other languages
Japanese (ja)
Inventor
Daiichi Harada
原田 大一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3732390A priority Critical patent/JPH03241745A/en
Publication of JPH03241745A publication Critical patent/JPH03241745A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To control a missing wiring pattern and increasing resistance due to disconnection by processing a high melting point metal film being an antireflection film through O2 plasma for several minutes and also through nitric acid so as to lower the reflectivity of the metal film. CONSTITUTION:An antireflection high melting point metal film 4 by means of titanium is formed on a metal film 3. Further, the surface of the high melting point metal film 4 is subjected to surface roughening by O2 plasma for about several minutes and also processed by nitric acid. Therefore, the reflectivity of the surface of the high melting point metal film 4 lowers in comparison with that before processing. Further, a wiring pattern 7 is formed when the high melting point metal film 4 and the metal film 3 are etched by RIE while a resist pattern 6 is used as a mask. Thus, it is possible to prevent a missing wiring pattern and increasing disconnection and resistance.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、反射防止膜として高融点金属膜を用いた金
属配線パターンの形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of forming a metal wiring pattern using a high melting point metal film as an antireflection film.

(従来の技術) 金属パターンの形成方法としては、たとえば、特開昭5
9−154027号公報により開示されている方法があ
る。
(Prior art) As a method for forming a metal pattern, for example, Japanese Patent Application Laid-open No. 5
There is a method disclosed in Japanese Patent No. 9-154027.

この開示方法の場合は、下地基板上に比較的光反射率の
大きい第1の金属層を形成し、この第1の金属層の上に
光反射率の低い第2の導電性膜を形成した後、第2の導
電性膜の上に写真製版技術によって耐エツチング性のホ
トレジスト膜からなる所望のパターンマスクを形成し、
このマスクを介して第2の導電性膜と第1の金属の層に
ドライエツチングを施すようにしたものである。
In the case of this disclosed method, a first metal layer having a relatively high light reflectance is formed on a base substrate, and a second conductive film having a low light reflectance is formed on this first metal layer. After that, a desired pattern mask made of an etching-resistant photoresist film is formed on the second conductive film by photolithography,
Dry etching is applied to the second conductive film and the first metal layer through this mask.

一方、第4図は従来の別の配線パターンの形成方法を示
す工程断面図であり、この第4図により、従来の配線パ
ターンの形成方法について説明する。
On the other hand, FIG. 4 is a process sectional view showing another conventional wiring pattern forming method, and the conventional wiring pattern forming method will be explained with reference to FIG.

まず、第4図(a)に示すように、Stの下地基板1上
に絶縁膜2としてのBPSG (ホウ素−リンケイ酸ガ
ラス)を介して配線材料としてN −S i、あるいは
jV −3t−Cuの金属膜3をスパッタ法等の方法に
より5000人〜10000人形成する。
First, as shown in FIG. 4(a), N-Si or jV-3t-Cu is deposited as a wiring material on a St base substrate 1 through BPSG (boron-phosphosilicate glass) as an insulating film 2. The metal film 3 is formed by 5,000 to 10,000 people by a method such as a sputtering method.

次に、第4図(b)に示すように、金属膜3上に反射防
止膜として、高融点金属膜4を300人〜1000人程
度形成する。この高融点金属膜4としては、タングステ
ン、チタン、モリブデン、ニッケル等があげられる。
Next, as shown in FIG. 4(b), a high melting point metal film 4 is formed as an antireflection film on the metal film 3 by about 300 to 1000 people. Examples of the high melting point metal film 4 include tungsten, titanium, molybdenum, and nickel.

次に、第4図(c)に示すように、高融点金属膜4上に
バターニングのためのレジスト5を塗布し、露光・現像
により第4図(d)に示すように、レジストパターン6
を形成する。
Next, as shown in FIG. 4(c), a resist 5 for patterning is applied on the high melting point metal film 4, and by exposure and development, a resist pattern 6 is formed as shown in FIG. 4(d).
form.

次に、第4図(e)に示すように、レジストパターン6
をマスクにして、上記高融点金属膜4および金属膜3を
RIE (リアクティブイオンエツチング)により、エ
ツチングし、配線パターン7を形成する。
Next, as shown in FIG. 4(e), a resist pattern 6
Using as a mask, the high melting point metal film 4 and metal film 3 are etched by RIE (reactive ion etching) to form a wiring pattern 7.

第5図(a)〜第5図(f)は上記高融点金属膜4とし
て、チタン500人、表面処理の場合のレジストパター
ン6の上面SEM(走査型電子顕微鏡)の観測像を示す
図であり、第5図(a)と第5図(d)、第5図(b)
と第5図(c)、第5図(c)と第5図(f)はそれぞ
れ露光量500 m5ec、変換差−0,0岬、露光量
620 m5ec、変換差−0,1ttm 、露光量7
50 m5ec。
5(a) to 5(f) are views showing SEM (scanning electron microscope) images of the upper surface of the resist pattern 6 in the case of surface treatment using titanium as the high melting point metal film 4. Yes, Figure 5(a), Figure 5(d), Figure 5(b)
and Fig. 5(c), Fig. 5(c) and Fig. 5(f) respectively have an exposure amount of 500 m5ec, a conversion difference of -0.0 cape, an exposure amount of 620 m5ec, a conversion difference of -0.1ttm, and an exposure amount. 7
50 m5ec.

変換差−0,2amの場合を示しており、露光量の多少
にかかわらず、配線パターン7が欠落していることがわ
かる。
This shows the case where the conversion difference is -0.2 am, and it can be seen that the wiring pattern 7 is missing regardless of the amount of exposure.

(発明が解決しようとする課題) しかしながら、以上述べた第4図に示す配線パターンの
形成方法では、金属膜3の露光光の波長(436nm、
365nm)での反射率(以下反射率という)は80〜
90%であり、高融点金属膜4の反射率でも60%程度
であり、レジスト5のバターニングの際、反射光により
レジストパターン6が欠落し、ひいては配線パターンが
欠落し、断線や抵抗の増加といった問題を引き起こす。
(Problems to be Solved by the Invention) However, in the method for forming the wiring pattern shown in FIG. 4 described above, the wavelength of the exposure light of the metal film 3 (436 nm,
365 nm) (hereinafter referred to as reflectance) is 80~
90%, and the reflectance of the high melting point metal film 4 is also about 60%, and when patterning the resist 5, the resist pattern 6 is missing due to reflected light, and the wiring pattern is also missing, resulting in disconnection and increased resistance. cause such problems.

この発明は前記従来技術が持っている問題点のうち、反
射防止膜である高融点金属膜の反射率が充分低くないこ
とに起因するその反射光によるレジストパターンが欠落
して、配線が断線し易いという問題点について解決した
配線パターンの形成方法を提供するものである。
This invention solves the problems of the prior art described above, which is caused by the fact that the reflectance of the high-melting point metal film that is the anti-reflection film is not low enough, and the resist pattern is missing due to the reflected light and the wiring is disconnected. The present invention provides a method for forming a wiring pattern that solves the problem of ease of use.

(課題を解決するための手段) この発明は前記問題点を解決するために、配線パターン
の形成方法において、反射防止膜である高融点金属膜を
0□プラズマで数分処理しかつ硝酸で処理し、その反射
率を10%程度低くする工程を導入したものである。
(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a wiring pattern forming method in which a high melting point metal film, which is an anti-reflection film, is treated with 0□ plasma for several minutes and then treated with nitric acid. However, a process has been introduced to lower the reflectance by about 10%.

(作 用) この発明によれば、配線パターンの形成方法において、
以上のような工程を導入したので、高融点金属膜の反射
率が10%程度低下することにより、後工程でレジスト
パターンの形成時に高融点金属膜による反射光がなくな
り、レジストパターンの欠落を抑制し、ひいては配線パ
ターンの欠落、断線による抵抗の増加を抑制する。した
がって、前記問題点を除去できる。
(Function) According to the present invention, in the method of forming a wiring pattern,
By introducing the above process, the reflectance of the high melting point metal film is reduced by about 10%, which eliminates the light reflected by the high melting point metal film during the formation of the resist pattern in the subsequent process, suppressing the loss of the resist pattern. This also suppresses increases in resistance due to missing wiring patterns and disconnections. Therefore, the above problem can be eliminated.

(実施例) 以下、この発明の配線パターンの形成方法の実施例につ
いて図面に基づき説明する。第1図(a)ないし第1図
(f)はその一実施例の工程断面図である。
(Example) Hereinafter, an example of the method for forming a wiring pattern of the present invention will be described based on the drawings. FIGS. 1(a) to 1(f) are process cross-sectional views of one embodiment.

この第1図(a)〜第1図(f)において、−第4図(
a)〜第4図(e)と同一部分には、同一符号を付して
述べる。
In this Fig. 1(a) to Fig. 1(f), - Fig. 4(
The same parts as in a) to FIG. 4(e) will be described with the same reference numerals.

まず、第1図(a)に示すように、従来法と同じように
Siの下地基板1上にBPSGによる絶縁膜2を形成し
、この絶縁膜2上に配線用の金属膜3を形成する。
First, as shown in FIG. 1(a), an insulating film 2 made of BPSG is formed on a Si base substrate 1 as in the conventional method, and a metal film 3 for wiring is formed on this insulating film 2. .

さらに、第1図(b)に示すように、上記金属膜3上に
チタンによる反射防止用の高融点金属膜4を500人程
度の厚さに形成する。
Furthermore, as shown in FIG. 1(b), a high melting point metal film 4 made of titanium for antireflection is formed on the metal film 3 to a thickness of about 500 mm.

ここで、バターニングのためのレジスト5を塗布する前
に、第1図(c)に示すように、上記高融点金属膜4の
表面を0□プラズマにて1分〜5分程度表面の粗面化処
理するとともに、その表面を硝酸により処理する。
Here, before applying the resist 5 for patterning, as shown in FIG. In addition to surface treatment, the surface is treated with nitric acid.

これにより、高融点金属膜4の表面の反射率は処理前に
比べ約10%程度低下する。この粗面化処理の後、第1
図(d)に示すように、レジスト5を塗布し、次いで、
第1図(e)に示すように、露光・現像を行い、レジス
トパターン6を形成する。
As a result, the reflectance of the surface of the high melting point metal film 4 is reduced by about 10% compared to before the treatment. After this roughening treatment, the first
As shown in figure (d), resist 5 is applied, and then
As shown in FIG. 1(e), exposure and development are performed to form a resist pattern 6.

さらに、第1図(f)に示すように、レジストパターン
6をマスクにして、高融点金属膜4と金属膜3をRIE
によりエツチングすることにより、配線パターン7を形
成する。
Furthermore, as shown in FIG. 1(f), using the resist pattern 6 as a mask, the high melting point metal film 4 and the metal film 3 are subjected to RIE.
By etching, a wiring pattern 7 is formed.

第2図に高融点金属膜4としてチタン500人の場合、
反射率の02プラズマ処理時間依存性を示す。処理時間
数分で反射率が10%程度低下し5分程度で飽和し、一
定の値となっているのがわかる。これから処理時間は1
分〜5分程度で充分であると考えられる。
In the case of 500 titanium as the high melting point metal film 4 in Figure 2,
The dependence of reflectance on 02 plasma treatment time is shown. It can be seen that the reflectance decreases by about 10% after several minutes of processing time, saturates after about 5 minutes, and remains at a constant value. From now on, the processing time is 1
It is considered that about 5 minutes is sufficient.

第3図(a)〜第3図(f)は上記高融点金属膜4とし
て、チタンを500人程度の厚さに形成し、チタン50
0人0□プラズマ処理、さらに硝酸処理をして粗面化し
た場合のレジストパターン6の上面SEM(走査型電子
顕微鏡)観察像を示す図である。
3(a) to 3(f), titanium is formed to a thickness of about 500 mm as the high melting point metal film 4,
0 is a diagram showing an SEM (scanning electron microscope) observation image of the upper surface of the resist pattern 6 when the surface is roughened by plasma treatment and further nitric acid treatment.

第3図(a)と第3図(d)、第3図(b)と第3図(
e)、第3図(c)と第3図(f)はそれぞれ露光量4
70m5ec、変換差−0,0−1露光量560m5e
c、変換差−0,1pm、露光量700m5ec、変換
差−0,2pmの場合である。
Figure 3(a) and Figure 3(d), Figure 3(b) and Figure 3(
e), Figure 3(c) and Figure 3(f) are each exposed at an exposure level of 4.
70m5ec, conversion difference -0,0-1 exposure amount 560m5e
c, conversion difference -0.1 pm, exposure amount 700 m5ec, conversion difference -0.2 pm.

この第3図(a)〜第3図(f)からも明らかなように
、露光量の多いところでは配線パターン7の欠落がみら
れるが、露光量の少ないところでは配線パターン7の欠
落は少なくなっており、反射率低下の効果が顕著にあら
れれていることがわかる。
As is clear from FIGS. 3(a) to 3(f), the wiring pattern 7 is missing in areas where the exposure amount is high, but the wiring pattern 7 is less likely to be missing in areas where the exposure amount is low. It can be seen that the effect of reducing the reflectance is remarkable.

(発明の効果) 以上詳細に説明したように、この発明によれば、反射防
止膜である高融点金属膜を0□プラズマと硝酸で処理し
てその反射率が10%程度低下するようにしたので、高
融点金属膜の反射によるレジストパターンの欠落に起因
する配線パターンの欠落や断線、抵抗の増加といったよ
うな問題点を解消でき、したがって、より安定した配線
パターンの形成が可能となるものである。
(Effects of the Invention) As explained in detail above, according to the present invention, the high melting point metal film, which is an antireflection film, is treated with 0□ plasma and nitric acid to reduce its reflectance by about 10%. Therefore, problems such as missing wiring patterns, disconnections, and increased resistance caused by missing resist patterns due to reflection from high-melting point metal films can be solved, and it is therefore possible to form more stable wiring patterns. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないし第1図(f)はこの発明の配線パタ
ーンの形成方法の一実施例を説明するための工程断面図
、第2図は同上実施例における高融点金属に施す0□プ
ラズマ処理対反射率の関係を示す特性図、第3図(a)
ないし第3図(f)は同上実施例における高融点金属に
02プラズマ処理と硝酸処理を施した場合のレジストパ
ターンの上面のSEM観察像を示す図、第4図(a)〜
第4図(e)は従来の配線パターンの形成方法を説明す
るための工程断面図、第5図(a)〜第5図(f)は従
来の配線パターンの形成方法における高融点金属膜に表
面処理をしない場合のレジストパターンの上面SEM観
察像を示す図である。 ■・・・下地基板、2・・・絶縁膜、3・・・金属膜、
4・・・高融点金属膜、5・・・レジスト、6・・・レ
ジストパターン、7・・・配線パターン。 $清明の工程跡向図 第1図 258− O2プラスマ爪理路閂 O2フ〉棉’Je%!’5 とJidtYヤ4■φH」
尤4第2図 本臼社のユ程1図 第4図 3:金@膜 4:旨版4属吸 5!レジスト 6:レジ又ドパターン 7;薯G築バダーン
1(a) to 1(f) are process cross-sectional views for explaining one embodiment of the wiring pattern forming method of the present invention, and FIG. Characteristic diagram showing the relationship between plasma treatment and reflectance, Figure 3 (a)
3(f) to 3(f) are views showing SEM observation images of the upper surface of the resist pattern when the refractory metal in the same example was subjected to 02 plasma treatment and nitric acid treatment, and FIG. 4(a) to
FIG. 4(e) is a process cross-sectional view for explaining the conventional wiring pattern forming method, and FIGS. 5(a) to 5(f) show high melting point metal films in the conventional wiring pattern forming method. FIG. 3 is a diagram showing a top SEM observation image of a resist pattern without surface treatment. ■...Base substrate, 2...Insulating film, 3...Metal film,
4... High melting point metal film, 5... Resist, 6... Resist pattern, 7... Wiring pattern. $ Seimei process trace diagram 1 258- O2 plasma claw road lock O2fu〉Cotton 'Je%! '5 and JidtYya4■φH'
尤4 fig. 2 Honususha's Yu-cho 1 fig. 4 fig. 3: gold@membrane 4: Uma version 4 genus suction 5! Resist 6: Resist pattern 7;

Claims (1)

【特許請求の範囲】 (a)下地基板上に絶縁膜を介して配線用の金属膜を形
成する工程と、 (b)上記金属膜上に反射防止用の高融点金属膜の形成
後、この高融点金属の表面をO_2プラズマと硝酸によ
る表面処理を行う工程と、 (c)レジストを塗布して所定のパターンの露光と現像
を行うことによりレジストパターンを形成した後、エッ
チングを行って配線パターンを形成する工程と、 よりなる配線パターンの形成方法。
[Claims] (a) A step of forming a metal film for wiring on a base substrate via an insulating film; (b) After forming a high melting point metal film for anti-reflection on the metal film, (c) Applying a resist, exposing and developing a predetermined pattern to form a resist pattern, and then etching to form a wiring pattern. A method for forming a wiring pattern, comprising: a process for forming a wiring pattern;
JP3732390A 1990-02-20 1990-02-20 Formation of wiring pattern Pending JPH03241745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3732390A JPH03241745A (en) 1990-02-20 1990-02-20 Formation of wiring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3732390A JPH03241745A (en) 1990-02-20 1990-02-20 Formation of wiring pattern

Publications (1)

Publication Number Publication Date
JPH03241745A true JPH03241745A (en) 1991-10-28

Family

ID=12494451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3732390A Pending JPH03241745A (en) 1990-02-20 1990-02-20 Formation of wiring pattern

Country Status (1)

Country Link
JP (1) JPH03241745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010165821A (en) * 2009-01-15 2010-07-29 Seiko Npc Corp Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010165821A (en) * 2009-01-15 2010-07-29 Seiko Npc Corp Method of manufacturing semiconductor device

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