JPH03241321A - Production of nonlinear element - Google Patents

Production of nonlinear element

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Publication number
JPH03241321A
JPH03241321A JP2038748A JP3874890A JPH03241321A JP H03241321 A JPH03241321 A JP H03241321A JP 2038748 A JP2038748 A JP 2038748A JP 3874890 A JP3874890 A JP 3874890A JP H03241321 A JPH03241321 A JP H03241321A
Authority
JP
Japan
Prior art keywords
layer
conductor layer
nonlinear
lower conductor
polishing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2038748A
Other languages
Japanese (ja)
Inventor
Satoru Miyashita
悟 宮下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2038748A priority Critical patent/JPH03241321A/en
Publication of JPH03241321A publication Critical patent/JPH03241321A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain the element which has a nonlinear electric conductivity inducing layer having moldability at and under ordinary temp. and atm. pressure and excellent controllability and operates stably by relieving the edge steps of a lower conductor layer formed on a glass substrate, then forming the nonlinear electric conductivity inducing layer and an upper conductor layer. CONSTITUTION:An insulating resin is applied at nearly the same thickness as the thickness of the lower conductor layer 12. The resin on at least the lower conductor layer 12 is removed by polishing. Alumina powder which is polishing powder is completely removed by washing with running water, ultrasonic cleaning in a neutral detergent and rinsing with pure water to expose the step-relieved insulating layer 15 remaining after the polishing after the edge steps of the lower conductor layer 12 formed on the glass substrate 11 are relieved in such a manner the nonlinear electric conductivity inducting layer 13 and the upper conductor layer 14 are formed. The element which has the nonlinear electric conductivity inducing layer 13 having the moldability at and under ordinary temp. and atm. pressure and the excellent controllability and operates stably is obtd. in this way.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、電流電圧特性が非線形である非線形素子に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonlinear element having nonlinear current-voltage characteristics.

[従来の技術] 従来の非線形素子としては、Siなどの半導体ウェハー
や、ガラスや単結晶等の上に形成した薄膜状の半導体を
用いていた。また、導電体−絶縁体一導電体構造(以後
本明細書ではMIM構造と呼ぶ)を持つものも実用化さ
れている。
[Prior Art] Conventional nonlinear elements have used semiconductor wafers such as Si, or thin film semiconductors formed on glass, single crystal, or the like. Further, devices having a conductor-insulator-conductor structure (hereinafter referred to as an MIM structure in this specification) have also been put into practical use.

[発明が解決しようとする課題] しかし、半導体を用いた従来の非線形素子では、非線形
素子のベースとなるべき半導体の形成にも、CVDなど
のスループットが良くない高価な真空装置を必要とする
ため、特に大きな面積を必要とする用途のためには、非
常に高価なものとなってしまうという課題があった。
[Problem to be solved by the invention] However, conventional nonlinear elements using semiconductors require expensive vacuum equipment such as CVD with poor throughput to form the semiconductor that is the base of the nonlinear element. However, there is a problem in that it becomes extremely expensive, especially for applications that require a large area.

また、M工M構造を持つ非線形素子も、非線形電気伝導
誘起層をタンタルなどの金属の1III極酸化で形成す
るため、陽極酸化膜自体の特性を変化させることは困難
で、素子特性はほとんど膜厚と素子面積のみで制御を行
うしかない。このため、素子特性(例えば○N/○FF
比とONE流、素子容it)をバランス良く制御するの
は難しい。
In addition, in nonlinear elements with an M/M structure, the nonlinear electrical conduction inducing layer is formed by 1III anodic oxidation of a metal such as tantalum, so it is difficult to change the characteristics of the anodic oxide film itself, and the device characteristics are almost the same as the film. The only way to control it is by controlling the thickness and element area. For this reason, element characteristics (for example, ○N/○FF
It is difficult to control the ratio, ONE current, and element capacity in a well-balanced manner.

一方、少なくとも高分子絶縁体と、高分子絶縁体内に分
散した導電体または半導体から構成されている非線形電
気伝導誘起層を用いると、原理的には制御性に優れた非
線形素子が得られるものの、ガラス基板上に形成した下
部導電体層のエツジ段差箇所において、非線形電気伝導
誘起層が薄くなって短絡電流が流れたり、上部導電体層
が断線するなど信頼性や安定性に欠けていた。
On the other hand, although a nonlinear element with excellent controllability can be obtained in principle by using a nonlinear electrical conduction inducing layer composed of at least a polymeric insulator and a conductor or semiconductor dispersed within the polymeric insulator, The nonlinear electrical conduction inducing layer becomes thinner at the edge step portions of the lower conductor layer formed on the glass substrate, causing short-circuit currents to flow, and the upper conductor layer to break, resulting in a lack of reliability and stability.

本発明では、常温常圧で形成可能かつ制御性に優れた非
線形電気伝導誘起層をもち、安定に作動する非線形素子
の製造法を提供することによって上記の課題を解決する
ことを目的とするものである。
The present invention aims to solve the above problems by providing a method for manufacturing a nonlinear element that can be formed at room temperature and pressure, has a nonlinear electrical conduction inducing layer with excellent controllability, and operates stably. It is.

C課題を解決するための手段] 本発明の非線形素子の製造法は、導電体に挟持された非
線形電気伝導誘起層が少なくとも高分子絶縁体と、高分
子絶縁体内に分散した導電体または半導体から構成され
ている非線形素子において、ガラス基板上に形成した下
部導電体層のエツジ段差を以下に示す工程で緩和した後
、非線形電気伝導誘起層及び上部導電体層を形成するこ
とを特徴とする。
Means for Solving Problem C] The method for manufacturing a nonlinear element of the present invention is such that the nonlinear electrical conduction inducing layer sandwiched between conductors is made of at least a polymeric insulator and a conductor or semiconductor dispersed within the polymeric insulator. This nonlinear element is characterized in that the edge step of the lower conductor layer formed on the glass substrate is relaxed in the following steps, and then the nonlinear electrical conduction inducing layer and the upper conductor layer are formed.

a)絶縁性の樹脂を、下部導電体層を形成した基板上に
塗布する工程。
a) A step of applying an insulating resin onto the substrate on which the lower conductive layer is formed.

b)研磨により、少なくとも下部導電体層上の樹脂を削
除する工程。
b) A step of removing at least the resin on the lower conductor layer by polishing.

C)基板に付着した研磨材を除去する工程。C) Step of removing abrasive material attached to the substrate.

[実施例] 以下、実施例により本発明の詳細を示す。[Example] Hereinafter, the details of the present invention will be shown by examples.

(実施例1) 第1図に、本実施例において製造する非線形素子の断面
の概念を示す。また、第2図に下部導電体層のエツジ段
差を緩和しない従来の素子の概念を示す。
(Example 1) FIG. 1 shows the concept of a cross section of a nonlinear element manufactured in this example. Further, FIG. 2 shows the concept of a conventional element in which the edge step of the lower conductor layer is not alleviated.

基板としては、表面を光学研磨したパイレックスガラス
11を用い、金属などの導電体膜をスパッターもしくは
蒸着で形成し、フォトエツチングによってパターンを形
成して下部導電体12としたものを用い、素子面積が2
0μm角となるように20μm幅にバターニングした。
The substrate used was Pyrex glass 11 with an optically polished surface, a conductor film made of metal or the like was formed by sputtering or vapor deposition, and a pattern was formed by photoetching to form the lower conductor 12. 2
It was patterned to a width of 20 μm so that it was 0 μm square.

第3図に、下部導電体層の段差を緩和する工程を模式的
に示す。
FIG. 3 schematically shows a step of alleviating the step difference in the lower conductor layer.

第3図(a)は、絶縁性の樹脂を下部導電体層とほぼ同
じ厚みに塗布した断面図である。樹脂はポリアミック酸
をスピンコードで塗布した後、焼成によりポリイミドと
した。
FIG. 3(a) is a cross-sectional view in which an insulating resin is applied to approximately the same thickness as the lower conductor layer. The resin was made into polyimide by applying polyamic acid with a spin cord and then baking it.

第3図(b)は、研磨により、少なくとも下部導電体層
上の樹脂を削除した断面図である。研磨材としてはプラ
スチック研磨用の発泡ウレタンバットとアルミナ粉末を
用い、定盤上で回転させることにより、樹脂層のみを削
除した。
FIG. 3(b) is a cross-sectional view in which at least the resin on the lower conductor layer is removed by polishing. A foamed urethane bat for plastic polishing and alumina powder were used as polishing materials, and only the resin layer was removed by rotating them on a surface plate.

第3図(C)は、基板に付着した研磨材を除去した断面
図である。研磨粉であるアルミナ粉末を流水洗浄、中性
洗剤中の超音波洗浄、純水すすぎにより完全に除去し、
研磨で残った、段差緩和絶縁体層15を露出させた。
FIG. 3(C) is a cross-sectional view with the abrasive material attached to the substrate removed. Alumina powder, which is polishing powder, is completely removed by washing with running water, ultrasonic washing in a neutral detergent, and rinsing with pure water.
The step-reducing insulator layer 15 remaining after polishing was exposed.

非線形電気伝導層に用いる高分子絶縁体は、ポリフマル
酸ジイソプロピル(以下本明細書ではPDiPFと略記
する)をもちいた。PDiPFなどのポリフマル酸エス
テル類を単独で用いた場合、数百オングストロームまで
の非常に薄いスピンコード膜でも、電気絶縁特性の優れ
た薄膜が得られる材料として知られている。 (重厚ら
、高分子討論会予稿集Vol。39. No、 8 (
19891p、 2563 )PDiPFは再沈澱によ
って精製したのち、精製したクロロホルムに溶解してP
DiPF溶液を作った。更に、有機半導体であるオキサ
ジアゾール誘導体(2,5−Bis (4−dieth
ylaminophenyll−L 3+40zadi
axole)を溶解して、均一溶液とした。この溶液を
、0. 5−μmのフィルターに通してごみを除去し、
原料溶液とした。混合の比率は、目的とする非線形素子
のON電流値および/または0FFtIl流値と膜強度
の兼ね合いで決められる。
The polymer insulator used for the nonlinear electrically conductive layer was diisopropyl polyfumarate (hereinafter abbreviated as PDiPF). When a polyfumarate ester such as PDiPF is used alone, it is known as a material that allows a thin film with excellent electrical insulation properties to be obtained even in a very thin spin cord film of up to several hundred angstroms. (Jetatsu et al., Polymer Symposium Proceedings Vol. 39. No. 8 (
19891p, 2563) After PDiPF was purified by reprecipitation, it was dissolved in purified chloroform to dissolve PDiPF.
A DiPF solution was made. Furthermore, oxadiazole derivatives (2,5-Bis (4-dieth
ylaminophenyl-L 3+40zadi
axole) was dissolved to form a homogeneous solution. This solution was mixed with 0. Pass through a 5-μm filter to remove dust.
This was used as a raw material solution. The mixing ratio is determined based on the desired ON current value and/or 0FFtIl current value of the nonlinear element and film strength.

この原料溶液を前述の基板上に、スピンコーターで所定
の膜厚となるように回転数と時間を制御して塗布し、非
線形電気伝導誘起層13とした。
This raw material solution was coated onto the above-mentioned substrate using a spin coater while controlling the rotation speed and time to obtain a predetermined film thickness, thereby forming the nonlinear electrical conduction inducing layer 13.

こうして形成した非線形電気伝導誘起層の上に、金属を
スパッターもしくは蒸着で形成し、20μm幅に上部導
電体14をフォトエツチングでパターン形成して、MI
M構造の非線形素子が得られた。
On the thus formed nonlinear electrical conduction inducing layer, a metal is formed by sputtering or vapor deposition, and an upper conductor 14 is patterned to a width of 20 μm by photoetching.
A nonlinear element with M structure was obtained.

こうして得られた非線形素子はショートも断線も発生せ
ず、暗所で電流電圧特性を測定すると、第4図のように
安定した非線形性を長時間示すことを確認した。このと
き、上部導電体と下部導電体に異なるものを用いると、
電圧の印加方向によって特性が非対称になる場合もあっ
た。
The thus obtained nonlinear element did not cause any short circuit or disconnection, and when its current-voltage characteristics were measured in a dark place, it was confirmed that it exhibited stable nonlinearity for a long time as shown in FIG. 4. At this time, if different materials are used for the upper conductor and lower conductor,
In some cases, the characteristics became asymmetric depending on the direction of voltage application.

この非線形素子は、ON電圧を9ボルト、OFF電圧を
lボルトとしたときに、電流の0N10FF比が4桁以
上とれる。
This nonlinear element has a current 0N10FF ratio of more than four digits when the ON voltage is 9 volts and the OFF voltage is 1 volt.

(実施例2) 実施例1と同様にして下部導電体層を形成した基板に、
シロキサン系の樹脂を下部電極の約2倍の厚みに塗布し
た。下部導電体層上の樹脂がほぼ全て削除できる条件で
ソフト研磨を行い、研磨材を洗浄で除去し、下部導電体
層および段差緩和絶縁体層を露出させた。
(Example 2) On a substrate on which a lower conductor layer was formed in the same manner as in Example 1,
A siloxane resin was applied to a thickness approximately twice that of the lower electrode. Soft polishing was performed under conditions that allowed almost all of the resin on the lower conductor layer to be removed, and the abrasive was removed by cleaning, exposing the lower conductor layer and the step-reducing insulator layer.

次に実施例1と同様にして精製し、フィルターを通した
PDiPF溶液に亜鉛塩を溶解させた。
Next, the zinc salt was dissolved in a PDiPF solution purified and filtered in the same manner as in Example 1.

この溶液に硫化水素ガスを通気して、硫化亜鉛の微粒子
を生成させた。できた分散液を水洗することで余分な亜
鉛塩を除去し、導電体粒子が分散された原料分散液を得
た。この原料分散液を用いて、前述の下部導電体及び段
差緩和絶縁体層を形成した基板に塗布して非線形電気伝
導誘起層とし、上部導電体の形成を行って、非線形素子
を作成した。
Hydrogen sulfide gas was bubbled through this solution to generate fine particles of zinc sulfide. Excess zinc salt was removed by washing the resulting dispersion with water to obtain a raw material dispersion in which conductor particles were dispersed. This raw material dispersion liquid was applied to the substrate on which the lower conductor and step-reducing insulator layer described above were formed to form a nonlinear electrical conduction inducing layer, and an upper conductor was formed to produce a nonlinear element.

このようにして作成された非線形素子は、ショートも断
線も発生せず、暗所で電流電圧特性を測定すると、実施
例1と同様に安定した非線形性を長時間示した。また、
下部導電体層上に痕跡程度の樹脂が残存していても、電
流電圧特性に差異はほとんど認められなかった。
The nonlinear element produced in this manner did not cause any short circuit or disconnection, and when its current-voltage characteristics were measured in a dark place, it exhibited stable nonlinearity for a long time as in Example 1. Also,
Even if a trace of resin remained on the lower conductor layer, almost no difference was observed in the current-voltage characteristics.

(実施例3) 実施例1と同様にして下部導電体層を形成した基板に、
エステル系樹脂を下部導電体層の約半分の厚みに塗布し
た。下部導電体層上の樹脂が全て削除できる条件でソフ
ト研磨を行い、研磨材を洗浄で除去し、下部導電体層お
よび段差緩和絶縁体層を露出させた。
(Example 3) On a substrate on which a lower conductor layer was formed in the same manner as in Example 1,
The ester resin was applied to about half the thickness of the lower conductor layer. Soft polishing was performed under conditions that allowed all of the resin on the lower conductor layer to be removed, and the abrasive was removed by washing to expose the lower conductor layer and the step-reducing insulator layer.

次に実施例1と同様にしてn製ししたPDiPFとポリ
(3−へキシルチオフェン)を塩化炭素に溶解し、0.
5μmのフィルターを通して原料溶液を得た。この原料
溶液を用いて、前述の下部導電体及び段差緩和絶縁体層
を形成した基板に塗布して非線形電気伝導誘起層とし、
金属酸化物をスパッターもしくは蒸着で形成し上部導電
体層とした。
Next, PDiPF prepared in the same manner as in Example 1 and poly(3-hexylthiophene) were dissolved in carbon chloride.
A raw material solution was obtained through a 5 μm filter. Using this raw material solution, apply it to the substrate on which the aforementioned lower conductor and step-reducing insulator layer are formed to form a nonlinear electrical conduction inducing layer,
A metal oxide was formed by sputtering or vapor deposition to form the upper conductor layer.

このようにして作成された非線形素子は、ショートも断
線も発生せず、暗所で電流電圧特性を測定すると、実施
例1と同様に安定した非線形性を長時間示した。
The nonlinear element produced in this manner did not cause any short circuit or disconnection, and when its current-voltage characteristics were measured in a dark place, it exhibited stable nonlinearity for a long time as in Example 1.

以上実施例を述べたが、本発明は以上の実施例のみに限
定されるものではない。絶縁性樹脂や上下導電体、高分
子絶縁体のみならず、分散させる導電体や半導体も種々
考えられる。
Although the embodiments have been described above, the present invention is not limited only to the above embodiments. In addition to insulating resins, upper and lower conductors, and polymer insulators, various conductors and semiconductors to be dispersed can also be considered.

本発明の非線形素子は、これを用いたアクティブマトリ
ックス表示装置や光シヤツターなどの電気光学装置、温
度、湿度、光、ガス、溶液などのセンサーなどにも広く
応用が可能である。
The nonlinear element of the present invention can be widely applied to active matrix display devices, electro-optical devices such as optical shutters, and sensors for temperature, humidity, light, gas, solutions, etc., using the same.

[発明の効果] 以上述べたように、本発明によれば常温常圧で形成可能
で、かつ制御性に優れた非線形電気伝導誘起層をもち、
安定に作動する非線形素子の製造法を提供することによ
って安価で優れた非線形素子を作成することが可能にな
る。本発明の非線形素子は素子構造が簡単な上、非線形
電気伝導誘起層の形成が容易なため、特に大きな面積の
ものを作成するのには有利である。
[Effects of the Invention] As described above, the present invention has a nonlinear electrical conduction inducing layer that can be formed at room temperature and pressure and has excellent controllability.
By providing a method for manufacturing a nonlinear element that operates stably, it becomes possible to create an inexpensive and excellent nonlinear element. The nonlinear element of the present invention has a simple element structure and the nonlinear electrical conduction inducing layer can be easily formed, so it is particularly advantageous for manufacturing a large area element.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の実施例1で作成した、非線形素子の
概念を表す断面図である。 第2図は、従来の下部導電体層のエツジ段差を緩和しな
い非線形素子の概念を表す断面図である。 第3図は、下部導電体層のエツジ段差を緩和する工程を
模式的に表わす断面図である。 (a)は、絶縁性樹脂
を下部導電体層上に塗布する工程の断面図であり、 (
b)は、研磨により下部導電体層上の樹脂を削除する工
程の断面図であり、 (C)は、基板に付着した研磨材
を除去する工程の断面図である。 第4図は、本発明の実施例1で作成した、非線形素子の
電流電圧特性を表す図である。 15・・・・・・・・・・段差緩和絶縁体層31・・・
・・・・・−・・研磨材 41・・・・・・・・・・電流電圧特性曲線板
FIG. 1 is a cross-sectional view showing the concept of a nonlinear element created in Example 1 of the present invention. FIG. 2 is a cross-sectional view showing the concept of a conventional nonlinear element that does not alleviate the edge step of the lower conductor layer. FIG. 3 is a cross-sectional view schematically showing the step of reducing the edge step of the lower conductor layer. (a) is a cross-sectional view of the process of applying insulating resin onto the lower conductor layer;
(b) is a cross-sectional view of the step of removing the resin on the lower conductor layer by polishing, and (C) is a cross-sectional view of the step of removing the abrasive material adhering to the substrate. FIG. 4 is a diagram showing current-voltage characteristics of a nonlinear element created in Example 1 of the present invention. 15... Step difference mitigation insulator layer 31...
・・・・・−・・Abrasive material 41・・・・・・・・Current-voltage characteristic curve plate

Claims (1)

【特許請求の範囲】 導電体に挟持された非線形電気伝導誘起層が少なくとも
高分子絶縁体と、高分子絶縁体内に分散した導電体また
は半導体から構成されている非線形素子において、ガラ
ス基板上に形成した下部導電体層のエッジ段差を以下に
示す工程で緩和した後、非線形電気伝導誘起層及び上部
導電体層を形成することを特徴とする非線形素子の製造
法。 a)絶縁性の樹脂を、下部導電体層を形成した基板上に
塗布する工程。 b)研磨により、少なくとも下部導電体層上の樹脂を削
除する工程。 c)基板に付着した研磨材を除去する工程。
[Claims] A nonlinear element in which a nonlinear electrical conduction inducing layer sandwiched between conductors is composed of at least a polymeric insulator and a conductor or semiconductor dispersed within the polymeric insulator, formed on a glass substrate. 1. A method for manufacturing a nonlinear element, characterized in that a nonlinear electrical conduction inducing layer and an upper conductive layer are formed after the edge step of the lower conductive layer is reduced by the steps described below. a) A step of applying an insulating resin onto the substrate on which the lower conductive layer is formed. b) A step of removing at least the resin on the lower conductor layer by polishing. c) Step of removing abrasive material attached to the substrate.
JP2038748A 1990-02-20 1990-02-20 Production of nonlinear element Pending JPH03241321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2038748A JPH03241321A (en) 1990-02-20 1990-02-20 Production of nonlinear element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2038748A JPH03241321A (en) 1990-02-20 1990-02-20 Production of nonlinear element

Publications (1)

Publication Number Publication Date
JPH03241321A true JPH03241321A (en) 1991-10-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2038748A Pending JPH03241321A (en) 1990-02-20 1990-02-20 Production of nonlinear element

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Country Link
JP (1) JPH03241321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007116029A (en) * 2005-10-24 2007-05-10 Mitsubishi Electric Corp Wiring board, method for manufacturing same, and display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007116029A (en) * 2005-10-24 2007-05-10 Mitsubishi Electric Corp Wiring board, method for manufacturing same, and display device

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