JPH0323948U - - Google Patents
Info
- Publication number
- JPH0323948U JPH0323948U JP8548689U JP8548689U JPH0323948U JP H0323948 U JPH0323948 U JP H0323948U JP 8548689 U JP8548689 U JP 8548689U JP 8548689 U JP8548689 U JP 8548689U JP H0323948 U JPH0323948 U JP H0323948U
- Authority
- JP
- Japan
- Prior art keywords
- input
- logic circuit
- internal logic
- output buffer
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8548689U JPH0323948U (en:Method) | 1989-07-19 | 1989-07-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8548689U JPH0323948U (en:Method) | 1989-07-19 | 1989-07-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0323948U true JPH0323948U (en:Method) | 1991-03-12 |
Family
ID=31634648
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8548689U Pending JPH0323948U (en:Method) | 1989-07-19 | 1989-07-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0323948U (en:Method) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0711783A (ja) * | 1993-06-28 | 1995-01-13 | Kawamoto Kunichika | 住 宅 |
-
1989
- 1989-07-19 JP JP8548689U patent/JPH0323948U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0711783A (ja) * | 1993-06-28 | 1995-01-13 | Kawamoto Kunichika | 住 宅 |