JPH03239338A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03239338A JPH03239338A JP3385990A JP3385990A JPH03239338A JP H03239338 A JPH03239338 A JP H03239338A JP 3385990 A JP3385990 A JP 3385990A JP 3385990 A JP3385990 A JP 3385990A JP H03239338 A JPH03239338 A JP H03239338A
- Authority
- JP
- Japan
- Prior art keywords
- package
- chip
- holes
- wiring board
- smaller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 7
- 238000005219 brazing Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
テープオートメイテッドボンディング方式を用いてリー
ドをポンディングしたチップをパッケージに搭載した半
導体装置に関し、
アウターリードボンディングの容易化を目的とし、
テープオートメイテッドボンディング方式を用いてリー
ドをポンディングしたチップをパッケージに搭載して成
る半導体装置において、−上記チップとパッケージとの
間に、該パッケージより小型で且つ多数のスルーホール
を有するバッファー配線基板を設け、該バッファー配線
基板のスルーホールに前記チップのリードを接続し、さ
らに該スルーホールをパッケージのリードピンに接続し
た配線パターンに接続して成るように構成する。[Detailed Description of the Invention] [Summary] Regarding a semiconductor device in which a chip with leads bonded using the tape automated bonding method is mounted in a package, the tape automated bonding method is used for the purpose of facilitating outer lead bonding. In a semiconductor device comprising a chip mounted on a package with leads bonded thereto, a buffer wiring board is provided between the chip and the package, which is smaller than the package and has a large number of through holes; The leads of the chip are connected to through holes in the substrate, and the through holes are connected to wiring patterns connected to lead pins of the package.
本発明は、Ｔ Ａ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔｅ
ｄ Ｂｏｎｄｉｎｇ）方式を用いてリードをボンディン
グしたチップをパッケージに搭載した半導体装置に関す
る。The present invention is based on TAB (Tape Automate).
The present invention relates to a semiconductor device in which a chip with leads bonded using the D Bonding method is mounted in a package.
ＬＳＩが高集積化されるに伴ってチップサイズの増大及
び■／○の数の増加が著しく、それに伴ってパッケージ
サイズの増大及びリードピンも多ビン化、高密度化され
て来ており、この高密度化されたリードビンに対応する
リードパターンとチップに接続した内リードを均一にボ
ンディングすることは困難となっている。As LSIs become more highly integrated, the chip size and the number of ■/○ have increased significantly.As a result, the package size has also increased and lead pins have become more numerous and denser. It has become difficult to uniformly bond the lead patterns corresponding to the densely packed lead bins and the inner leads connected to the chip.
第３図は従来のＴＡＢ技術を用いて大チップを多ピンパ
ラゲージに組立実装した半導体装置を示す図である。同
図において１は＾１２０３又はｕ２Ｎよりなる基板２に
多数（３００〜５００）のり−ドビン３が植設されたパ
ッケージ、４はチップ、５は一端をデツプ４にバンブ６
を介してＴＡＢ方式でボンディングされたリード（Ｃｕ
素材にＳｎめっき又はＡ ｕめっきされたもの）であり
、他端をパッケージ１のリードビン３に接続した配線パ
ターン７にボンディングツールを用いて熱圧着されてい
る。FIG. 3 is a diagram showing a semiconductor device in which a large chip is assembled and mounted on a multi-pin parallel gauge using the conventional TAB technique. In the same figure, 1 is a package in which a large number (300 to 500) glue-dobins 3 are implanted on a substrate 2 made of ^1203 or u2N, 4 is a chip, and 5 is a package with one end connected to a depth 4 with a bump 6.
Leads (Cu
The other end is bonded to the wiring pattern 7 connected to the lead bin 3 of the package 1 by thermocompression using a bonding tool.
また８は表面をＮｉ／Ａｕでめっきしたコバールよりな
る封止キャップ、９は熱伝導性の良い金属を用いたヒー
トシンクであり、チップ４の裏面及び封止キャンプの上
面にろう材で接合しチップ４を封止している。１０はヒ
ートシンク９に接続されたＡ６等の放熱フィンである。Further, 8 is a sealing cap made of Kovar whose surface is plated with Ni/Au, and 9 is a heat sink using a metal with good thermal conductivity, which is bonded to the back surface of the chip 4 and the top surface of the sealing camp with a brazing material. 4 is sealed. 10 is a heat dissipation fin such as A6 connected to the heat sink 9.
上記従来の半導体装置では、ＬＳＩの高集積化に伴うチ
ップサイズの増大及びＩ １０数の増加、それに伴うパ
ッケージの多ビン化、パッケージサイズの増大という状
況の下で、次のような問題が生している。In the above-mentioned conventional semiconductor devices, the following problems have arisen as the chip size and I10 number have increased due to higher integration of LSIs, and as a result, the number of bins in the package has increased and the package size has increased. are doing.
（１）多ビンパッケージはリードビン３の植設密度が犬
であるため、ガイド治具と加熱治具を兼ねたアウターリ
ードボンディング用支持治具を変形のない様に作成する
ことば困難である。(1) Since the lead bins 3 of the multi-bin package have a high density, it is difficult to create an outer lead bonding support jig that serves as both a guide jig and a heating jig without deformation.
（２）その結果パッケージの均一加熱が困難で良好かつ
均一なアウターリードボンディングが用難である。又そ
れを補なう為にアウターリードボンディング用ヒートツ
ールの温度分布のコントロールが必要となり、高精度、
高価格等ツールへの負荷が大となる。(2) As a result, it is difficult to uniformly heat the package, making it difficult to perform good and uniform outer lead bonding. In addition, to compensate for this, it is necessary to control the temperature distribution of the heat tool for outer lead bonding, resulting in high precision and
The cost is high and the load on the tool is heavy.
本発明は上記従来の問題点に鑑み、アラターリ（３）
−ドボンディングを容易化した半導体装置を提供するこ
とを目的とする。SUMMARY OF THE INVENTION In view of the above conventional problems, it is an object of the present invention to provide a semiconductor device that facilitates bonding.
上記目的を達成するために本発明の半導体装置では、テ
ープオートメイテッドボンディング方式を用いてリード
５をボンディングしたチ・ンプ４をパッケージ１に搭載
して成る半導体装置において、上記チップ４とパッケー
ジ１との間に、該パッケージ１より小型で且つ多数のス
ルーホール１２を有するバッファー配線基板１１を設け
、該バッファー配線基板１１のスルーホール１２に前記
チ・ンブ４のリード５を接続し、さらに該スルーホール
をパッケージ１のリードビン３に接続した配線パターン
７に接続して戒ることを特徴とする。In order to achieve the above object, in a semiconductor device of the present invention, the chip 4 and the package 1 are mounted on the package 1, and the chip 4 is bonded to the leads 5 using a tape automated bonding method. A buffer wiring board 11 that is smaller than the package 1 and has a large number of through holes 12 is provided between the buffer wiring board 11, and the leads 5 of the channel 4 are connected to the through holes 12 of the buffer wiring board 11. It is characterized in that the hole is connected to the wiring pattern 7 connected to the lead bin 3 of the package 1.
バ・ンファー配線基板１１はパッケージ１より小型かつ
平板状である為アウターリードホンディング用支持治具
及びヒートツールも小型となり、精度（４）
良く作成することができ、またバッファー配線基板は熱
容量的にもパッケージＩより小さく均一な加熱ができる
ため、良好なアウターリードボンディングが可能となる
。Since the buffer wiring board 11 is smaller and flat than the package 1, the supporting jig and heat tool for outer lead bonding are also smaller and can be manufactured with good accuracy (4). Since heating is smaller and more uniform than in Package I, good outer lead bonding is possible.
第１図は本発明の実施例を示す図であり、（ａ）は断面
図、（ｂ）はバッファー配線基板の一部を示す平面図で
ある。FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) is a cross-sectional view, and (b) is a plan view showing a part of a buffer wiring board.
同図において、■はパッケージであり、該パッケージは
Ａ ｆｆ ２０３又は１ｌｆｆｉＮよりなる基板２の下
面に多数（３００〜５００）のリードビン３が植設され
、上面には該リードビン３にそれぞれ接続した配線パタ
ーン７が形成されている。また４はチップであり、該チ
ップはバンブ６を介してリード５ （Ｃｕ素材にＳｎめ
っき）の一端がＴＡＢ方式でボンディングされている。In the figure, ■ is a package, and this package has a large number (300 to 500) of lead bins 3 planted on the bottom surface of a substrate 2 made of A ff 203 or 1lffiN, and wiring connected to each of the lead bins 3 on the top surface. A pattern 7 is formed. Further, 4 is a chip, to which one end of a lead 5 (Cu material plated with Sn) is bonded via a bump 6 using the TAB method.
１１は本発明の要点であるバッファー配線基板であり、
該バッファー配線基板１１は１２０３又はｉＮ等でパッ
ケージ１よりも小形に形成され、多数のスルーホール１
２が設けられ（５）
（６）
ており、１面には所定のボンディングパターン１３が形
成されている。そして該バッファー配線基板１１はパッ
ケージ１とチップ４との間に配置され、その上面のボン
ディングパターン１３にチップ４のリード５がアウター
リードボンディングされ、下面ではそのスルーホール１
２がパッケージ１上の配線パターン７に半田等の低融点
ろう材１４で接合されている。なおバッファー配線基板
１１としてΔ１２０３を用いた場合には、その配線基板
内の配線を多層配線としても良い。またスルーホール１
２はアウターリードボンディングパターンの密度により
第１図（ｂ）に示すように千鳥形等の配置にしても良い
。また第１図（ａ）において、８はＮ ｉ ／ Ａ ｕ
めっきしたコバールよりなる封止キャップで、その下面
を封止材でパッケージ１に接合され、上面にはチップ４
と共にろう材により放熱フィン１０を有するヒートシン
ク９が接合されチップ４を気密封止している。11 is a buffer wiring board which is the main point of the present invention;
The buffer wiring board 11 is made of 1203 or iN or the like and is smaller than the package 1, and has a large number of through holes 1.
2 are provided (5) (6), and a predetermined bonding pattern 13 is formed on one surface. The buffer wiring board 11 is arranged between the package 1 and the chip 4, and the leads 5 of the chip 4 are outer lead bonded to the bonding pattern 13 on the upper surface, and the through holes 1
2 is bonded to the wiring pattern 7 on the package 1 with a low melting point brazing material 14 such as solder. Note that when Δ1203 is used as the buffer wiring board 11, the wiring within the wiring board may be multilayer wiring. Also through hole 1
2 may be arranged in a staggered pattern or the like as shown in FIG. 1(b) depending on the density of the outer lead bonding pattern. Moreover, in FIG. 1(a), 8 is N i / A u
A sealing cap made of plated Kovar, whose bottom surface is bonded to the package 1 with a sealing material, and whose top surface has a chip 4.
A heat sink 9 having heat dissipating fins 10 is also bonded with a brazing material to hermetically seal the chip 4.
以上の本実施例は次のような順序で組立てられる。The above embodiment is assembled in the following order.
（１）先ずチップ４にＴＡＢ方式を用いてインナーリー
ドボンディングを行なった後リード５をキャリアテープ
から力・ン卜する。(1) First, inner lead bonding is performed on the chip 4 using the TAB method, and then the leads 5 are pulled out from the carrier tape.
（２）次に上記のり一ド５がボンディングされたチップ
４をバッファー配線基板１１にアウターリードボンディ
ングヒートツールを用いてボンディングを行なう。(2) Next, the chip 4 to which the glue 5 has been bonded is bonded to the buffer wiring board 11 using an outer lead bonding heat tool.
（３）次にバッファー配線基板１１とパッケージ１上の
配線パターン７を低融点ろう材１４を用いて接合する。(3) Next, the buffer wiring board 11 and the wiring pattern 7 on the package 1 are bonded using a low melting point brazing material 14.
（４）最後に封止材を用いてパッケージ１を封止キャッ
プ８で封止し、かつチップ背面とヒートシンク９をろう
材を用いて気密封止する。(4) Finally, the package 1 is sealed with a sealing cap 8 using a sealing material, and the back surface of the chip and the heat sink 9 are hermetically sealed using a brazing material.
このように構成された本実施例は、バッファー配線基板
１１が小型かつ平板状に形成されているため、アウター
リードボンディング用支持治具及びヒートツールが精度
良く作製でき、またバッファー配線基板１１が小型であ
るため熱容量もパッケージ１に比し小さくかつ均一加熱
が可能な為アウターリードボンディングが容易となり、
また均一に（７）
（８）
ボンディングすることができる。従って従来品ではチッ
プサイズが１３ｍｍ角まで、パッケージのり−ドビンが
５００本程度までであったものが、本実施例ではチップ
サイズが２０ｍｍ角程度まで、リードビンが１０００本
程度まで可能となり、大チップで且つ多ピンパツケージ
でのＴＡＢ実装範囲の拡大が可能となる。In this embodiment configured as described above, the buffer wiring board 11 is small and formed in a flat plate shape, so the support jig and heat tool for outer lead bonding can be manufactured with high precision, and the buffer wiring board 11 is small and flat. Therefore, the heat capacity is smaller than that of package 1, and uniform heating is possible, making outer lead bonding easier.
Furthermore, it is possible to uniformly (7) (8) bond. Therefore, whereas with conventional products, the chip size can be up to 13 mm square and the number of package glue bins can be up to about 500, in this embodiment, the chip size can be up to about 20 mm square and the number of lead bins can be up to about 1000, making it possible to handle large chips. Moreover, it is possible to expand the TAB mounting range in multi-pin packages.
第２図は本発明の他の実施例を示す図である。FIG. 2 is a diagram showing another embodiment of the present invention.
同図において第１図と同一部分は同一符号を付して示し
た。In this figure, the same parts as in FIG. 1 are designated by the same reference numerals.
本実施例は基本的には前実施例と同様であり、異なると
ころは、チップ４の表裏を逆にして、その裏面をチップ
接着剤（Ａｇガラス又はＡｇポリイミドペースト等）１
５でパンファー配線基板１１に接着されていることと、
ヒートシンク及び放熱フィンを除去したことである。This example is basically the same as the previous example, except that the chip 4 is turned upside down and the back side is coated with a chip adhesive (Ag glass or Ag polyimide paste, etc.).
5 is bonded to the breadboard wiring board 11;
The heat sink and heat dissipation fins were removed.
本実施例は前実施例に対し冷却効果が異なるのみにて、
他の作用効果は前実施例と同様である。This example differs from the previous example only in the cooling effect.
Other effects are the same as in the previous embodiment.
以上説明した様に、本発明によれば、チップとパッケー
ジとの間の電気的接続にパッケージより小さいバッファ
ー配線基板を用いることにより、アウターリードボンデ
ィング用支持治具及びヒートツールも小型で良いため精
度良く且つ安価に作成でき、またパッケージに比し熱容
量も小さいため均一加熱ができ容易且つ良好なアウター
リードボンディングができる。これにより大チップ多ビ
ンパッケージでのＴＡＢ実装範囲の拡大に寄与すること
ができる。As explained above, according to the present invention, by using a buffer wiring board smaller than the package for electrical connection between the chip and the package, the support jig and heat tool for outer lead bonding can also be small and accurate. It can be manufactured well and at low cost, and has a smaller heat capacity than a package, so it can be heated uniformly and can perform easy and good outer lead bonding. This can contribute to expanding the range of TAB mounting in large chip multi-bin packages.
第１図は本発明の実施例を示す図、
第２図は本発明の他の実施例を示す図、第３図は従来の
ＴＡＢ技術を用いて大チップを多ビンパッケージに明文
実装した半導体装置を示す図である。
図において、
１はパッケージ、
２は基板、
（９）
（１０）
３はリードピン、
４はチップ、
５はリード、
６はバンプ、
７は配線パターン、
８は封止キャップ、
９はヒートシンク、
１０は放熱フィン、
１１はバッファー配線基板、
１２はスルーホール、
１３はボンディングパターン、
１４はろう材
を示す。
（１１）Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing another embodiment of the invention, and Fig. 3 is a semiconductor in which a large chip is clearly mounted in a multi-bin package using conventional TAB technology. It is a figure showing an apparatus. In the figure, 1 is a package, 2 is a substrate, (9) (10) 3 is a lead pin, 4 is a chip, 5 is a lead, 6 is a bump, 7 is a wiring pattern, 8 is a sealing cap, 9 is a heat sink, 10 is a 11 is a buffer wiring board, 12 is a through hole, 13 is a bonding pattern, and 14 is a brazing material. (11)
Claims (1)
リード（５）をボンディングしたチップ（４）をパッケ
ージ（１）に搭載して成る半導体装置において、 上記チップ（４）とパッケージ（１）との間に、該パッ
ケージ（１）より小型で且つ多数のスルーホール（１２
）を有するバッファー配線基板（１１）を設け、該バッ
ファー配線基板（１１）のスルーホール（１２）に前記
チップ（４）のリードを接続し、さらに該スルーホール
（１２）をパッケージ（１）のリードピン（３）に接続
した配線パターン（７）に接続して成ることを特徴とす
る半導体装置。[Claims] 1. A semiconductor device comprising a chip (4) to which leads (5) are bonded using a tape automated bonding method is mounted on a package (1), wherein the chip (4) and the package (1) are mounted on a package (1). ) is smaller than the package (1) and has a larger number of through holes (12
) is provided, the leads of the chip (4) are connected to the through holes (12) of the buffer wiring board (11), and the through holes (12) are connected to the through holes (12) of the package (1). A semiconductor device characterized in that it is connected to a wiring pattern (7) connected to a lead pin (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3385990A JPH03239338A (en) | 1990-02-16 | 1990-02-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3385990A JPH03239338A (en) | 1990-02-16 | 1990-02-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03239338A true JPH03239338A (en) | 1991-10-24 |
Family
ID=12398232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3385990A Pending JPH03239338A (en) | 1990-02-16 | 1990-02-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03239338A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6334936A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Mounting structure of tape carrier |
-
1990
- 1990-02-16 JP JP3385990A patent/JPH03239338A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6334936A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Mounting structure of tape carrier |
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