JPH03239336A - Lateral transistor - Google Patents

Abstract

PURPOSE:To substantially increase the base concentration of a parasitic transistor and to reduce a parasitic effect by a method wherein a high-concentration diffusion region is arranged in a well region so as to surround an emitter region and a collector region. CONSTITUTION:A high-concentration diffusion-layer region 25 which surrounds an emitter region 23 and a collector region 24 is arranged in a well region 22. Consequently, the base concentration of a parasitic transistor using the well region 22 as a base can be increased substantially as compared with a case where the diffusionlayer region 25 does not exist or a case where the diffusion-layer region 25 is arranged only in one part around the emitter region 23 and the collector region 24. Thereby, the current-amplification factor of the parasitic transistor can be reduced. When the diffusion-layer region 25 is arranged by ensuring a prescribed separation distance from the emitter and the collector regions 23, 24, it does not influence a junction capacity of the emitter and collector regions 23, 24.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a lateral transistor, and more particularly to a lateral transistor using an MO8 field effect transistor structure.

(b) By converting the conventional MO8ii field-effect transistor into a lateral type bipolar transistor, it is possible to provide a high-performance lateral transistor using 0MO8 technology, and also to use such a lateral transistor in a low-noise amplifier circuit,
For example, 'IEEE J
OURNAL OF SOLID-5TAIE CIR
CUITS, VOL, 5C-18, NO, June 31983, pages 273 to 279.

FIG. 5 is a plan view showing an NPN lateral transistor using a conventional MOS field effect transistor structure, and FIG. 4 is a cross-sectional view taken along the line Y--Y in FIG.

In the figure, a P-type well region (2) formed on an N-type silicon substrate (1) (hereinafter referred to as the substrate) and an N+-type emitter region ( 3) and a collector region (4), a P+ type diffusion layer region <5> disposed adjacent to the emitter region (3) or the collector region (4), and an emitter region (
The well region (2) between the collector region (4) and the gate electrode layer (7) is connected to the gate electrode layer (7) via the 5i02 film (6), and the substrate bias is applied to the substrate (1) except for the well region (2). An N+ type diffusion layer region (8>) is arranged.

=1 contact holes (9) are opened in the emitter region (3), the collector region (4), and the diffusion layer regions (5), (8), aluminum is deposited, and the emitter electrodes (lO), Collector electrode (11), base electrode (1
2>, the substrate bias electrode (13) is taken out, and the substrate bias electrode (13) is extended to the power supply voltage V cc
It is connected to the.

Further, the gate electrode B (7>) is connected to the ground potential, and the MOS field effect transistor whose source and drain are the emitter region (3) and collector region (4) is in an off state.

With the structure as described above, M using 0MO3 technology
The OS field effect transistor is converted into a lateral type bipolar transistor.

In this case, the channel region of the MOS field effect transistor is the substantial base region (
14), and by miniaturizing the gate electrode layer (7),
The length (so-called base width) of this base region (14) is also reduced, making it possible to provide a lateral transistor T with a high current amplification factor (hereinafter referred to as hfe).

However, in general 0MO3 technology, the well region (2
Since a P+ buried layer is not formed in 〉, a parasitic NPN formed by the emitter region (3) or collector region
) There was a problem in that the hfe of the lateral transistor T1 decreased due to the parasitic effects of the transistors T t and T s and the variation increased.

As a conventional technique related to this problem, by increasing the impurity concentration of the well region (2), the parasitic transistor T
The collector resistances R1 and R2 of the parasitic transistors T* and Ts can be increased by using techniques to reduce the hfe of the parasitic transistors T* and T-, or by ensuring a large distance between the well region <2> and the diffusion layer region (8). As a result, there is a technique for reducing the hfe of the parasitic transistor.

(c) Problems to be solved by the invention By the way, increasing the impurity concentration in the well region (2) leads to an increase in the junction capacitance between the emitter region (3) and collector region (4) and the well region (2). At the same time, hfe of the lateral transistor T is also lowered, resulting in a disadvantage that the operating speed of the lateral transistor T1 is lowered.

In addition, ensuring the distance between the double region (2) and the diffusion layer region (8) is large enough to sufficiently reduce the hfe of T*, Ta increases the pattern area and significantly reduces the integration density. The disadvantage was that it deteriorated.

The present invention was created in view of the problems of the prior art, and aims to provide a lateral transistor that reduces the effects of parasitic transistors and does not cause a significant decrease in operating speed or integration density. shall be.

(d) Means for Solving the Problems The structure of the lateral transistor of the present invention includes a low concentration well region of the opposite conductivity type formed on a semiconductor substrate of the -conductivity type, and MO3 field effects 1 to 1 on the surface of the well region. In a lateral transistor having a transistor structure and in which the source and drain regions of the MOS field effect transistor structure are configured as emitter and collector regions, the well region is provided with a high concentration of opposite conductivity type surrounding the emitter region and the collector region. It is characterized by that a diffusion layer region is arranged.

(f) Effects According to the present invention, since the high concentration diffusion layer region surrounding the emitter region and the collector region is arranged in the well region, the base concentration of the parasitic transistor based on the well region is This can be substantially higher than when there is no region or when the diffusion layer region is arranged only partially around the emitter region and the collector region.

Therefore, it is possible to reduce the hfe of the parasitic transistor compared to the conventional one, and by arranging the diffusion layer region with a predetermined distance from the emitter/collector region, the hfe of the emitter/collector region can be reduced. It does not affect the junction capacitance.

Further, since the pattern area occupied by the diffusion layer region may be relatively small, there is an advantage that the integration density does not decrease significantly.

(F) Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a plan view showing an N P N l-synister according to an embodiment of the present invention, and FIG. 1 is a cross-sectional view taken along line XX in FIG. 2.

In the figure, a P-type low concentration well region (22) is formed on an N-type silicon substrate (21) (hereinafter referred to as a "double substrate").
) (Boron concentration: 5 x 10” atoms/
cm 3~5X 10” atoms/cTn3
, diffusion depth: 3 μm to 5 μm) N+ type emitter region (23) and collector region (24) spaced apart on the surface of the well region (22); P+ type diffusion layer region (25) arranged to surround (Boron concentration: I x 10
"atoms, /CT13~IXlO"'ato
ms/cm3, depth of diffusion 10.5 μm ~ 2 μm)
There is.

A gate electrode layer (27) made of phosphorus-doped polysilicon formed via a 5i0a film (26) is provided in the well region (22) between the emitter region (23) and the lucator region (24). , An N+ type diffusion layer region (28) for substrate bias is arranged on the substrate (21) except for the well region (22).

On the substrate (21) except for each of the above-mentioned diffusion layer regions, there is a Loc
An os oxide film (29) is formed, and the toc.

An interlayer insulating film (30) is formed on the entire surface of the substrate (21) on the S oxide film (29) or the diffusion layer region.

The emitter region (23), collector region (24), and diffusion layer regions (25) and (28) have contact holes (3
1) is opened and aluminum is deposited, respectively.
The emitter electrode (32), collector electrode (33), base electrode (34), and substrate bias electrode (35) are taken out, and the substrate bias electrode (35) is extended and connected to the power supply voltage V.C. There is.

Further, the gate electrode layer (27) Lt is connected to the ground potential, and when operating with the emitter grounded, the emitter electrode (32) is further connected to the ground potential.

The configuration described above provides an NPN lateral transistor T.

A feature of the present invention is that the well region (22) has a diffusion layer region <25> arranged so as to surround the emitter region (23) and the collector region (24),
This makes it possible to increase the base concentration of the parasitic NPN) transistor T6, reduce hfa, and reduce its parasitic effect.

Here, the diffusion depth of the diffusion layer region (25) is defined as the well region (
If it is formed as deep as the diffusion depth of 22), hfe4 of the parasitic NPN transistors Ts and T- can be made very small.

In addition, by increasing the distance between the well region (22) and the diffusion layer region (28) to 15 μm or more, the collector resistances Rs and Ra are increased, and the synergistic effect with the effect of the diffusion layer region (25) further reduces parasitic transistor h
FE can be reduced.

Although this embodiment relates to an NPN lateral transistor, it goes without saying that it can be applied to a PNP transistor.

Next, an example in which the lateral transistor of the present invention is applied to a bandgap reference bias generation circuit will be described with reference to FIG.

In the figure, P-channel transistors T of the same size
, , T, resistors Rg, Re, and temperature compensation transistors T o , T +. (T, which has twice the size of T), the reference voltage V ref =V
BII+ Rs/ R5XkT/ qX Ink(k
; Boltzmann constant, T: absolute temperature, q: electron charge, ■
, is known to be given by the base-emitter voltage of the transistor T.

T,,T, of this circuit. When the conventional lateral transistor described above is used, there is a problem in that Vref has a large dependence on the power supply voltage (V, c) and Vref has large variations due to the effect of the parasitic transistor. The lateral transistor of the present invention is T,,T,. If applied to
It is possible to provide a bandgap reference bias generation circuit with reduced variation in ref.

Here, if T16 is configured by arranging in parallel transistors having the same size and shape as T, it is possible to further reduce variations in V ref due to differences in shape.

(G) As described in detail, according to the present invention, a high concentration diffusion region is arranged in the wool region so as to surround the emitter region and the collector region, so that the base concentration of the parasitic transistor is It is possible to fabricate a lateral transistor with substantially increased parasitic effects and reduced parasitic effects.

Further, since the lateral transistor of the present invention can be formed together with an MO3 field effect transistor on the same substrate using CMOS process technology, it can be applied to 0M08 circuits such as band gap type reference bias generation circuits.

Furthermore, since the lateral transistor of the present invention has reduced parasitic effects, when applied to an 0M03 circuit -I+, the -6 path characteristic can be improved by 1 compared to the conventional transistor.

4. Bell of the drawing! ij, ;su2 Explanation The first figure is a sectional view taken along the line XX in the AA diagram, and the second factor is a plan view showing the NPN lateral transistor according to the embodiment of the present invention. A circuit diagram of a Bandgi ＼ Tsuzu type reference bias circuit according to an embodiment of the present invention, FIG. 4 is a cross-sectional view taken along the Y-Y cutting line in FIG. 5, and FIG. There is a ``I7-view'' C shown.

]2

Claims (4)

[Claims] (1) a low-concentration well region of an opposite conductivity type formed on a semiconductor substrate of one conductivity type; an emitter region and a collector region of one conductivity type spaced apart from each other on a surface of the well region; and the emitter region and collector region of one conductivity type. In the lateral transistor, the gate electrode layer is provided on the surface of the well region with an insulating film interposed between the well region and the well region. A lateral transistor characterized in that a diffusion layer region is arranged. (2) The lateral transistor according to claim 1, further comprising a wiring layer connecting the emitter region and the gate electrode to a ground potential or a power supply potential. (3) A base electrode layer connected to the diffusion layer region is provided in claim 1 or claim 2.
Lateral transistor as described in section. (4) The lateral transistor according to claim 1, 2 or 3, wherein the insulating film is made of silicon dioxide, and the gate electrode layer is made of conductive polysilicon.