JPH03237759A - Manufacture of integrated circuit having hbt - Google Patents

Abstract

PURPOSE:To reduce a distance of a step between an element isolating region and an upper part of a heterojunction bipolar transistor(HBT) structure part and to flatten the surface of an insulating film layer by removing a crystal structure of the element isolating region leaving a part of a non-operating part of the HBT structure in the element isolating region for isolating elements of the HBT from each other. CONSTITUTION:HBT element structure part 20a, 20b are provided to a compound semiconductor metal 1. An isolating region 21 for isolating is provided between the element structure parts 20a, 20b. HBT multilayer structure between a crystal structure part 9 and an operating part of the HBT structure parts 20a, 20b is removed as far as a sub-collector layer 2. An insulating layer 10 is buried in a clearance between the part whose HBT multilayer structure is removed and the crystal structure part 9 so that the crystal structure part 9 is covered with the insulating layer 10. An electrode wiring layer 8 is formed on the insulating film layer 10. In this way, an upper surface of the insulating film layer 10 formed on the crystal structure part 9 is flattened by providing the crystal structure part 9 to an element isolating region 21. It is possible to carry out fine patterning of the electrode wiring layer 8 thereafter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing an integrated circuit having a heterojunction bipolar transistor therein.

[Conventional technology]

In recent years, with advances in crystal growth technology for ■-V group compound semiconductors, circuits having heterojunction bipolar transistors (hereinafter referred to as HBTs) are being realized, although they are still at the research stage. This heterojunction bipolar transistor has been the mainstay of ultrahigh-speed ICs for some time.
It outperforms the t bipolar transistor (hereinafter referred to as 5iBT) in terms of high speed and high driving ability, and is attracting attention as a driving element for future ICs.

Then, in order to incorporate this HBT into an integrated circuit, the SBT
We utilize microfabrication technology, equipment, and mass production technology that achieves high yields. Element isolation is required between HBT elements formed in an integrated circuit, and conventionally this element isolation has been performed by removing the entire crystal part of a single HBT other than the operating part. Then, an insulating film layer and an electrical wiring layer are formed thereon to form an integrated circuit.

[Problem to be solved by the invention]

In the above element isolation method, as shown in FIG.
b and these element isolation portions 33, that is, H
It is necessary to overcome a step H corresponding to the thickness needle of the BT crystal. On the other hand, with photolithography technology, which is a basic element of microfabrication technology, it is difficult to transfer a fine pattern to areas with steps. This is because, in a currently used stepper using the reduction projection exposure method, the theoretical relationship between the resolution R and the depth of focus δ is as follows. In order to obtain high resolution as shown in these equations, it is necessary to increase the numerical aperture and shorten the wavelength of the light used. However, in this case, the depth of focus becomes shallow, and as a result, it becomes difficult to transfer a fine pattern to a portion with large steps.

R-0,61λ/N,A.

δ-λ/2 (NAo) where λ: wavelength, NAo: numerical aperture (-nsin
a), n: refractive index of the medium, α: angle of incident light.

From this point of view, it has been difficult to apply fine photolithography technology to conventional element isolation methods that produce a step difference estimated to be 1.5 μm or more.

An object of the present invention is to provide a method for manufacturing an integrated circuit that solves the above problems.

[Means to solve the problem]

A method for manufacturing an integrated circuit according to the present invention includes, on a compound semiconductor substrate, a subcollector layer and a collector layer having a first conductivity type, a base layer having a second conductivity type, and an emitter layer having a first conductivity type. a step of sequentially forming a heterojunction bipolar transistor stacked structure, an element isolation region forming step of forming an element isolation region of a heterojunction bipolar transistor structure constituted by the stacked structure, and a step of forming an insulating film in the element isolation region. In the device isolation region forming step, a crystal structure portion constituted by at least a part of the heterojunction bipolar transistor stacked structure is placed at a position spaced apart from the heterojunction bipolar transistor structure portion of the device isolation region. , and at least the upper layer of the sub-collector layer of the stacked structure in the region between the heterojunction bipolar transistor structure and the crystal structure is removed.

[Effect]

In the present invention, the crystal structure of the element isolation region is removed while leaving a part of the inactive portion of the HBT structure in the element isolation region for isolating each HBT element in an integrated circuit. Therefore, when an insulating film layer is formed in the element isolation region,
The step distance between the element isolation region and the upper part of the HBT structure is reduced, and the surface of the insulating film layer can be flattened. This makes it possible to apply fine photolithography technology.

〔Example〕

Embodiments according to the present invention will be described below with reference to the drawings.

Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.

FIG. 1 shows a partial cross section of the main part of an integrated circuit manufactured by an integrated circuit manufacturing method according to an embodiment of the present invention.

As shown in FIG. 1, in the integrated circuit, an HBT element structure section 20a120b is provided on a compound semiconductor substrate 1,
These element structures 20a.

An element isolation region 21 for element isolation is provided between the elements 20b. This HBT element structure section 20a.

20b, the sub-collector layer 2 is similar to the conventional HBT.
, a collector layer 3, a base layer 4, an emitter layer 5, and an emitter cap layer 6 are formed in this order from the substrate 1 side, and on the sub-collector layer 2, base layer 4, and emitter cap layer 6, collector electrodes 2a, A base electrode 4a and an emitter electrode 5a are formed.

On the other hand, in the element isolation region 21 of the substrate 1, the H
Layers 2b, 3b corresponding to the sub-collector layer 2, collector layer 3, base layer 4, emitter layer 5, and emitter cap layer 6, respectively, which constitute the BT element structures 20a, 20b.
, 4b, 5b, and 6b, the crystal structure part 9 is
It is provided as shown in FIG. The crystal structure portion 9 is configured in a pyramid shape such that the width of each layer becomes narrower as the distance from the semiconductor substrate increases. The crystal structure portion 9 and the HBT structure portions 20a, 2
The HBT laminated structure between the active part 0b and the sub-collector layer 2 has been removed. Then, an insulating layer 10 is buried in the gap between the removed portion of the HBTfa layer structure and the crystal structure part 9 so as to cover the crystal structure part 9, and an electrode wiring layer is formed on the insulating film layer 10. 8 is formed. Here, by providing the crystal structure portion 9 in the element isolation region 21, the upper surface of the insulating film layer 1o formed thereon is flattened. Thereafter, it becomes possible to perform fine patterning of the electrode wiring layer 8, and as a result, an integrated circuit having HBTs integrated at high density can be realized.

Next, a method for manufacturing an integrated circuit, which is an embodiment of the present invention, will be described with reference to FIG.

First, as shown in FIG. 2(a), a compound semiconductor substrate 1
A plurality of HBT structures 20a and 20b (two cases will be explained in this embodiment) are formed on the element isolation region 2.
1 shows a state in which a crystal structure portion 9 is formed.

The method for forming the HBT structures 20a and 20b on the compound semiconductor substrate 1 is the same as the conventional method for manufacturing an integrated circuit including a plurality of HBTs, so a detailed explanation will be omitted. When removing a portion of the HBT laminated structure in the element isolation region 21 that corresponds to a non-operating part as an HBT, this crystal structure portion 9 removes a portion of each layer of the HBT laminated structure on the element isolation region 21. It can be formed by etching it so that it remains. This is done by changing the mask pattern on the photomask used when forming element isolation regions by selectively removing each layer in the portion corresponding to the non-active portion, so that part of the non-active portion is not removed. Each layer of the operating part may be removed.

Next, an insulating layer 14 made of polyimide, for example, is applied to cover the tops of the HBT structures 20a and 20b, and the crystal structure 9 and H
It is formed over the entire surface of the substrate 1 to a thickness such that the bottom of the recess 14a114b formed corresponding to the step between the BT structures 20a and 20b is located at a higher position than the emitter electrode 5a of the HBT structure. This state is shown in FIG. 2(b). As shown in FIG. 2(b), by leaving the crystal structure portion 9 in the element isolation region 21, the upper surface of the insulating layer 14 is planarized compared to the case where the crystal structure portion 9 is not present.

Next, a photoresist is applied to the entire surface of the substrate 1.

In this state, the depression 14 of the insulating layer 14 shown in FIG. 2(b)
It also flows into the layers a and 14b, and the upper surface of the formed layer 15 is further flattened. This state is shown in FIG. 2(c).

Next, the layer 15 and the insulating layer 14 on the entire surface of the substrate 1 are etched back to expose the upper part of the emitter electrode 5a. This state is shown in FIG. 2(d). As shown in FIG. 2(d), the upper surface of the insulating film layer 1o formed by etching back is further planarized.

Next, an electric wiring layer 8 is placed on this flattened insulating film layer 1o.
form. This state is shown in FIG. 2(e). By using such a method, there are fewer steps on the surface of the insulating film layer 1o on which the electrical wiring layer 8 is formed, and a fine pattern can be easily formed using conventional photolithography technology. This enables high-density integration of integrated circuits having HBTs.

Next, the principle of reducing the level difference and flattening the structure by providing the crystal structure portion 9 using the polyimide coating method as described above will be explained with reference to FIG.

FIG. 3(a) shows the shape of the polyimide film formed on the step, and FIG. 3(b) shows the relationship between the distance from the step and the amount of step in the changed state of FIG. 3(a). . As shown in FIGS. 3(a) and 3(b), when there is a step on the substrate on which the polyimide film is formed, the surface of the polyimide film changes smoothly as it moves away from the step position. A predetermined distance, the beam in Figure 3(a). If you move further away, it will no longer change. Then, as shown in FIG. 3(a), the distance increases. In the following case, for example, in the case of Ll, the amount of change is Hl, and the amount of change is smaller than the step difference IHo. In this way, when a polyimide film is formed in a region with steps, by reducing the distance between the step portions, it is possible to reduce the steps on the upper surface of the polyimide film applied there. In the conventional case, since nothing was provided in the element isolation part, the distance between H87, that is, the distance corresponding to the distance from the step part in the above explanation, exceeded Lo, and the electric wiring layer 16 formed thereon had to overcome a step Ho between the HBT structure line portion and the substrate surface of the element isolation portion. As a result, it has been difficult to form desired fine wiring due to the depth of focus of photolithography described above. On the other hand, in this embodiment, since the insulator 9 is provided, the distance between the HBT structure line edge 9 and the HBT structure line edge 9 will be explained first. As a result, the upper surface of the film formed thereon can be flattened.

The present invention is not limited to the above embodiments, and various modifications may be made.

Specifically, in the above embodiment, the crystal structure portion 9 and the HB
Ions of an inert species may be implanted into the substrate between the T structure portions 20a and 20b to increase the resistance of the boundary portion and enhance the element isolation effect. This state is shown in Figure 4(a).
Shown below. In this FIG. 4(a), inert species ions are implanted into the region 16.

It is also preferable to implant ions of an inert species into the crystal structure of the above embodiment to increase the resistance. This state is shown in FIG. 4(b). In FIG. 4(b), ions of inert species are implanted into the crystal structure portion 9a.

Further, in the above embodiment, the insulating film layer is planarized by etching back, but it is also possible to form the electrical wiring layer 8 directly on the insulating film layer in the state shown in FIG. 2(b). , the surface of the insulating film layer can be planarized compared to the conventional case.

Furthermore, in the above embodiment, when removing a portion of the HBT stacked structure in the element isolation region, all layers up to the sub-collector layer are removed. The sub-collector layer left between the structural lines may be ion-implanted with an inert species to increase the resistance and provide element isolation function. This state is shown in Figure 4(c).
Shown below.

In FIG. 4(c), inert species ions are implanted into region 17.

Further, in the above embodiment, the crystal structure portion 9 includes portions corresponding to each layer of the HBT laminated structure, but it is not necessary to consist of all the layers in this way. It suffices if it is composed of layers corresponding to layers above the sub-collector layer in the laminated structure. FIG. 4(d) shows a case in which the crystal structure part 9 is composed of a sub-collector layer and a base layer, that is, a case in which the emitter layer and the emitter cap layer are removed when forming the crystal structure part 9. FIG. 4(e) shows the case in which all the particles have been removed. Even in such a case, the insulating film layer 10 can be planarized.

Further, in the manufacturing method of the above embodiment, the photoresist film 15 and the insulating layer 14 are etched back until the emitter electrode is exposed, but this etchback is stopped before the upper part of the emitter electrode 5a is exposed. An electrical wiring layer 8 may be formed thereon. This example is shown in Figure 4(f).
Shown below. In this case, since the electrical wiring layer 8 can have a large distance from the HBT structure, the wiring capacitance can be reduced and the speed of the integrated circuit can be increased.

Note that one or more of the above modified methods may be combined.

〔Effect of the invention〕

In the method for manufacturing an integrated circuit having an HBT of the present invention, the surface of the insulating film layer on which the electrical wiring layer of the integrated circuit is formed can be formed flat, and as a result, the HBT can be formed in high density on the semiconductor substrate. realizable.

In the integrated circuit having the HBT manufactured by the method of the present invention, the surface of the insulating film layer on which the electrical wiring layer of the integrated circuit is formed is flattened, so that conventional photolithography technology cannot be used. By using this, high integration becomes possible.

one base electrode, 4... base layer, 5... emitter layer, 5
a... Emitter electrode, 6... Emitter cap layer,
8... Electric wiring layer, 9... Crystal structure part, 9a...
Inactivated crystal structure portion, 10...insulating film layer, 14
...Insulation 8 layers, 14a, 14b--Insulation INIHI
Hollow, 15... Photoresist film, 20a, 20
b... HBT structure portion, 21... element isolation region.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a partial cross-sectional structure of an integrated circuit obtained by a manufacturing method according to an embodiment of the present invention, and FIG. Figure 3 is a diagram showing a cross section of an integrated circuit during the process, and Figure 3 is a diagram explaining the principle of planarization according to the present invention. FIG. 34 is a diagram showing a partial cross-sectional structure of an integrated circuit according to another embodiment of the present invention, and FIG.
The figure is a diagram showing a partial cross-sectional structure of a conventional integrated circuit.

Claims (1)

[Claims] A subcollector layer and a collector layer having a first conductivity type, a base layer having a second conductivity type, and an emitter layer having a first conductivity type are sequentially formed on a compound semiconductor substrate. , a step of forming a heterojunction bipolar transistor stacked structure; an element isolation region forming step of forming an element isolation region of the heterojunction bipolar transistor structure constituted by the stacked structure; and forming an insulating film layer in the element isolation region. In the device isolation region forming step, a crystal structure portion made up of at least a part of the heterojunction bipolar transistor stacked structure is placed in a position spaced apart from the heterojunction bipolar transistor structure portion of the device isolation region. A method for manufacturing an integrated circuit having an HBT, wherein at least an upper layer of the sub-collector layer of the stacked structure in a region between the heterojunction bipolar transistor structure and the crystal structure is removed.