JPH03237527A - Data storage device - Google Patents

Abstract

PURPOSE:To facilitate the control according to new control information by holding a function by which the contents of a preservation memory, which is not used at the time of executing the control operation, can be written and read by a host controller. CONSTITUTION:At the time of normal operation, a power control circuit 4 receives the application instruction from a host controller and the power source of the controller is turn on, then a power on completion signal 21 is made to 'H'. A memory control circuit 3 confirms the 'high' of the signal 21 to write all of contents of an electrically programmable non-volatile memory circuit 1 in a memory circuit 2 and sets a control start signal 29 to 'H'. A sequence control circuit 5 performs the control based on contents of the memory circuit 2. When new control information is sent from a host device to the power control circuit 4, the memory control circuit 3 writes it in the memory 1. When a control information read instruction is sent from the host device to the power control circuit 4, the memory control circuit 3 reads out control information from the memory circuit 1 and sends it to the host device through the power control circuit 4.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data storage device, and more particularly to a data storage device having a sequence control circuit unit that controls various sequence operations according to sequence control information stored in a memory circuit. Regarding equipment.

[Conventional technology]

Conventional data storage devices are composed of extremely complex hardware circuits that use a large number of logic circuit elements to control various complex sequential operations, but in recent years, control information has been stored in memory circuits. Microprogram type sequence control circuits that perform various controls based on the control information have come to be used. In data storage devices that employ such microprogram-based sequence control circuits, if the control method changes, it is necessary to change the control circuit itself, as in the case of hardware-based sequence control circuits. Not, but because it changes the contents of the memory circuit,
Memory circuit needs to be replaced. However, in recent years, the amount of data processed and stored in computer systems is enormous, and the number of data storage devices connected to one central processing unit may reach a considerable number. In such a case, it is very difficult to replace the memory circuit for sequence control of all the pig storage devices, and there is a drawback that it requires a large amount of cost.

[Problem to be solved by the invention]

The problem to be solved by the present invention, in other words, the object of the present invention is to overcome the drawbacks of the conventional data storage device as described above, and to enable the data storage device to be stored while the device is in operation at the site of use without removing the memory circuit. An object of the present invention is to provide a data storage device that can quickly rewrite the contents of a memory circuit by easily rewriting the contents of an electrically rewritable nonvolatile memory circuit.

[Means to solve the problem]

The data storage device of the present invention includes a sequence control circuit unit that controls various sequence operations, an electrically rewritable nonvolatile memory circuit that retains control information of the sequence control circuit unit when power is turned off, and a sequence control circuit unit that controls various sequence operations. A memory circuit for reading out control information when the control circuit unit executes various control operations, and a memory circuit for storing control information in advance in the electrically rewritable nonvolatile memory circuit according to a power-on completion signal sent from the power supply control circuit unit. transfer control information to the memory circuit, and after the transfer is completed, connect the address signal, data signal, and read control signal of the memory circuit to the memory address signal, memory data signal, and memory read control signal of the sequence control circuit section, respectively. , has an interface signal for instructing the sequence control circuit unit to start control, and for exchanging various commands and data with the sequence control circuit unit using serial data; It has interface signals for exchanging various commands and data using serial data between the memory control circuit unit that rewrites and reads the contents of arbitrary addresses in the rewritable nonvolatile memory circuit and the host control device. The power is turned on in response to a power-on command sent from the host controller via the interface signal, and upon completion of power-on, a power-on completion signal is sent to the memory control circuit, and the power is turned off in response to a power-off command. and transmits the power-on status, abnormality in the power supply, and status of the cooling fan in response to a status read command, and when an abnormality in the power supply and abnormality in the cooling fan is detected, reports the abnormality to the higher-level control device. The memory of the electrically rewritable non-volatile memory circuit is sent to the memory control circuit section by a sequence control information rewrite command from the higher-level control device and a memory address and new sequence control information sent following the command. An address sequence control information rewrite command and new sequence control information are sent, and the sequence control information read command from the upper control device and a memory address sent following that command are used to send the memory control circuit unit to the memory control circuit section. sending a sequence control information read command for the memory address of the rewritable nonvolatile memory circuit;
and a power supply control circuit unit that sends sequence control information stored in the memory address sent from the memory control circuit unit to the upper control device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the electrically rewritable nonvolatile memory circuit (storage memory) ■ represents the storage memory address signal 11.
The memory circuit (execution memory) 2 is connected to the memory control circuit 3 via the storage memory data signal 12 and the storage memory control signal 13, while the memory circuit (execution memory) 2 is connected to the execution memory address signal 14 and the execution memory data signal 15. and the memory control circuit 3 via the execution memory control signal 16.
It is connected to the.

The power supply control circuit 4 is connected to a host control device (not shown) via a serial data input signal 17, a serial data input control signal 18, a serial pig output signal 19, and a serial data output control signal 20, and receives a power-on completion signal 21. and is connected to the memory control circuit 3 by a control data input signal 22, a control data input control signal 23, a control data output signal 24, and a control data output control signal 25.

The sequence control circuit unit 5 is connected to a lower-order controlled unit (not shown) by a control instruction signal 30 and a control state signal 31, and receives a memory address signal 26, a memory data signal 27, a memory control signal 28, and a control start instruction signal 29. It is connected to the memory control circuit 3 via the memory control circuit 3.

FIG. 2 is a block diagram showing details of the memory control circuit of the embodiment of FIG. 1.

In FIG. 2, the control data input/output control circuit 301 is
It is connected to the power supply control circuit 4 via a control data input/output signal 22 , a control data input control signal 23 , a control data output signal 24 , and a control data output control signal 25 . It is also connected to the command judgment execution control circuit 302 via a control signal 310.

The command judgment execution control circuit 302 receives the power-on completion signal 21
The power supply control circuit 4 and the control start instruction signal 29
The sequence control circuit section 5 is connected to the storage memory 1 by the storage memory address signal 11, the storage memory data signal 12, and the storage memory control signal 13.
is connected to. In addition, storage memory address signal 1
1, storage memory data signal 12, and execution memory control signal 311, memory address signal switching circuit 303 and memory data signal switching circuit 304, respectively.
and a memory control signal switching circuit 305, and are connected to a memory address signal switching circuit 303, a memory data signal switching circuit 304, and a memory control signal switching circuit 305 by a signal switching signal 312.

The memory address signal switching circuit 303 uses the execution memory address signal 14 and the memory data signal switching circuit 3
04 is connected to the execution memory 2 by the execution memory data signal 15, and the memory control signal switching circuit 305 is connected to the execution memory 2 by the execution memory control signal 16. It is connected to the sequence control circuit section 5 by.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

During normal operation, the power supply control circuit 4 receives a power-on command from the host control device using the serial data input signal 17 and the serial data input control signal 18 to power on the device, and then sends a power-on completion signal 21 to a high level (“H
”>.The memory control circuit 3 outputs the power-on completion signal 2.
1 becomes "H", it is determined that power-on is completed, and the signal switching signal 312 is set to "H". When the signal switching signal 312 becomes H'', the memory address signal switching circuit 303 connects the storage memory address signal 11 and the execution memory address signal 14, and the memory data signal switching circuit 304 connects the storage memory data signal 12 and the execution memory address signal 14. The memory control signal switching circuit 305 connects the memory data signal 15 for execution, and the memory control signal switching circuit 305 connects the memory control signal 311 for execution and the memory control signal 16 for execution.Next, the instruction judgment execution control port lit! Address “O” is set in the address signal 11, and the storage memory control signal 13
The contents of the storage memory 1 are read out via the storage memory data signal 12. At this time, the execution memory address signal 14 also receives the address “0” from the storage memory address signal 11 via the memory address signal switching circuit 303.
°A street address has been set. Next, the previously read data is outputted from the storage memory data signal 12 to the execution memory data signal 15 via the memory data signal switching circuit 304, and from the execution memory control signal 311 to the memory control signal switching circuit 305 and the execution memory data signal 15. Writing is performed in the execution memory 2 via the memory control signal 16. Thereafter, the same operation is repeated by incrementing the address by "1" until it reaches the last memory address.

After all the contents of the storage memory 1 are written to the execution memory 2 by this operation, when the signal switching signal 312 is set to low level (“L”), the memory address signal switching circuit 303 switches between the memory address signal 26 and the execution memory 2. and the memory address signal 14 for the memory data signal switching circuit 30.
4 is a memory data signal 27 and an execution memory data signal 1
The memory control signal switching circuit 305 connects the memory control signal 28 and the execution memory control signal 16. Next, the control start instruction signal 29 is set to "H". When the two control start instruction signals become "H", the sequence control circuit section 5 starts the sequence control from the execution memory 2 using the memory address signal 26 and the memory control signal 28. The information is read through the memory data signal 27 and executed in the execution memory 2.
The next control means is determined based on the sequence control information read from the controller and the content of the control status signal 31 read from the lower-order controlled section, and control instructions are given to the lower-order controlled section via the control instruction signal 30. .

Next, the operation when rewriting the contents of the storage memory 1 from the higher-level control device will be described.

As mentioned above, after the contents of the storage memory 1 are transferred to the execution memory 2, the storage memory address signal 11 is
The storage memory data signal 12 and the execution memory control signal 311 are disconnected from the execution memory address signal 14, the execution memory data signal 15, and the execution memory control signal 16, respectively. Therefore, the storage memory 1 is essentially in an unused state. That is, even if the contents of the storage memory 1 are rewritten in this state, the operation of the device will not be affected. Therefore, at this time, the contents of the storage memory 1 are rewritten.

When the host control device sends a sequence control information rewriting command, a rewriting address, and new sequence control information to the power supply control circuit 4 via the serial data input signal 17 under the control of the serial data input control signal 18, the power supply control circuit 4 receives the control data. It is controlled by an input control signal 23 and sends a sequence control information rewrite command, a rewrite address, and new sequence control information to the control data input/output control circuit 301 of the memory control circuit 3 via the control data input signal 22 . Control data human output control circuit 30
1 sequentially sends the received information to the command judgment execution control circuit 302 using a control signal 310. The command determination execution control circuit 302 determines that the information input by the control signal 310 is a memory IF change command, determines that the subsequently input information is a rewrite address, and outputs the storage memory address signal 11.
The information that is subsequently input is determined to be new sequence control information, and is output as the storage memory data signal 12, and written to the storage memory 1 using the storage memory control signal 13. By the above operation, storage memory 1
The contents of will be rewritten.

Next, the operation when the higher-level control device reads the contents of the storage memory 1 will be explained.

First, when a sequence control information read command and a read address are sent to the power supply control circuit 4 via the serial data input signal 17 under the control of the serial data input control signal 18 from the host control device, the power supply control circuit 4 inputs the control data. 6 control data input/output control circuit 3 that is controlled by the control signal 23 and sends the sequence control information rewriting command and read address to the control data input/output control circuit 301 of the memory control circuit 3 via the control data input signal 22;
01 sequentially sends the received information to the command judgment execution control circuit 302 using a control signal 310. The command determination execution control circuit 302 determines that the information input by the control signal 310 is a memory read command, determines that the subsequently input information is a read address, and outputs the storage memory address signal 11.
The data is read out using the storage memory control signal 13. Next, the read data is output to the control data output signal 24 while being controlled by the control data output control signal. The data outputted by the control data output signal 24 is controlled by the serial data output control signal 20 and outputted to the host control device via the serial data output signal 19.

Through the above operations, the contents of the storage memory 1 are read out.

〔Effect of the invention〕

As explained above, the data storage device of the present invention employs a microprogram method in the sequence control circuit section,
A conventional data storage device that stores sequence control information in a memory and further includes a power supply control circuit that has an interface for transmitting and receiving serial data to and from a host control device in order to turn on and off power from the host control device. The device is equipped with two memories, a storage memory and an execution memory, for storing sequence control information, and the contents of the storage memory that are not used when executing control operations can be transferred from the higher-level control device. By adding write and read functions, the disadvantage of conventional data storage devices is that the memory in which the control information is stored must be removed and replaced when changing the control information. This has the effect that control information can be easily rewritten without replacing the memory. Furthermore, since there is no need to replace the memory, there is also the effect of cost savings. Furthermore, since the unused storage memory is rewritten when a control operation is executed, the control information can be rewritten at any time, and the contents of the execution memory can be rewritten by turning the power back on at any time. Another advantage is that control can be performed using new control information.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing details of the memory control circuit section of the embodiment of FIG. 1...Electrically rewritable nonvolatile memory circuit (
memory for storage), 2... memory circuit (memory for execution), 3... memory control circuit, 4...
- Power supply control circuit, 5... Sequence control circuit section, 301... Control data input/output control circuit, 30
2... Command judgment execution control circuit, 303...
...Memory address signal switching circuit, 304...
Memory data signal switching circuit, 305...Memory control signal switching circuit.

Claims (1)

[Scope of Claims] A sequence control circuit unit that controls various sequence operations; an electrically rewritable nonvolatile memory circuit that retains control information of the sequence control circuit unit when power is turned off; and the sequence control circuit. A memory circuit that reads control information when the unit executes various control operations, and control that is stored in advance in the electrically rewritable nonvolatile memory circuit based on a power-on completion signal sent from the power supply control circuit unit. Transfer information to the memory circuit, and after the transfer is completed, connect the address signal, data signal, and read control signal of the memory circuit to the memory address signal, memory data signal, and memory read control signal of the sequence control circuit section, respectively, and It has an interface signal for instructing the sequence control circuit unit to start control and for exchanging various commands and data with the sequence control circuit unit by serial data, and the electrical rewriting is possible by the interface signal. It has an interface signal for exchanging various commands and data using serial data between a memory control circuit unit that rewrites and reads the contents of arbitrary addresses in a non-volatile memory circuit, and a host control device. Power is turned on in response to a power-on command sent from the higher-level control device via the interface signal, a power-on completion signal is sent to the memory control circuit unit upon completion of power-on, and the power is turned off in response to a power-off command. and transmits the power-on state, abnormality in the power supply, and status of the cooling fan by a status read command, and when an abnormality in the power supply and abnormality in the cooling fan is detected, reports the abnormality to the upper control device; The sequence of the memory addresses of the electrically rewritable non-volatile memory circuit is sent to the memory control circuit section by a sequence control information rewriting command from a higher-level control device, a memory address sent following the command, and new sequence control information. A control information rewrite command and new sequence control information are sent, and the memory control circuit section is electrically rewritten by a sequence control information read command and a memory address sent from the higher-level control device following the command. a power supply control circuit that sends out a sequence control information read command of the memory address of the non-volatile memory circuit, and sends the sequence control information stored in the memory address sent from the memory control circuit unit to the higher-level control device; A data storage device comprising: