JPH06348503A - Device with master and slave control system and its control method - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a nonvolatile memory and to reduce the cost of the device which has the master and slave control systems by allowing plural control systems to share the nonvolatile memory stored with microprograms. CONSTITUTION:The master control system is provided with an MPU 21, the nonvolatile memory 29 stored with the microprogram for master control, microprogram for slave control, and microprogram for data transfer, a flash ROM 16 for downloading, etc., and the slave control systems are each provided with an MPU 24, a nonvolatile memory 31, an address switching circuit 28, etc.; and a communication memory 13 that the MPUs of the master control system and slave control system can access is provided and the microprogram for slave control is transferred from the master control system to the nonvolatile memories 31 of respective slave control systems through the communication memory 13 to control the respective slave control systems.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention provides a master / slave control system having two or more control systems, one of which is a master control system and the other control system is a slave control system. It is used for a device (for example, a magnetic tape device) that has it.

[0002]

2. Description of the Related Art FIGS. 16 to 19 are views showing a conventional example. In FIGS. 16 to 19, 1 is a magnetic tape device (MT).
U), 2 is an interface control system (hereinafter referred to as “IF control system”), 3 is a servo control system (hereinafter referred to as “SV control system”)
4) is a head (read / write head, etc.), 5
Is a motor, 6 is a sensor, 7 is a write control unit, 8 is a read control unit, 9 is a motor drive circuit, 10 is a detection circuit, 11 is an interface control unit (hereinafter referred to as “IF control unit”), and 12 is a servo control unit. (Hereinafter referred to as “SV control unit”), 13 is a communication memory, 14 and 17 are RAM (Random Access Memory), and 15 and 18 are ROM.
(Read Only Memory), 16 and 19 are flash ROMs
(FLASH ROM), 22 and 25 are input / output control units (hereinafter referred to as “I / O control units”), 23 and 26 are address decoding circuits, and 43 is an interface MPU (Mi).
cro Processor Unit) (hereinafter referred to as “IF MPU”), 44 is a servo control MPU (hereinafter “SV MPU”)
U ”).

§1: Description of magnetic tape device--see FIG. 16 FIG. 16 is a schematic configuration diagram of a magnetic tape device. Less than,
A schematic configuration of the magnetic tape device will be described with reference to FIG.

The magnetic tape device (MTU) 1 includes an IF control system 2 for controlling an interface with a host device (magnetic tape control device: MTC), an SV control system (servo control system) 3 for controlling a mechanical section. There are these control systems (I
The F control system and the SV control system) constitute a logic control unit (logic control unit).

The IF control system 2 includes an IF control unit 1
1, ROM 15, flash ROM 16, and RAM
14 and the like, and the SV control system 3 includes an SV control unit 12 and
A ROM 18, a flash ROM 19, a RAM 17, etc. are provided.

In addition to the above logic system control unit, the magnetic tape device 1 has a communication memory 1
3, a read controller 8 for controlling reading of data from the medium,
A write controller 7 for controlling writing of medium data, a head (read / write head, etc.) 4, a motor (reel motor, etc.) 5, a sensor 6, a motor drive circuit 9, a sensor 6.
A detection circuit 10 and the like for detecting the output signal of is provided.

In the magnetic tape device having such a structure, the IF control system 2 is a master control system and the SV control system 3 is a slave control system. Then, the IF control system 2
A communication memory 13 is provided between the (master control system) and the SV control system 3 (slave control system).
Both control systems transfer data or information via the communication memory 13.

§2: Description of Master / Slave Control System--See FIG. 17 FIG. 17 is a block diagram of a master / slave control system. As described above, the magnetic tape device 1 has the I / F control system (master control system) 2 and the SV control system (slave control system) 3.

Hereinafter, regarding the master / slave control system,
This will be described with reference to FIG. As shown in the figure, the IF control system (master control system) 2 includes an IF MPU 43 and R
OM15, flash ROM16, I / O control section 2
2, the RAM 14, and the address decoding circuit 23 are provided.

The SV control system (slave control system) 3 includes an SV MPU 44, a ROM 18, and a flash R.
An OM 19, an I / O control unit 25, a RAM 17, and an address decoding circuit 26 are provided.

The IF MPU 43 and the SV M
The PUs 44 are independent of each other and each have an address bus (IF ADDRESS BUS, SV ADDRES BUS) and a data bus (IF DATA BUS, SV DATA BUS).

The IF MPU 43 shown in FIG.
16, the address decode circuit 23 is provided in the IF control unit 11 of FIG. 16, and the SV MPU 44 of FIG. 17 and the address decode circuit 26 are provided in the SV control unit 12 of FIG.

The function of each part is as follows. (1): The IF MPU 43 is a processor that performs various controls of the IF control system 2.

(2): The ROM 15 is a non-volatile memory storing a control microprogram of the IF control system 2. (3): The flash ROM 16 is transferred from the host device to the IF
This is a non-volatile memory for downloading the microprogram of the control system when updating the microprogram.

(4): The I / O control unit 22 uses various I / O
O (input / output) control is performed. (5): The RAM 14 is the ROM 15 when the MPU 21 is used for work or performs a high speed operation.
It is a memory used to transfer the micro program of.

(6): The address decoding circuit 23 uses I
This is a circuit for decoding an address on the F address bus. (7): The communication memory 13 is a memory used when transferring various data or information between the IF control system 2 and the SV control system 3.

(8): The SV MPU 44 is a processor for performing various controls of the SV control system 3. (9): The ROM 18 is a non-volatile memory that stores a control microprogram of the SV control system 3.

(10): The flash ROM 19 is a non-volatile memory for downloading the micro program of the SV control system from the host device when the micro program is updated.

(11): The I / O controller 25 uses various I / O
/ O (input / output) control. (12): The RAM 17 is used as the ROM 1 when the MPU 24 is used for work or operates at high speed.
8 is a memory used to transfer 8 microprograms.

(13): The address decoding circuit 26
This is a circuit for decoding an address on the SV address bus. As described above, the MPU 43 for IF and the MPU 44 for SV
Are different control systems (IF control system and SV control system),
The respective control microprograms were separated into ROMs 15 and 18 accessible by each MPU.

That is, the control microprogram of the IF control system 2 is stored in the ROM 15, and the control microprogram of the SV control system 3 is stored in the ROM 18. Therefore, the same number of ROMs (nonvolatile memories) as MPUs or more are required.

Further, when the microprogram is updated from the host device, each control system is flash RO
The download process was performed using M. For example,
The control microprogram of the IF control system is a higher-level device (M
TC), the control microprogram is downloaded to the flash ROM 16 and the SV
When the control microprogram of the control system is updated from the host device, the control microprogram is downloaded to the flash ROM 19.

Therefore, the flash RO for download
M16 and 19 are provided for each control system and ROM
It was configured with a memory having the same capacity as that of 15, 18. In this way, physically, the ROM of the IF control system 2 and the SV control system 3
(Non-volatile memory) was separated, so ROM1
Even if the actually used memory capacity of 5 and 18 was physically sufficient for one ROM, each MPU required a ROM.

Further, when high speed control is required, high speed RAMs 14 and 17 are required for each control system. In this case, the microprograms in the ROMs 15 and 18 are
Each control system was controlled by using the microprograms in the RAMs 14 and 17 after the transfer to the AMs 14 and 17.

§3: Description of Control of Master / Slave Control System ... See FIG. 17 As described above, the MPU of each control system (IF MPU 43)
The SV MPU 44) is provided with one ROM and one flash ROM for one MPU, and the control microprograms of the respective control systems are stored in the ROM for control.

RAMs (volatile memories) 14 and 17 are provided for high-speed control and to secure a work area.
Was provided to control. The outline of the control of the control system will be described below. In the following description, the address (X
(X XX XX) Hex represents a hexadecimal number, and X represents an arbitrary value.

Each of the ROMs 15 and 18 has an address (0X XX XX) Hex in terms of hardware, and when the IF MPU 43 and the SV MPU 44 specify the address (0XXX XX) Hex, the ROM 1 is used.
5 and the ROM 18 are selected.

Thus, the IF MPU 43 and the SV M
Since the PU 44 is booted from the address (0000 hex) Hex, when the power is turned on (when the device is booted), RO
M15 and 18 are selected, and the IF MPU4 is selected in accordance with the control microprogram of each control system in the ROM 15 and 18.
3 and the SV MPU 44 controls each control system.

Even when speed is required for control,
It cannot be booted from RAM14,17. Therefore, in such a case, the control microprograms in the ROMs 15 and 18 are once transferred to the RAMs 14 and 17, and then the control microprograms in the RAMs 14 and 17 are used for control.

Further, when the control microprogram is downloaded to the flash ROM, the flash ROM is selected instead of the ROM to perform the control.

§4: Description of Address Decode Circuit--See FIG. 18 FIG. 18 is an explanatory diagram of the address decode circuit, and FIG.
8A is an explanatory diagram of the address decoding circuit, and FIG. 18B is an example of input (upper 3 bits) and output of the address decoding circuit.

When the MPUs 21 and 24 specify an address, the hardware configuration until actual selection is as follows:
An address decoding circuit as shown in FIG. 18A is used (the same circuit in the IF control system and the SV control system).

This address decoding circuit 23 (or 2
In 6), eight signal lines are selected by the upper 3 bits of the address bus. Note that only the selected signal line becomes low level L, and the other signal lines become high level H.
Is.

For example, if the upper 3 bits are (0X
XX XX) Hex, signal line 0 is selected, and (1X
XX XX) Hex, signal line 1 is selected, and (2X
(XXXX) Hex, signal line 2 is selected, (5
(X XX XX) Hex, the signal line 5 is selected, and (6
If (X XX XX) Hex, the signal line 6 is selected, and (7
If (X XX XX) Hex, the signal line 7 is selected.

In this case, in each of the signal lines, 0 is a ROM select signal, 1 is a RAM select signal, 2 is a communication memory select signal, ...
This is an O control unit select signal.

An area on each memory can be selected by using this signal line as a select signal. That is, IF MPU 43 (or SV MPU 4
In 4), only the selected one can be accessed by the select signal output from the address decoding circuit 23 (or 26).

§5: Description of memory capacity--see FIG. 19 FIG. 19 is an explanatory view of the capacity of the nonvolatile memory.
9A is a diagram showing the capacity of the ROM 15, and FIG. 19B is a ROM.
18 is an explanatory diagram of the capacity, and FIG. 19C is an explanatory diagram of the combined capacity.

The capacity of the ROM (nonvolatile memory) actually used is as follows. For example, RO
It is assumed that the in-use area of M15 is the area shown in FIG. 19A and the in-use area of the ROM 18 is the area shown in FIG. 19B. When the areas in use of these two ROMs are combined, for example, as shown in FIG. 19C, R
It is assumed that the area is smaller than the capacity of the OM15.

As described above, even when the capacity of the area used by two or more ROMs is smaller than the total capacity of one ROM, a ROM (nonvolatile memory) is required for each control system. Therefore, the memory usage efficiency is low. Also,
The same applies to the flash ROM.

[0040]

SUMMARY OF THE INVENTION The above-mentioned conventional devices have the following problems. : Since the MPU for IF and the MPU for SV are different control systems (master control system and slave control system), each microprogram has a ROM accessible by each MPU.
(Non-volatile memory).

Therefore, the ROM (nonvolatile memory) is
It needed the same number as MPU or more. Therefore,
The number of non-volatile memories storing microprograms increases, which also causes an increase in the cost of the device.

When each of the above microprograms is updated from the host device, each control system uses the flash ROM to perform the download process. In this case, the flash ROM for download is
It was composed of a memory with the same capacity as the ROM.

Therefore, the number of flash ROMs is large,
Moreover, a large capacity was needed. As a result, the cost of the device has increased. : Physically RO of master control system and slave control system
Since M (non-volatile memory) and flash ROM are separated, even if the memory capacity actually used for ROM or flash ROM is physically sufficient for one memory, each MPU will have a ROM. I needed it.

The present invention solves such a conventional problem, and a plurality of control systems are used to store a non-volatile memory in which micro programs are stored, or a flash RO for downloading.
By sharing M, it is intended to improve the efficiency of use of the memory and reduce the cost of the device.

[0045]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the same parts as those in FIGS. 16 to 19 are designated by the same reference numerals. Further, 21 and 24 are MPU (Micro
Processor Unit), 28 is an address switching circuit, 29 is a non-volatile memory, and 30 and 31 are volatile memories.

In order to solve the above problems, the present invention has the following constitution. (1): In a device having two or more control systems, one of which is a master control system, and the other control system being a slave control system, the master control MPU21 for controlling the master control system
And a master control microprogram used to control the master control system, a slave control microprogram used to control each slave control system, and slave data transfer for transferring the slave control microprogram to the slave control system. A non-volatile memory 29 storing a micro program for use, an I / O control unit 22 for controlling input / output of a master control system, and an MPU 24 for controlling the slave control system in the slave control system, and a master control system And a volatile memory 31 for storing the slave control microprogram transferred from the slave control system.
An I / O control unit 25 for performing output control is provided, and a communication memory 13 accessible by the MPU 21 of the master control system and the MPU 24 of the slave control system is provided.
The slave control microprogram is transferred from the master control system via the communication memory 13 to the volatile memory 31 of each slave control system, and each slave control system is controlled. Was shared by the master / slave control system.

(2): In the device having the master / slave control system of the above configuration (1), the slave control system is provided with the address switching circuit 28 for switching the address area accessed by the MPU 24 of the slave control system, The address area accessed by the control MPU 24 is
The communication memory 13 is switched to accessible when the control of the MPU 24 is started, and the volatile memory 31 is switched to accessible after the slave control microprogram is transferred to the volatile memory 31.

(3): In the device having the master / slave control system of the above configuration (1), the flash ROM 16 is provided in the master control system, and each microprogram of the nonvolatile memory 29 is updated from the host device. In that case, the micro program, flash ROM above
By downloading to 16, the master control system and the slave control system microprograms can be updated.

(4): One master control system and one or more slave control systems. The master control system includes the MPU 21 for controlling the master control system and the non-volatile memory 2.
9, a slave control system is provided with an MPU 24 for controlling the slave control system, a volatile memory 31 and a master control system MPU 21 and a slave control system M.
Communication memory 1 accessible by PU 24
In a control method of an apparatus having a master / slave control system provided with No. 3, a master control microprogram used for controlling the master control system in advance in the nonvolatile memory 29 of the master control system, and control of each slave control system. Data such as a microprogram for slave control to be used for is stored in the:
U21 reads the slave control microprogram from the non-volatile memory 29 and transfers it to the communication memory 13: After that, in the slave control system,
The MPU 24 transfers the slave control microprogram on the communication memory 13 to the volatile memory 31.
The volatile memory 31 is selected by switching the address area to be accessed by 24, and the MPU 24 is configured to start control by the slave control microprogram of the volatile memory 31.

(5): In the control method of the device having the master / slave control system of the above configuration (4), in the master / slave control system: In the nonvolatile memory 29 of the master control system, in addition to the above microprogram, A slave data transfer microprogram for transferring the slave control microprogram to the slave control system is stored in advance: When power is turned on, the master control system MPU 21 is stored.
Only in the master control system, the MPU 24 in the slave control system is kept in the halt state (operation stopped state). In the master control system, the MPU 21 reads the microprogram for data transfer from the nonvolatile memory 29 and transfers it to the communication memory 13. Then, in the master control system, the MPU 21 releases the halt state of the MPU 24 of the slave control system to start the control, and the MPU 21 of the master control system further executes the slave control microprogram from the nonvolatile memory 29. In the slave control system, the MPU 24 starts control in the communication memory 13 after releasing the halt state in the slave control system, and the slave control in the communication memory 13 is performed by the data transfer microprogram. For The black program was configured to transfer the volatile memory 31.

[0051]

The operation of the present invention based on the above configuration will be described with reference to FIG. (1): First, the master control system MPU 21 selects the non-volatile memory 29 when the power is turned on, and the slave memory data transfer micro program read from the non-volatile memory 29 to the communication memory 13 (servo control system boot program). ) Transfer.

(2): After that, the MPU 21 releases the halt signal set in the register in the I / O control unit 22, and starts the MPU 24 of the slave control system.
By this processing, the MPU 24 starts control in the communication memory 13.

(3): Next, the MPU 2 of the master control system
Reference numeral 1 designates the access area as the communication memory 13 and stores the slave control microprogram read from the nonvolatile memory 29 in the communication memory 13
Transfer to.

(4): On the other hand, in the slave control system, when the halt signal is released, the MPU 24 rises and the communication memory 13 starts control as described above. (5): Then, the MPU 24 transfers the slave control microprogram in the communication memory 13 to the volatile memory 31 and writes the slave control microprogram in the slave data transfer microprogram.

(6): After that, when the final data writing is completed, in the slave control system, the address switching circuit 2
8, the address area accessed by the MPU 24 is switched, the volatile memory 31 is selected, and the MPU 24 starts control by the slave control microprogram of the volatile memory 31.

With the above arrangement, the master control system and the slave control system microprograms may be collectively stored in the non-volatile memory of the master control system. Further, when updating the microprogram from the host device, if the microprogram is downloaded to the flash ROM 16 of the master control system, it can be used in each slave control system in the same manner as the microprogram of the nonvolatile memory. You can

Therefore, in a plurality of control systems, a non-volatile memory storing a microprogram and a flash ROM
Can be shared, the efficiency of memory usage can be improved, and the cost of the device can be reduced.

[0058]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 15 are views showing an embodiment of the present invention. In FIGS. 2 to 15, the same parts as those in FIG. 1 and FIGS. 16 to 19 are designated by the same reference numerals.

Further, 34 and 35 are AND circuits (logical product circuits), 36 and 37 are OR circuits (logical sum circuits), and 38 is N.
OT circuit (negative circuit), 40 is DPRAM (Dual Port)
RAM), 41 is an EPROM (Erasable and Programma)
ble ROM), 42 is SRAM (Static RAM), 4
Reference numerals 5 and 46 denote registers.

(Basic Description of Embodiment) First, a basic description of the embodiment will be given with reference to FIGS. §1: Explanation of basic configuration of master / slave control system
.. see FIG. 2 FIG. 2 is a basic configuration diagram of the master / slave control system.

As shown in the figure, the control system is composed of a master control system and a slave control system, and a communication memory 13 is provided between both control systems. The master control system includes the MPU 21, the non-volatile memory 29, the flash ROM 16, and the I / O control unit 22.
A volatile memory 30 and an address decoding circuit 23 are provided.

The slave control system includes an MPU 24.
A volatile memory 31, an I / O control unit 25, an address decoding circuit 26, and an address switching circuit 28 are provided. The function of each part is as follows.

(1): The MPU 21 is a processor for performing various controls of the master control system. (2): The nonvolatile memory 29 includes a master control microprogram (a microprogram used for control in the master control system), a slave control microprogram (a microprogram used for control in the slave control system), and slave data. This is a memory that stores data such as a transfer microprogram (a microprogram for transferring a slave control microprogram).

(3): The flash ROM 16 is a non-volatile memory for downloading the microprogram from the host device when the microprogram is updated.

(4): The I / O control unit 22 uses various I / O
(Input / output) control is performed. Also, this I / O
The control unit 22 is provided with a register (described later) for setting / releasing (setting / resetting) a halt signal for the MPU 24 of the slave control system.

(5): The volatile memory 30 is used by the MPU 21 of the master control system for work, or
It is a memory for transferring and using the microprogram of the non-volatile memory 29 when the master control system is controlled at high speed.

(6): The address decoding circuit 23 is a circuit for decoding an address on the address bus of the master control system. (7): The communication memory 13 is a memory used when transferring various data (microprogram etc.) or information (status information etc.) between the master control system and the slave control system.

(8): The MPU 24 is a processor for performing various controls of the slave control system by the microprogram transferred from the master control system. (9): The I / O control unit 25 uses various I / O (input / output)
It controls. In addition, this I / O control unit has
A register (described later) for setting a selection signal (selection signal) of the address switching circuit is provided.

(10): The volatile memory 31 is a memory for storing the control microprogram (slave control microprogram) of the slave control system sent from the master control system.

(11): The address decoding circuit 26
This is a circuit for decoding an address on the address bus of the slave control system. (12): The address switching circuit 28 is a circuit for switching addresses according to the signal decoded by the address decoding circuit 26 and the signal from the register in the I / O control unit 25.

§2: Description of Memory Map of Nonvolatile Memory and Communication Memory ... See FIG. 3 FIG. 3 is a diagram showing a memory map, FIG. 3A is a memory map of the nonvolatile memory 29, and FIG. It is a memory map of the communication memory 13.

Communication memory 1 shown in FIG.
3 and the internal area of the non-volatile memory 29 of the master control system are divided as shown in FIG. In this example, the memory area of the non-volatile memory 29 is divided into at least three areas, area 1 is an area for storing a master control microprogram, area 2 is an area for storing a slave control microprogram, and area 3 is a slave. This area is used to store the microprogram for data transfer.

The area of the communication memory 13 is also divided into three areas, area 1 is a slave data transfer microprogram area, area 2 is a communication area, and area 3 is a slave control microprogram transfer area.

The communication area of the area 2 is an area in which the MPU 21 issues a command to the MPU 24 and the MPU 24 sends status information to the MPU 21.

§3: Description of access area of slave control system MPU--see FIG. 4 FIG. 4 is an explanatory view of the access area of the slave control system MPU. FIG. 4A is before address switching, and FIG. 4B is after address switching. Indicates.

In the following description, the address (XX
XX XX) Hex represents a hexadecimal number, and X represents that any value will do. For example, the address (00 00 0
0) In the access area from Hex to (0X XX XX) Hex, the communication memory 1 before the address switching
The area of No. 3 is the area of the volatile memory 31 after the address switching.

In addition, the address (10000) Hex
The area of (1X XX XX) Hex is the access area of the volatile memory 31 before the address switching, but becomes another access area (space area in this example) after the address switching.

Further, the address (20:00 00) Hex
In the area of (2X XX XX) Hex, before the address switching, another access area (space area in this example)
However, it becomes the access area of the communication memory 13 after the address switching.

§4: Description of Address Switching Logic--See FIG. 5 FIG. 5 is a basic explanatory diagram of the address switching logic.
5A is an explanatory diagram of the address decoding circuit, and FIG. 5B is an explanatory diagram of the address switching circuit.

The basic address switching logic of the slave control system will be described below with reference to FIG. In the following description, the case where the slave control system has one MPU will be described. However, when there are two or more slave control system MPUs (a plurality of slave control systems are connected to one master control system). The case) is the same as the following logic.

Description of Address Decode Circuit The address decode circuit 26 inputs the upper address 3
One signal line is selected by 3 bits of the upper address. In the following description, the low level is L and the high level is H for each signal line.

* DATA0 to * DATA shown in FIG. 5A
Reference numeral 7 denotes a signal line on the output side of the address decode circuit 26. Only one signal line selected by the address decode circuit 26 becomes L, and the other seven signal lines are H (only the selected signal line is selected. At L, the other signal lines are at H).

Further, * DATA0 to * DATA7 are addresses (0X XX XX) Hex to (7X XX XX) accessed by the MPU 24 of the slave control system, respectively.
The signal for selecting Hex is shown.

For example, if the upper 3 bits are (0X
XX XX) Hex, * DATA0 = L, * DAT
A1 to * DATA7 = H. In addition, (1X XX
XX) Hex, * DATA1 = L, * DATA0 =
H, * DATA2 to * DATA7 = H, and (2X
XX XX) Hex, * DATA2 = L, * DATA
0 = H, * DATA1 = H, * DATA3 to * DATA
7 = H.

Description of Address Switching Circuit As shown in FIG. 5B, the address switching circuit 28 includes:
AND circuits 34 and 35, OR circuits 36 and 37, and NO
A T circuit 38 is provided.

Then, as an input signal of the address switching circuit 28, SELECT (select signal from the I / O control section 25) and a signal line * D of the address decoding circuit 26 are inputted.
The signals of ATA0, * DATA1, and * DATA2 are used, and the signals of * COMM and * RAM are output as output signals.

In this case, the data switching signal is set to SELE.
CT, the signal line for selecting the communication memory 13 is * COMM, and the signal line for selecting the volatile memory 31 is * RAM.

The MPU 24 uses the address (00 00 0
0) Since it starts from Hex, the data indicating the upper address is (0X XX XX) Hex at the beginning, and *
DATA0 is selected.

Therefore, the signal line of * DATA0 becomes L, and * DATA1 to * DATA7 become H. At this time,
Since SELECT is configured to be hard reset, SELECT = L.

Therefore, * DATA0 is L, SELECT
Is L, the output of the OR circuit 36 becomes L, and AND
The circuit 34 becomes L because * DATA2 is H. As a result, the signal line * COMM for selecting the communication memory 13 becomes L. In this way, * CO
When MM = L, the communication memory 13 is in the selected state.

Next, when switching is performed, SELECT =
When set to H, when * DATA0 is selected, NOT circuit 3
The output of 8 becomes L, and the output of the OR circuit 37 is * DAT.
Since A0 is also L, it becomes L.

Therefore, the output of the AND circuit 35 is * D
Although ATA1 is H, it becomes L and the volatile memory 31 is selected. The address is switched by the above switching logic.

(Explanation of Embodiments by Specific Examples) Hereinafter, an example of the master / slave control system in the magnetic tape device will be described in detail.

§1: Description of Configuration of Magnetic Tape Device--See FIG. 6 FIG. 6 is a configuration diagram of the magnetic tape device. The configuration of the magnetic tape device will be described below with reference to FIG.

The magnetic tape unit (MTU) 1 has an IF control system (interface control system) 2 for controlling an interface with a host device (magnetic tape controller: MTC).
And an SV control system (servo control system) 3 for controlling the mechanical section, and these control systems (IF control system and SV control system)
Thus, a logic control unit (logic control unit) is configured.

The IF control system 2 includes the IF control unit 1
1, EPROM 41, flash ROM 16, R
The AM 14 and the like are provided, and the SV control system 3 includes an SV control unit 12
The SRAM 42, the address switching circuit 28, and the like are provided.

Further, in the magnetic tape device 1, a DPRAM (used as a communication memory) 40, a read control unit 8 for controlling reading of medium data, and writing of medium data are provided in addition to the above logic system control unit. A control write controller 7, a head (read / write head) 4, a motor (reel motor or the like) 5, a sensor 6, a motor drive circuit 9, a detection circuit 10 for detecting an output signal of the sensor 6, and the like. It is provided.

In the magnetic tape device having such a structure, the IF control system 2 is a master control system and the SV control system 3 is a slave control system. Then, the IF control system 2
A DPRAM 40 is provided between the (master control system) and the SV control system 3 (slave control system), and both control systems transmit data (microprogram etc.) or information (status information etc.) via the DPRAM 40. ) Transfer.

§2: Description of Master / Slave Control System--See FIG. 7 FIG. 7 is a block diagram of a master / slave control system of the magnetic tape device shown in FIG.

In the control system of the magnetic tape device, the IF control system (master control system) 2 is provided with an IF MPU 43 and an EP.
A ROM 41, a flash ROM 16, an I / O control unit 22, a RAM 14, and an address decoding circuit 23 are provided.

The SV control system (slave control system) 3 is provided with an SV MPU 44, an SRAM 42, an I / O control unit 25, an address decoding circuit 26, and an address switching circuit 28.

The I / O control section 22 is provided with a register 45, and the I / O control section 25 is provided with a register 46.
And a DPRAM forming a communication memory between the IF control system 2 and the SV control system 3.
40 is provided.

The IF MPU 43, the I / O control unit 22, and the address decoding circuit 23 are provided in the IF control unit 11, and the SV MPU 44 and the address decoding circuit 26 are provided in the servo control unit 12. It is provided.

The function and the like of each part are as follows. (1): The IF MPU 43 is a processor that performs various controls of the IF control system 2.

(2): The EPROM 41 has an IF control microprogram (a microprogram used for control in the IF control system), an SV control microprogram (a microprogram used for control in the SV control system), and SV data. It is a non-volatile memory that stores data such as a transfer microprogram (a microprogram for transferring an SV control microprogram).

(3): The flash ROM 16 is a non-volatile memory used for downloading the microprograms when the above microprograms are updated from the host device, and is composed of a memory having the same capacity as the EPROM 41.

The flash ROM is a non-volatile memory that can electrically write and erase data as needed. Therefore, the flash RO as described above
When EPROM, which is a non-volatile memory that is rewritable by general ultraviolet rays, or PROM, which is a writable non-volatile memory, is used instead of M, when the program data is updated, once the EPROM, or It was necessary to remove the PROM from the printed circuit board and replace it with a newly updated EPROM or PROM.

In this case, the work of exchanging the memory is performed manually, and since the memory is removed from the printed circuit board, it is necessary to turn off the power supply of the device, and the system must be brought down.

However, if a flash ROM is used,
At the time of updating the microprogram, the download can be easily performed as it is without removing it from the printed circuit board and without turning off the power of the apparatus.

Therefore, flash R is available for downloading.
When the OM is used, human intervention is eliminated at the time of updating the microprogram, and labor can be saved. Therefore, maintainability is improved.

(4): The I / O control unit 22 uses various I / Os.
(Input / output) control is performed. Also, this I / O
The control unit 22 is provided with a register 45 for setting / releasing (setting / resetting) a halt signal for the SV MPU 44 of the SV control system 3.

(5): The RAM 14 is the IF of the IF control system.
Used by the MPU43 for work, or I
It is a memory for transferring and using the microprogram of the EPROM 41 when the control of the F control system is performed at high speed.

(6): The address decoding circuit 23
This is a circuit for decoding an address on the IF address bus of the F control system. (7): The DPRAM 40 is a communication memory used when transferring various data (microprogram etc.) or information (status information etc.) between the IF control system 2 and the SV control system 3.

(8): The SV MPU 44 receives the SV by the microprogram transferred from the IF control system 2.
It is a processor that performs various controls of the control system 3. (9): The I / O control unit 25 uses various I / O (input / output)
It controls. In addition, this I / O control unit has
A register 46 for setting a selection signal (selection signal) of the address switching circuit is provided.

(10): The SRAM 42 is the IF control system 2
This is a memory that stores the SV control microprogram sent from the computer. (11): The address decoding circuit 26 has the SV control system 3
It is a circuit for decoding the address on the SV address bus.

(12): The address switching circuit 28 outputs the signal decoded by the address decoding circuit 26 and I
This is a circuit for switching addresses according to a signal from a register 46 in the / O control unit 25.

§3: Description of memory map when power is turned on--see FIG. 8 FIG. 8 is a memory map when power is turned on (before address switching). Memory map at power-on (before address switching) (memory map of DPRAM area and RAM area)
Is as follows. (1) to (4) are addresses of the SV control system, and (5) to (7) are addresses of the IF control system.

In the following description, the address (XX
XX XX) Hex represents a hexadecimal number, and X represents that any value will do. (1): Address (00 00 00) Hex to (01
FF FF) Hex is an area 1 of the DPRAM 40 (communication memory) accessed by the SV MPU 44.
Is. This area 1 is used as an SV data transfer microprogram area.

(2): Address (02 00 00) He
x to (0200 FF) Hex is the area 2 of the DPRAM 40 accessed by the SV MPU 44. This area 2 is further divided into three areas.

Among them, the address (02 00 00) He
x is “IF → SV command area” (from the IF control system to S
The area for storing the command to be passed to the V control system), the address (0202002) Hex is “SV → IF status area” (the area for storing the status information to be passed from the SV control system to the IF control system), to (02 00 FF ) Hex
It is an "IF-SV communication area" (a communication area between the IF control system and the SV control system).

(3): Address (02 01 00) He
x to (0F FF FF) Hex is the area 3 of the DPRAM 40 accessed by the SV MPU 44. This area 3 is an SV control microprogram (SV MPU 4
4 is a transfer area for a control microprogram used.

(4): Address (10 00 00) He
x is an access area of the SRAM 42 of the SV control system. This area is used as a writing area for the SV control microprogram.

(5): Address (20 00 00) He
x to (21 FF FF) Hex is the area 1 of the DPRAM 40 accessed by the IF MPU 43. This area 1 is used as an area for storing the SV data transfer microprogram.

(6): Address (22 00 00) He
x to (2200 FF) Hex is the area 2 of the DPRAM 40 accessed by the IF MPU 43. This area 2 is further divided into three areas.

Among them, the address (22 00 00) He
x is an area for storing the "IF command" (command issued by the IF control system), address (22 00 02) He
x is an "SV status" area (area that receives status information from the SV control system), ~ (2200 FF)
Hex is the "IF-SV communication area" (I
It is a communication area between the F control system and the SV control system.

(7): Address (22 01 00) He
x to (2F FF FF) Hex is the area 3 of the DPRAM 40 accessed by the IF MPU 43. This area 3 is an SV control microprogram (SV MPU 4
4 is a transfer area for a control microprogram used.

§4: Description of memory map after address switching--see FIG. 9 FIG. 9 is a memory map after address switching. The memory map after the address switching is as follows. In addition,
The address (XX XX XX) Hex is in hexadecimal notation.

After the address switching, the address area accessed by the SV MPU is switched. That is, the SV control system address (00 00 00) Hex at power-on
~ (01 FF FF) Hex, (02 00 00) He
x, (02 00 02) Hex, ~ (02 00 F
F) Hex, (02 01 00) Hex ~ (0F FF
FF) Hex is the address (20000)
0) Hex to (21 FF FF) Hex, (2200)
00) Hex, (2200 02) Hex, ~ (2200)
FF) Hex, (22 01 00) Hex ~ (2F F
F FF) Hex is switched.

In addition, the SV control system address (1000
00) Hex is switched to the address (00 00 00) Hex. Then, after the address switching, the address (20000 00) Hex to (21FF FF) Hex
Of the IF MPU 43 and SV MPU 44.
SV communication area ".

The address (00 00 00) Hex
Is the execution area of the SV control microprogram.
The other address areas are the same as when the power was turned on. §5: Description of address decoding circuit and address switching circuit ... See FIGS. 10 and 11. FIG. 10 is an explanatory diagram of the address decoding circuit, FIG. 11A is an explanatory diagram of the address switching circuit, and FIG. 11B is an I / O control unit. 3 is an explanatory diagram of a register of FIG.

Hereinafter, referring to FIGS. 10 and 11, S
The address switching logic of the V control system will be described. In the following description, the low level is L and the high level is H.

Description of Address Decode Circuit ... See FIG. 10. The address decode circuit 26 shown in FIG. 10 is a specific example of the address decode circuit shown in FIG. 5A. It is a circuit that inputs and decodes.

This address decode circuit 26 has its input as the upper address 3 bits and selects each signal line by the upper address 3 bits. Then, only the selected signal line becomes L (low level), and the other signal lines become H (high level).

For example, if the upper 3 bits are (0X
XX XX) Hex, * DPR1 = L, * SRAM
= H, * DPR2 = H. Also, (1X XX X
X) When Hex, * DPR1 = H, * SRAM = L, * D
When PR2 = H and (2X XX XX) Hex, *
DPR1 = H, * SRAM = H, * DPR2 = L.

The * DPR1 and * SR shown in FIG.
The signal lines AM and * DPR2 correspond to the signal lines * DATA0 to * DATA2 in FIG. 5A, respectively. : Description of address switching circuit ... FIGS. 11A and 11B
The B reference address switching circuit 28 has the same configuration as the circuit shown in FIG. 5B, and AND circuits 34 and 35, an OR circuit 36,
37 and a NOT circuit 38.

However, the input signal and the output signal of the address switching circuit 28 are as shown in FIG. 11A. In this case, input to the address switching circuit shown in FIG. 5B * D
ATA0, * DATA1, * DATA2, SELECT
11A includes * SRAM, * DPR1, * DPR2, and RRMSL in the address switching circuit shown in FIG. 11A, respectively.
Has become.

Further, * COMM and * RAM of the address switching circuit shown in FIG. 5B are respectively * DPRCS and * SRAM in the address switching circuit shown in FIG. 11A.
It is CS.

The input signal RRMSL is as shown in FIG.
As shown in B, this is the output signal of the register 46 provided in the I / O control unit 25. §6: Description of address switching logic ... FIGS. 10 and 11
Reference The address switching logic will be described below with reference to FIGS.

The address decoding circuit shown in FIG.
The address switching logic of the SV control system by the address switching circuit shown in FIG. 11 is basically the same as the address switching logic by the circuit shown in FIG.

When switching addresses, MP for SV
U44 specifies an address on the address bus (SV address bus of the SV control system). Of these addresses, the upper 3 bits of the address are input to the address decoding circuit 26 and decoded, and the signal lines * DPR1, * SRAM, *
DPR2 or the like is selected. Note that only one selected signal line becomes L, and all other signal lines become H in the non-selected state.

S at power-on (before address switching)
V control system selection process For example, if the upper 3 bits are (0X XX X
X) Hex, the signal line * DPR1 is selected and * DPR1 is selected.
PR1 = L, * SRAM = H, * DPR2 = H.

Here, RRMSL is connected to the register 46, and this register 46 is cleared when the SV MPU 44 is started up. Therefore, MPU4 for SV
When RMSSL is started up (before address switching), RRMSL
= L.

Further, the SV control system uses the address (00 0
Since 00) Hex starts, the upper 3 bits of the address are (00 00 00) at the start,
The signal line * DPR1 = L.

That is, when the SV MPU 44 is started up (before address switching), RRMSL = L, * DPR
Since 1 = L, the output signal of the OR circuit 36 is L. In this case, when * DPR1 is selected, *
The SRAM and * DPR2 etc. are H. Therefore, * DP
When R1 is selected, the output of the AND circuit 34 is L
And * DPRCS = L, and DPRAM40
(Communication memory) is selected.

At this time, since the output of the NOT circuit 38 is H, the output of the OR circuit 37 is H, and the output of the AND circuit 35 is H, * SRAMCS = H and the SRAM4
2 is in a non-selected state.

The selection with respect to the DPRAM 40 is performed as described above, and when the SRAM 42 is selected from this state, the following is performed. When accessing the SRAM 42, it is selected by designating the address to (1X XX XX) Hex.

In this case, the address is (1X XX X
When X) Hex is designated, the address decoding circuit 26 selects the signal line * SRAM and sets * SRAM = L. At this time, all the other signal lines are at the high level H, so that * DPR1 = H and * DPR2 = H.

That is, * SRAM = L, RRMSL =
L, * DPR1 = H, * DPR2 = H, so * D
PRCS = H, * SRAMCS = L, and SRAM4
2 is selected.

Description at Address Switching and After Address Switching When the SV MPU 44 finishes transferring all the SV control microprograms to the SRAM 42, the address switching is performed. At the time of this address switching, SPU MPU4
4 sets a high level signal in the register 46 in the I / O control unit 25. Therefore, * RRMSL, which is the signal line from the register 46, is set to H.

Therefore, the address (0
(X XX XX) Hex, * DPR1 = L, * DPR
Since 2 = H, * SRAM = H, RRMSL = H,
* DPRCS = H, * SRAMCS = L, SR
AM42 is selected.

The address (2X XX XX) Hex
Then, * DPR1 = H, * DPR2 = L, * SRAM =
Since H and RRMSL = H, * DPRCS = L, *
SRAMCS = H, and the DPRAM 40 (communication memory) is selected.

§7: Description of Processing of IF Control System ... See FIGS. 12 and 13. FIGS. 12 and 13 are processing flowcharts of the IF control system. The processing of the IF control system will be described below with reference to FIGS. 12 and 13. Note that S1 to S10 in FIGS.
Indicates each processing number.

S1: First, when the power is turned on (when the device is started up), the IF MPU 43 performs an initial diagnosis process. S2: The MPU 43 for IF, when the process of S1 ends,
The address is designated as (20000) Hex, and the access area is set to the area 1 of the DPRAM 40.

S3: Next, the MPU 43 for IF uses the DPR
S read from EPROM 41 in area 1 of AM43
Write the V data transfer micro program (servo control system boot program).

The SV data transfer microprogram is the SV control microprogram (servo control system control microprogram) from the DPRAM 40.
It is a program for transferring to the SRAM 42.

S4: When all the SV data transfer microprograms have been written in the process of S3, the IF
The MPU 43 for use cancels (resets) the halt signal set in the register 45 in the I / O control unit 22.

As a result, the halt signal of the SV MPU 44 is released and the SV MPU 44 is started up. S5: By the processing of S4, the SV MPU 44 makes the DPR
Control starts at AM40.

S6: The MPU 43 for IF specifies the address in (22 01 00) Hex and sets the access area as
The area 3 of the DPRAM 40 is set. S7: After that, the IF MPU 43 uses the SV control microprogram read from the EPROM 41 as a DPR.
Write to area 3 of AM40.

S8: Following the processing of S7, the MPU for IF
43 is an IF command area (area 2) of the DPRAM 40
The load instruction (DPRAM for the SV MPU 44).
(Instruction to load the SV microprogram stored in the SRAM into the SRAM) is written (load instruction is issued).

S9: After that, the MPU 43 for IF uses DP
It is determined whether or not there is a load completion report from the SV MPU 44 in the SV status area (area 2) of the RAM 40. If not, wait for the load completion report.

S10: If a load completion report is received in the processing of S9, the IF MPU 43 further determines whether or not the final data writing of the SV control microprogram has been completed.

As a result, if the final writing is not completed, the process of S6 is performed, but if it is completed, the next I
F control is performed. §8: Description of processing of SV control system ... See FIGS. 14 and 15. FIGS. 14 and 15 are processing flowcharts of the SV control system. The processing of the SV control system will be described below with reference to FIGS. 14 and 15. Note that S11 to S2 in FIGS.
0 indicates each processing number.

S11: When the power is turned on (at the time of start-up), the SV MPU 44 has the halt signal set by hardware by the IF MPU 43. For this reason,
The operation of the SV MPU 44 is stopped.

S12: After that, when the IF MPU 43 releases the halt signal, the SV MPU 44 rises and starts its operation. S13: Then, the SV MPU 44 sets the SV data transfer microprogram to the address (00 00
00) Start with Hex (start with DPRAM40).

S14: SV MP following the processing of S13
The U44 determines whether or not there is a load instruction from the IF MPU 43 in the IF command area (area 2) of the DPRAM 40. As a result, if there is no load instruction, wait until there is a load instruction.

S15: If there is a load instruction in the IF command area of DPRAM 40, IF MPU 43
Specifies the address as (10000) Hex and sets the access area to SRAM 42.

S16: Following the processing of S15, MP for SV
The U44 transfers the SV control microprogram written in the DPRAM 40 to the SRAM 42 for writing. S17: When the writing to the SRAM 42 is completed, SV
The MPU 44 for load issues a load completion report to the SV status area (area 2) of the DPRAM 40.

S18: After that, the SV MPU 44 executes the S
It is determined whether or not the final data writing of the V control microprogram is completed. If not completed, the process of S14 is performed.

S19: When the final data writing has been completed in the processing of S18, the SV MPU 44 executes R
The AM address is changed from (10 00 00) Hex to (0
00000) Switch to Hex.

At the same time, the address of the DPRAM 40 is changed from (00 00 00) Hex to (20 00 0).
0) Switch to Hex. S20: After that, the SV microprogram is SRAM
Start on 42. After that, the SV MPU 44
SV control (servo control) is performed in the SV control system by the SV control microprogram of RAM 42 (microprogram transferred from the IF control system).

(Other Embodiments) Although the embodiments have been described above, the present invention can be implemented as follows. : Regarding the master / slave control system, the example in which the slave control system is one has been explained, but for one master control system,
Even if there are a plurality of slave control systems, they can be implemented in the same manner as in the above embodiment.

The flash ROM for download can be controlled in the same manner as in the case of the EPROM. : The device having the master / slave control system is not limited to the magnetic tape device, but can be applied to any other device (for example, a disk device).

[0173]

As described above, the present invention has the following effects. : A master / slave control system can share a non-volatile memory storing microprograms or a flash ROM for download.

Therefore, it is possible to improve the use efficiency of the memory and realize the cost reduction of the device. : Especially, in a device having a large number of slave control systems for a single master control system, a large number of non-volatile memories and flash ROMs can be saved. Therefore, in such a device, it is possible to further improve the use efficiency of the memory and realize cost reduction of the device.

: Non-volatile memory or flash ROM
Can be physically combined in one place, so that the component mounting space can be reduced. As a result, downsizing and cost reduction of the device can be realized.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a basic configuration diagram of a master / slave control system.

FIG. 3 is a memory map (A is a nonvolatile memory memory map, and B is a communication memory memory map).
Is.

FIG. 4 is an explanatory diagram of an access area of a slave control system MPU (A is before address switching, B is after address switching).

FIG. 5 is a basic explanatory diagram of address switching logic (A is an explanatory diagram of an address decoding circuit and B is an explanatory diagram of an address switching circuit).

FIG. 6 is a configuration diagram of a magnetic tape device.

FIG. 7 is a configuration diagram of a master / slave control system.

FIG. 8 is a memory map when the power is turned on.

FIG. 9 is a memory map after address switching.

FIG. 10 is an explanatory diagram 1 of an address switching logic (an explanatory diagram of an address decoding circuit).

FIG. 11 is an explanatory diagram 2 of an address switching logic (A is an explanatory diagram of an address switching circuit and B is an explanatory diagram of a register).

FIG. 12 is a processing flowchart 1 of the IF control system.

FIG. 13 is a processing flowchart 2 of the IF control system.

FIG. 14 is a processing flowchart 1 of the SV control system.

FIG. 15 is a processing flowchart 2 of the SV control system.

FIG. 16 is a configuration diagram of a conventional magnetic tape device.

FIG. 17 is a block diagram of a conventional master / slave control system.

FIG. 18 is an explanatory diagram of a conventional address decode circuit.

FIG. 19 is an explanatory diagram of a conventional memory capacity.

[Explanation of symbols]

 13 Communication Memory 16 Flash ROM 21, 24 MPU 22, 25 I / O Control Unit 28 Address Switching Circuit 29 Nonvolatile Memory 30, 31 Volatile Memory

Claims (5)

[Claims] 1. In a device having two or more control systems, one control system of which is a master control system and the other control system is a slave control system, wherein a master control is provided. System, the MPU (processor) that controls the master control system (2
1) and a master control microprogram used to control the master control system, a slave control microprogram used to control each slave control system, and a slave for transferring the slave control microprogram to the slave control system A non-volatile memory (29) storing a microprogram for data transfer and an I / O controller (2) for controlling input / output of a master control system.
2) is provided, and the MPU (processor) that controls the slave control system etc. in the slave control system
(24), a volatile memory (31) for storing a slave control microprogram transferred from the master control system, and an I / O control unit (2) for controlling input / output of the slave control system.
5) and a communication memory (13) accessible by the master control system MPU (21) and the slave control system MPU (24). Via the communication memory (13)
Transfer to the volatile memory (31) of each slave control system,
A device having a master / slave control system, characterized in that the nonvolatile memory (29) is shared by the master / slave control system by controlling each slave control system. 2. The slave control system is provided with an address switching circuit (28) for switching the address area accessed by the MPU (24) of the slave control system, and the address area accessed by the MPU (24) of the slave control system. When the control of the MPU (24) is started, the communication memory (13) is switched to be accessible, and the slave control microprogram is stored in the volatile memory (3
The device having a master / slave control system according to claim 1, wherein the volatile memory (31) is switched to be accessible after the transfer to (1). 3. The flash ROM in the master control system
(16) is provided, and when each microprogram of the non-volatile memory (29) is updated by the host device, the microprogram is updated to the flash ROM (1
6. The device having a master / slave control system according to claim 1, wherein the microprograms of the master control system and the slave control system can be updated by downloading to 6). 4. An MPU for controlling a master control system, comprising one master control system and one or more slave control systems.
(21) and a non-volatile memory (29) are provided, and the slave control system includes an M for controlling the slave control system.
A master / slave provided with a PU (24) and a volatile memory (31) and a communication memory (13) accessible by the master control system MPU (21) and the slave control system MPU (24) In a device having a control system: In advance, in the nonvolatile memory (29) of the master control system,
Data such as a master control microprogram used to control the master control system and a slave control microprogram used to control each slave control system is stored in advance: When the power is turned on, the master control system outputs MPU (21 )
Reads the slave control microprogram from the non-volatile memory (29) and transfers it to the communication memory (13): After that, in the slave control system, the MPU (24)
The slave control microprogram in the communication memory (13) is transferred to the volatile memory (31): After the transfer is completed, in the slave control system, the MPU (24)
The master / slave characterized by switching the address area to be accessed by selecting the volatile memory (31) and starting the control by the MPU (24) by the slave control microprogram of the volatile memory (31). A method for controlling an apparatus having a control system. 5. In the master / slave control system, for slave data transfer for transferring a slave control microprogram to the slave control system, in addition to the microprogram, in a nonvolatile memory (29) of the slave control system. Stores a micro program: When the power is turned on, only the master control system MPU (21) is operated, and the slave control system MPU (24) is kept in the halt state (operation stopped state). Then, the MPU (21) reads the microprogram for data transfer from the non-volatile memory (29) and transfers it to the communication memory (13): Then, in the master control system, the MPU (21) performs slave control. The system MPU (24) is released from the halt state to start control, and the master control system MPU (24 1), from the non-volatile memory (29) reads out the slave control micro program, and transfers the communication memory (13), - the slave control system, after releasing the halt status, MPU
(24) starts control in the communication memory (13), and transfers the slave control microprogram in the communication memory (13) to the volatile memory (31) by the data transfer microprogram. 5. A method for controlling an apparatus having a master / slave control system according to claim 4.