JPH03236697A - Video signal converter - Google Patents

Abstract

PURPOSE:To obtain a synthesis moving picture by storing a video signal corresponding to each picture into each frame memory, storing Y, R-Y to a 1st field memory and Y, B-Y into a 2nd field memory and reading them in the unit of fields. CONSTITUTION:Y, R-Y and Y, B-Y of input picture data VD1-VD4 are written in line memories 10A-10D for one horizontal line each by using a prescribed write clock for each horizontal period according to a prescribed format. Moreover, the Y, R-Y or Y, B-Y for one horizontal line are read from the line memories 10A-10D by using a prescribed read clock and written in frame memories 12A-12D. Each frame memory is formed to be 2-layer structure consisting of the 1st field memory M0 for the Y, R-Y and the 2nd field memory M1 for the Y, B-Y. Then the data for 2 lines are outputted to a conventional receiver from both the memories via output terminals 70, 72, 74 while arranging the time to synthesize 4 moving pictures into one picture.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal conversion device, and particularly to a GLT for converting a video signal whose information has been compressed in a predetermined format into a normal video signal. [Prior Art] FIG. 11 shows an example of an image format to which the present invention is applied. According to this format, the sampling clock (frequency) is 13.5MHz v
For each frame image consisting of 858 pixels in the direction and 525 lines in the Y (vertical) direction, the luminance signal Y and color difference signals R-Y, B are processed in the X direction using band compression technology. -Y pixels are 352 and 178 respectively
, 176 pieces, Y, RY in the Y direction. B-Y is 2i+23 (i=o,...
・・239), 4i+23 (i=o, ・・・・・
・119), 4i 125 (i=o,...
119). In other words, according to this format, there are 240 (2i+23) horizontal lines in one frame in a non-interlaced manner.

[23], [25], ... [499], [5011
is given, and among them, Y for 352 pixels is given for each horizontal line [23], [27], ... [499] of the first set (4i + 23), and the pixels following that Y are given. Given 176 pieces of RY, the second set (4i+
25), each horizontal line [25], [29], ... [
In 5011, Y for 352 pixels is given, and subsequently, B-Y for 176 pixels is given. Such a format is used, for example, in information compression for recording images on a CD-ROM. [Problems to be Solved by the Invention] By the way, it is not possible to record a video signal in the format as described above on a CD.
-Even if it is reproduced from ROM etc., the luminance signal Y and the color difference signal R-
Since the times of Y and B-Y are different from each other, it cannot be displayed on a normal television receiver as it is. Also, even if you perform interlace conversion and enlarge the display, the number of Y pixels is (352
X240), the number of pixels of R-Y, B-Y is (178x12
0), high-density moving images cannot be obtained. The present invention has been made in view of such problems, and the luminance signal Y is provided in a non-interlaced manner within one frame, and color difference signals R-Y, B- are provided following Y during each horizontal period. It is an object of the present invention to provide a new video signal conversion device for converting a video signal in a format in which Y is given selectively and alternately into a video signal that can be enlarged and displayed as a high-density moving image on an ordinary television receiver. purpose. [Means for Solving the Problems] In order to achieve the above object, the first video signal conversion device of the present invention provides a luminance signal Y within one frame in a non-interlaced manner, and provides a luminance signal Y during each horizontal period. A video signal for converting a video signal in a format in which a luminance signal Y is followed by color difference signals R-Y and B-Y selectively and alternately into a video signal that can be displayed as a moving image on a television receiver. A signal conversion device, wherein each frame memory includes a first field memory for storing Y and R-Y of the video signal and a second field memory for storing Y and B-Y of the video signal. mutually independent first, second, third and fourth frame memories consisting of memories; Second. 3rd and 4th
Y, R-Y, which is simultaneously written to the frame memory of , and given in a pair of consecutive horizontal periods for each video signal
and write control means for writing Y, B-Y into the first and second field memories of each frame memory at mutually corresponding addresses; The first corresponding to the screen
(Y)i, (Y)i for two lines each from the first and second field memories of the frame memory of
+1, one line of (RY)l and one line of (
B -Y )1+1 is read out, and two lines of (Y)i, (
Y)1+1. (R-Y)i and 1 for one line
The line (B - Y ) ill is read out, and in the second half of the first field, two lines of (Y )j, (Y)
j+1. One line of (R-Y)j and one line of (B-Y)j+1 are read out, and two lines of data are read out from the first and second field memories of the fourth frame memory corresponding to the lower right screen. (Y)j,
(Y)j+1. One line of (R-Y)j and one line of (B-Y)ill are read out, and in the first half of the second field at the time of reading, the first and second fields of the first frame memory are read out at a constant cycle. (RY)ill for one line and (Y')i for two lines from the field memory. (Y′)i, Ill, (B −Y
)1 and one line of (RY)ill and two lines of (Y')i from the first and second field memories of the second frame memory, respectively.
1, (Y')i, t+1.1 line (B -
Y)1 is read, and in the latter half of the second field, (R-Y)j for l life is read from the first and second field memories of the third frame memory at a constant cycle.
+1 and 2 lines [(Y')i, J, (Y')
i, j+1, one line of (B-Y)j is read out, and one line of (R-Y)j+ is read from the first and second field memories of the fourth frame memory, respectively.
(Y') i, j, (Y') i, j for 1 and 2 lines
+1, a read control means for reading one line of (B-Y)j; in the first half of the first field at the time of reading, the first and second field memories of the first frame memory are read out during a certain period; (Y)i, (Y)i+1, 1 for two lines read out in a predetermined order.
(RY) f for one line, (B - Y) for one line
ill and the first and second field memories of the second frame memory for two lines read out in a predetermined order (Y)i, (Y)i11. Input (R-Y)i for one line and (B-Y)ill for one line, and (Y)+, (R
-Y)+, (B-Y)irl are output at the same time and (Y)1 during the next horizontal period.
+x, (RY)+, (B-Y)x+t
are output simultaneously at the same time, and in the second half of the first field, two lines of (Y )j, (Y)jul, 1
(R-Y)j for one line, (B-Y) for one line
(Y)j, (Y)jel for two lines read out from the first and second field memories of the fourth frame memory in a predetermined order, (R-Y)j for one line, Input (B - Y)jul for one line, and (Y)j, (R
-Y)j, (B-Y)jul are output simultaneously at the same time, and (Y)ju is output during the next horizontal period.
l, (RY)j, (B-Y)jel are output at the same time and at the same time, and in the first half of the second field during reading, the first and second frames of the first frame memory are output during a certain period. (Y ′)i, i, (Y ′)i, for two lines read out in a predetermined order from the field memory of
(R-Y) for i+1.1 lines, (B-Y) for 1411 lines, and (B-Y) for 2 lines read out in a predetermined order from the first and second field memories of the second frame memory. Y')i, , (Y')i, 1+1,
(R-Y)i+1 for 1 line, (R-Y) for 1 line, (
B-YLI is input and (Y'
)i, , (RY)i+t, CB-Y)i are output simultaneously at the same time, and (Y') is output during the next horizontal period.
i, ++t, (RY)i+1, (B-Y)i are output simultaneously with the same time, and in the second half of the second field, the first and second frames of the third frame memory are output for a certain period of time. Two lines of (Y')i, j, (Y')i, J+ plate, one line of (R-Y)jel, and one line of (B-) read out in a predetermined order from the field memory.
Y)j and two lines of (Y')i, J, (Y')i, jel, read from the first and second field memories of the fourth frame memory in a predetermined order.
(R-Y) gel for 1 line, (B
-Y)j, and during the next horizontal period (Y
')i,, (RY)jel. (B - Y )j are output at the same time and at the same time, (Y')i, ++t, (R
-Y)++t. The configuration includes a delay means for simultaneously outputting (B-Y)i at the same time. A suitable write control means for writing to the frame memory in the above video signal conversion device includes a presettable address counter and a control means for writing Y and RY to the first field memory of each frame memory. address storage means for storing the first write address;
address loading means for loading the stored first write address into the counter to generate the same write address as for Y and R-Y when writing Y and B-Y to the field memory; The structure includes address output means for simultaneously supplying the write address generated by the counter to the first, second, third, and fourth frame memories. Further, in the above-mentioned video signal conversion device, suitable readout control means for reading out the frame memory includes a presettable address counter, and in the first half of each field, Y, R-Y, or Y '
When reading BY, the first read address is stored, and in the second half of each field, Y9R-Y or Y' is stored from the third frame memory, and when BY is read, the first read address is stored. storage means; in the first half of each field, when reading Y, R-Y or Y, B-Y from the second frame memory, the stored first address is loaded into a counter;
A read address that is the same as the read address of the frame memory is generated, and in the second half of each field, when reading Y", R-Y, or Y" B-Y from the fourth frame memory, the stored first address is used. The structure includes address loading means for loading a counter to generate a read address that is the same as the read address of the third frame memory. [Operation] In the present invention, four frame memories are provided corresponding to four screens, and each frame memory is configured with two layers of field memories. The video signal corresponding to the upper left screen is stored in the first frame memory, its Y and R-Y are stored in the first field memory, and its Y and B-Y are stored in the second field memory. . At this time, Y, R-Y and Y, B-Y given in a pair of consecutive horizontal periods are respectively written into the first and second field memories at mutually corresponding addresses. A suitable write control circuit for such writing first stores the start address when writing Y and RY to the first field memory, and then stores Y and B-Y to the second field memory. When writing, by loading the first address stored by writing R and R-Y into the counter, the same write address is input to Y and R from the address counter.
-Give to write Y and Y, B-Y. For other screens (upper right screen, lower left screen, lower right screen), the respective video signals are simultaneously written to the 2nd to 4th frame memories at the write addresses corresponding to the 1st frame memory using the same action as above. . Reading from the frame memory is performed field by field. In the first half of the first field, at a predetermined period (every two horizontal periods), two lines of (Y)
, 1. (Y)1+I, 1. 1 line (RY
) i, l, one line of (B − Y )1+l, 1 is read out, and two lines of (Y ) i, 2. (Y)i+1, 2, (RY)i for 1 line, 2. 1 line (B
-Y)i+1,2 are read. These data are once input to the delay means, and from there, (Y)i, 1+ (Y)i, 2 . (RY)i,
1+ (RY)i, 2. (B-Y)i+1, 1+
(B-Y)i+1.2 are output simultaneously at the same time, and during the next l horizontal period (Y)f+1,1+ (Y)
1+1,2. (RY)i, l+ (RY)
i, 2. (B-Y)i+1.1+ (B-Y)i+
1 and 2 are output at the same time with the same time. In the second half of the first field, at a predetermined period (every two horizontal periods), two lines of (Y) are sent from both field memories of the third frame memory corresponding to the lower left screen in a predetermined order.
j, 3. (Y)j+1.3. One line of (R-
Y)j, 3.1 lines of (B-Y)jul, 3 are read out, and 2 lines of (Y) are read out in a predetermined order from both field memories of the fourth frame memory corresponding to the lower right screen. j, 4. (Y) jul, 4° (R-Y) j for 1 line, (B-Y) jul for 4.1 line
, 4 are read out, these data are once input to the delay means, and from there, (Y)7.3+ is read out during one horizontal period.
(Y)j, 4. (RY)j, 3+ (RY)j
, 3. (B-Y)j+1.3+ (B-Y)jul
, 4 are output at the same time, and during the next horizontal period (Y)jul, 3+ (Y)j+1.4 . (R-
Y)j, 3+ (RY)j, 4. (B-Y)ju
l, 4+ (B-Y)jul, 4 are output at the same time and at the same time. In addition, in the first half of the second field, at a predetermined period (every two horizontal periods), two lines of (Y')i, +
, 1. (Y')i, ++t, t, CB-YH for one line, l, (R-Y) for l life 1+1,1
At the same time, two lines of (Y') are read out in a predetermined order from both field memories of the second frame memory.
i. 1, (Y')i, ro + 1, (B-Y) day for 1 line,
l, one line of (RY)i+1. l is read out, these data are once input to the delay means, and from there, (Y')i, (,1+ (Y')i) during one horizontal period.
, 1, 2. , (B-Y)i, 1+ (B-Y)i
, 2. (RY)i+1, 1+ (RY)i
+1 and 2 are output at the same time with the same time, and during the next horizontal period (Y')i, 1+1,1 + (Y')i, I+
1,2 , (B-Y)i,l+ (B-Y)i,2
．． (RY)i+1.1+ (RY)i+1.
2 are output at the same time with the same time. Then, in the second half of the second field, a predetermined period (2
(Y')j,3.
(Y')i, Jul, (B-Y) for 3.1 lines
j, 3. One line of (RY)j+1,3 is read out, and two lines of (Y゛)j,4 are read out in a predetermined order from both field memories of the fourth frame memory.
．． (Y')i, Jul, (B-Y) for 4.1 lines
j, 4. One line of (RY)jul,4 is read out, these data are once input to the delay means, and from there (Y')i,j,3 + (
Y,′)i,1,4. , (B-Y)j, 3+ (B
-Y)j, 4. (RY)j+1.3+ (RY
)j+1.4 are output at the same time and the next 1
During the horizontal period (Y')i, J+1,3 + (Y')i,
j+1,4, (B-Y)j, 3+ (B-Y)j
,4. (RY)j+1.3+ (RY)j+
1.4 are output at the same time and at the same time. Video signals Y and RY thus obtained. When B-Y is applied to an ordinary television receiver, the four videos that were separate before conversion are converted into one high-density, normal-sized (4 times larger than before) video in an interlaced format.
Displayed as two composite videos. In a preferred read control circuit for reading the frame memory as described above, in the first half of the first and second fields, Y, R-Y or Y', B-Y is first read from the first frame memory. At the same time, store the first read address, and then read Y, Y, from the second frame memory.
When reading RY, Y', or BY, the first address stored in the previous first frame memory read is loaded into the address counter, and the read address is started from the first address. As a result, Y, RY, or Y'B-Y is read from the first and second frame memories, respectively, at the same address. 1st
And in the second half of the second field, the same operation is performed from the third frame memory and the fourth frame memory respectively at the same address, Y, R-Y or Y', B-
Y is read out. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the attached drawings. FIG. 1 shows the overall configuration of a video signal conversion device according to this embodiment. This device has four line memories 10 in the input stage.
A~IOD and four frames %IJ12A~12D
, six line memories 14A to 18B in the output stage, and frame memories 12A to 12D (7) a frame memory control circuit 20 for controlling iF loading/reading. Write address generation circuit 30° Read address generation circuit 40. Address switching circuit 50 and output line memory control circuit 60 for controlling writing and reading of output line memories 14A-18B
Equipped with. The line memories IOA, IOB, IOC, and IOD store video signals for four images in the format described above with reference to FIG. 11 from, for example, four CD-ROMs (not shown), respectively, as digital image data VDI, VD2. V.D.
3. VD4 are input in parallel and in synchronization with each other. These video signals cover one tooth surface 4 times horizontally, vertically, and vertically.
It may correspond to each small screen (upper left screen, upper right screen, lower left screen, lower right screen) when divided, and each is provided as a continuous frame image, that is, as a moving image. Each input image data VDI-VD4 is Y, R-VD4 which is given alternately every horizontal period according to the above format.
It is composed of Y, Y, and B-Y. The Y, R-Y or Y, B-Y for one horizontal line is a line memo IJIOA to IOD for each horizontal line with a write clock of 13.5MH2, which is equal to the sampling clock.
The line memory is written in the next horizontal period and read out from the line memory using a 20.25 MHz read clock. In this way, Y, RY or Y, B-Y for one horizontal line output from the line memories IOA to IOD are written to the frame memories 12A to 12D. FIG. 2 shows the address structure of frame memories 12A-12D. Each of these frame memories includes a first field memory M for Y, R-Y storage, as shown.
It has a two-layer structure of O, Y, and second field memory Ml for B-Y storage. Both field memories MO, M1 each have 120 row addresses and (352+176) column addresses. Horizontal line [4i +2
3] YR-Y of (1=0-L...119)
is stored in the 1st to 120th rows of the first field memory MO, and the horizontal line [4i+251 (i=o*i
s...119) are stored in the first to 120th rows of the second field memory Ml. Therefore, a pair of consecutive horizontal lines [4i+
231. Horizontal line [4i+23] per [4i+25]
] Y, RY and horizontal line [4i+25] Y, B-
Y is stored in the first field memory MO9 and second field memory Ml at the same address, respectively. FIG. 3 shows a write address generation circuit 30 according to this embodiment.
Read address generation circuit 401 and address switching circuit 5
A specific circuit configuration example of 0 is shown below. Write address generation circuit 30 and read address generation circuit 40
have the same circuit configuration, and include a multiplexer 32.42 for switching preset values and a presettable address counter 34.42 for updating addresses.
44 and a latch circuit 3 for storing preset values.
6.48. The address switching circuit 50 includes the write address generation circuit 30 and the read address generation circuit 4.
0, and a latch circuit 54 that latches the output of the multiplexer 52 and simultaneously applies it to the frame memories 12A to 12D. In the write address generation circuit 30, the multiplexer 3
2 is the initial value (0000) H from the initial value circuit (not shown) or the latch circuit 36 according to the switching control signal WRESET from the frame memory control circuit 20.
Select any of the output data from. Address counter 34 receives write load signal WLD from control circuit 20.
multiplexer 32 to the set terminal (SET) in response to
is loaded (input) as a preset value, and thereafter counts up in response to the write clock WCK from the control circuit 20, and outputs the counted value from the output terminals QO-15 at 16 bits. Write clock WCK is applied only during writing. The latch circuit 36 stores (latches) the count value (write address) of the counter 34 in response to the rise of the write latch signal WLA from the control circuit 20. 4 and 5 show frame memo 1 according to this embodiment.
The write operation of J12A to J12D is shown. These frame memories write each input data independently ('M, column-wise) at the same write address. Therefore, although one frame memory 12A will be explained as an example, similar write operations are performed in other frame memories 12B, 12C, and 12D. Note that during writing, the address switching circuit 50
The multiplexer 52 switches to the write address generation circuit 30 side in accordance with the switching control signal XQA2 from the control circuit 20. In the horizontal cycle timing of FIG. 4, immediately before data writing, the write latch signal WLA is at "L" level and the write load signal WLD is at "L" level (enabled state).
Figure 4 (F), (G)). . In addition, the switching control signal WRE
When SET is “L” (Fig. 4 (■)), multiplexer 3
2 has been switched to the preset value (0000)H. After a predetermined time from the horizontal synchronization signal, the Y pixel data DO, D1 .・・・・・・・・・
is given to the frame memories 12A to 12D, and in synchronization with this, the control circuit 20 gives the frame memory 1
A write control signal WE and a write clock WCK are applied to the write address generation circuit 2A and the write address generation circuit 30, respectively (FIGS. 4(B), (C), and (D)). Then, the counter 34 of the write address generation circuit 30 receives the first write clock WC.
In response to the rising edge of K, the initial value (0000) from the multiplexer 16 is loaded as a preset value, and thereafter it is increased by one each time the write clock WCK is received.
The count value is sequentially written to the address AO. AI, A2. Output as ... (Figure 4 (E))
. These write addresses are given to the frame memory 12A via the address switching circuit 60, and in the memory 12A, the direct data DI is written to the storage address designated by each write address AI. Immediately after the initial value is loaded into the counter 34, the write load signal WLD becomes disabled (“H”) (
Figure 4 (G)). Also, the write latch signal WLA is “H”
In response to this, the latch circuit 36 stores the write address at that time, that is, the initial value (0000)H. In addition, the switching control signal W
RESET changes to "H" (FIG. 4 (H)), and the multiplexer 32 is switched to the latch circuit 36 side. In addition, in the data DO to D527 input to the field memory MO or Ml (FIG. 4(B)), the first three
52 data DO-D351 are Y pixel data, and the next 176 data D352 to D527 are R-Y or B.
-Y pixel data. FIG. 5 is a timing diagram in terms of frame memory frame period. In this figure, data HO, H1, ... H239 are horizontal lines [23], [25], ... [499], respectively.
, [501], and each data H1 consists of the above data DO-D527 (FIG. 5(C)). The switching control signal WRESET is at the "L" level until the first data is written in the frame (until the first fall of the write clock WCK), and thereafter remains at the "H" level (Fig. 5 (D)). . Therefore, after providing the initial value (0000) H to the write counter 34, the multiplexer 32 loads the address stored in the latch circuit 36 into the counter 34 as a preset value. The write latch signal WLA is applied to each horizontal line [23
], [27], ... When writing Y and RY in [499], the first address AO rises from "L" to "H" periodically so that it is stored in the latch circuit 36. (Figure 5 (F)). The write load signal WLD is applied to the first horizontal line [23] and the second set of horizontal lines [25], [29]...[Y, B of [5011]
When writing -Y, the enable state ("L") is periodically set so that the address AO stored in the latch circuit 36 is loaded into the counter 34 as a preset value (FIG. 5(E)). As a result, when writing one frame of video signal to the frame memory 12A, the write address generated by the write counter 34 is as follows. first horizontal line

For [23], the write address is from AO to A with the initial value (0000)H as the preset value.
Increment up to 131. This creates a horizontal line

[23
] are written in the first line of the first field mesori MO. The write address corresponding to the preset value (initial value) is stored in the latch circuit 36. second horizontal line

For [25], the write address is a horizontal line

Preset value (initial value) same as [23]
Starting from AO and incrementing from AO to A131. This creates a horizontal line

Y and B-Y of [25] are written to the first row of the second field memory M1. third horizontal line

For [27], the write address is a horizontal line

[25] Last write address A 13
Starting from the next address (starting address of the second line) following 1. This creates a horizontal line

[27]Y,
RY is written in the second row of the first field memory MO. During this write, the first address is latch circuit 3.
6 is stored. 4th horizontal line

In contrast to [29], the write address starts from the address loaded into the counter 34, that is, the start address stored in the latch circuit 36. This results in a horizontal line

[29] Y, B-
Y is written to the second row of the second field memory M1. Thereafter, by the same operation as above, Y and R-Y of the first set of horizontal lines (4i+23) and Y and B-Y of the second set of horizontal lines (4i+25) are alternately stored in the first field memory. MO and second field memory M
1 with the same address. Next, reading from the frame memory 12 according to this embodiment will be explained. Reading is performed field by field, first reading the first field, then reading the second field. In the read address generation circuit 40 shown in FIG. Select one of the address noises from. address·
The counter 44 receives a read load signal R from the control circuit 20.
The output of the multiplexer 42 is input as a preset value to the cent terminal (SET) in response to the LD, and thereafter it is counted up in response to the read clock RCK from the control circuit 20, and the count value is sent to the output terminal QO in 16 bits. −
Output from 15. The read clock RCK is applied only during reading. The latch circuit 46 responds to the rise of the read latch signal RLA from the control circuit 20 to
Store (latch) the count value (read address). Further, in FIG. 3, a memory selector circuit 22 is a decoding circuit included in the control circuit 20, and is a decoding circuit included in the control circuit 20.
While receiving the enable signal r1, it decodes the 2-bit screen selection signals C8O and C8t, and selectively outputs one of the frame memory read enable signals 5ELI-8EL4. Kokote, S E Ll Ha upper left screen (picture 11ii 1
), rth corresponds to the upper right screen (screen 2), 5EL3 corresponds to the lower left screen (screen 3), and 5EL4 corresponds to the lower right screen (screen 4), respectively.% When 5ELi is output, frame memory 1
Reading is performed at 2A, when 5EL2 is output, reading is performed at the frame memory 12B, when 5EL3 is output, reading is performed at the frame memory 12C, and when 5EL4 is output, reading is performed at the frame memory 12D. Note that during reading, the multiplexer 52 of the address switching circuit 50 is switched to the read address generation circuit 40 side in accordance with the switching control signal XQA2 from the control circuit 20. FIG. 6 shows the timing of the read operation in the first half of the first field. Before starting reading in each horizontal period, the read latch signal RLA is at “L” level, and the read load signal R
LD is at “H” level (disabled state (“L”)
uH'') (Figure 6 (G), (H)).
When a predetermined period of time has elapsed from the start of the horizontal period, the control circuit 20
The read clock RCK is applied to the read address generation circuit 40 (FIG. 6(B)), and the first frame memory 12
A read enable signal 5ELI is applied to A (FIG. 6(C)). Then, in the read address generation circuit 40, the counter 44 starts from the first address AO and counts up by one each time the read clock RCK is received thereafter, and the count value is successively applied to the read addresses AO, AI.
, A2. ... is output as (Fig. 6 (F)). These read addresses are given to the first field memory MO of the frame memory 12A via the address switching circuit 50, and in this field memory MO, each read address AO, AI. ...Data YO from the memory address specified by A327,
l, Yl,! ,...(R175,1-YI75.1
) is read out. Here, data YO,l −Y35
1,1, (RO,l-Yo.1)~(R175,1-Y175.1) are data DO~D351, DQ~D175 (fourth
(B)), respectively. In this way, in the first half of the horizontal period, the first
From the frame memory 12A of , one line of (Y)i,
1. (RY)i, 1 is read. As described above, from the first frame memory 12A,
When the first data (YO) of R-Y is read out, the read latch signal RLA from the control circuit 20 rises to the "H" level (FIG. 6(G)), so that the data is output from the counter 44 at that time. The read address AO currently stored is stored (latched) in the latch circuit 46. When the reading from the first frame memory 12A is completed, the control circuit 2
The read load signal RLD from 0 is in the enabled state (“L”
”), and the read clock RC given under that condition
In response to the rise of K (FIG. 6(B)), the address AO stored in the latch circuit 46 is loaded into the counter 44 as a preset value via the multiplexer 42. As a result, the counter 44 starts counting again from this preset value AO, and thereafter increases the count value (read address) by 1 in response to the read clock RCK (FIG. 6(F)). On the other hand, when the reading from the first frame memory 12A is completed, the read enable signal 5ELI stops, and the read enable signal 5EL2 is applied instead, thereby putting the second frame memory 12B into the read enable state (the sixth Figure (C
), (D)). In the second half of the horizontal period, the second frame memory 12B corresponding to the - side 2 (upper right screen) reads the same read addresses AO, A2, . ...1 on A327
Line data (Y)i, 2. (RY)i,2 is read. In the next horizontal period, after reading Y from the first field memory MO of each frame memory, switching is made to the second field memory Ml. As a result, with the same read address, one line of (Y)i+1,l, (
B-Y)t+1. l is read out, and in the latter half of the horizontal period, one line of (Y
)ill, 2. (B-Y)ill, 2 is read. In the first half of the first field, the above operation is repeated. In the second half of the first field, screen 3 (lower left screen)
The same read operation as above is performed for the third and fourth frame memories 12C and 12D corresponding to screen 4 (lower right screen), respectively. That is, in the first horizontal period of each two horizontal periods, the third
(Y)j, 3 for l life from the frame memory 12C of
．． (RY)j, 3 is read out, and the fourth
(Y)j for l life from the frame memory 12D of
4. (RY)j,4 is read out, and in the next horizontal period, the third frame memory 1 is read out at the same readout address.
2C for one line (Y)j+1,3. (B
-Y )j+1, 3 are read out, and in the latter half of the horizontal period, one line of (Y)j+1, 4 . (B-Y) 10 folds,
4 is read out. In the second field, the same read operation as in the first field is performed except that the operations of the first and second field memories MO and Ml in each frame memory are switched. That is, as shown in FIG. 7, in the first field, Y is read out from the first field memory MO, whereas in the second field, Y is read out from the second field memory M. Also, in relation to this, in the first field, RY is read out in the previous horizontal period (i) of a pair of horizontal periods, and R-Y is read out in the next horizontal period (i+
1), B-Y is read out, whereas in the second field, B-Y is read out in the previous horizontal period (i), and R-Y is read out in the subsequent horizontal period (i+1). As shown in FIG. 9, in each of the first and second fields, when reading starts for screens 1 and 2 (top left screen, top right screen) and when reading starts for screens 3 and 4 (bottom left screen, bottom right screen), Preset value (0000) in address counter 44
H is loaded, and the counter 44 is set to the initial value (0000) H.
will be reset to In particular, when switching from the upper screen to the lower screen, as shown in FIG. 10, the screen selection signal C8O goes "L" after reading the last data on the upper right screen.
The preset signal PRE rises to “H” from
SET becomes enabled (“L”), and the preset value (0
000)iI is loaded into address counter 44. As a result, the count value (read address) of the counter 44 is reset to the preset value (0000)11. FIG. 8 shows the operation of the output line memories 14A-18B. In the horizontal period HDO, frame memories 12A and 12B
Screen 1. The data in the first row of 2 (
Y)0,1, (RY)0,1, (Y)0,2, (
When R-Y)0.2 is read out, (Y)o, 1 and (Y)0.2 are written to the line memory 14A at a frequency of 20.25MHz, and (R-Y)0. 1 and (R
-Y)0.2 is written to the line memory 16A. In the next horizontal period HDI, the frame memory 12A,
From 12B, data in the second row of screens 1 and 2 as described above (Y)i, 1, (BY)i, 1, (Y) 1, 2
, (B-Y) When 1.2 is read, 20.
With a 25MHz clock, (Y)t,l and (Y)i,2
is written in the line memory 14B, and (B-Y)i,1
and (B-Y)i,2 are written into the line memory 18B. On the other hand, from the line memory 14A, (Y)0.1 and (
At the same time as Y)0.2 is read out with a 13.5 MHz clock, (RY)0.1 and (RY)0.2 are read out from the line memory 18A with a 675 MHz clock. In the next horizontal period HD2, the frame memory 12A,
From 12B, data (Y) 2.1, (R-Y) 2. of the third row of screens 1 and 2 is obtained as described above. t. When (Y)2,2 and (RY)2.2 are read out,
(Y)2.1 and (Y)2.2 are written to the line memory 14A, and (RY)2.1 and (RY)2.2 are written to the line memory IE3B. On the other hand, from the line memory 14B, (Y)i,1 and (Y)i,2 are 13.5MH
The line memory 16 is read at the same time as the clock of z.
From A, (RY)0.1 and (RY)0.2 are 6.7
Read with 5MHz clock, line memory 18B
From (B-Y)i, 1 and (B-Y)i, 2 is 8.75M
It is read out using a Hz clock. In this way, in the first half of the first field, the 2 field memories MO and Ml of the first frame memory 12A corresponding to screen 1 (upper left screen) are read out in a predetermined order every two horizontal periods. (Y)i for the line, 1. (
Y) i+1, 1. (RY)i for one line, 1.
1 line of (B - Y) t+t, t, and screen 2
(Y)i, 21 (Y)i+ for two lines read out in a predetermined order from both field memories MO, Ml of the second frame memory 12B corresponding to (upper right screen)
1, 2. (R-Y)i for one line and (B-Y)l+1,2 for 2.1 lines are stored by the line memories 14A to 18B during one horizontal period under the control of the output line memory control circuit 60. (Y)i, 1+ (Y)i, 2°(RY)i, x+ (RY)i, 2. (B-Y
)i+1, *+(B −Y )i+1, 2 are output at the same time, and during the next horizontal period (Y)i+1,
l+ (Y)1+1.2. (RY)i, l+
(RY)i, 2. (B-Y) i+t, t+
(B-Y)i+1 and 2 are output at the same time at the same time. In addition, in the second half of the first field, every two horizontal periods,
Third frame memory 1 corresponding to screen 3 (lower left screen)
Two lines of (Y)j read out in a predetermined order from both field memories MO and M1 of 2C, 3. (Y
)l+1,3. (R-Y)j for one line, (B-Y)l+1.3 for 31 lines, and both field memories MO and Ml of the fourth frame memory 12D corresponding to screen 4 (lower right screen). Two lines of (Y)j read out in the order of (Y)j, 4. (Y)l+1.4
(RY)j for one line, 4. 1 line (B-
Y)j+t, 4 are processed by the line memories 14A to 18B under the control of the output line memory control circuit 60 during one horizontal period. (RY)j
, 3+ (RY)j, 3. (B-Y)l+1.3+
(B-Y)l+1.4 are output at the same time and at the same time,
During the next horizontal period (Y)l+1, 3+(Y)l+1,
4. (RY)j, 3+(RY)j, 4. (
B-Y)l+1,4+ (B-Y)l+1.4 are output at the same time with the same time. Also, in the first half of the second field, every two horizontal periods,
Both field memories MO of the first frame memory 12A
, Ml for two lines (Y
′)i,I,1,(Y′)i,1+I,1
．． (B-Y)i for 1 line, (R-
Y)l+1.1, and two lines of (Y')i, I, 1. (Y
')i, 141.1, (B-Y)i, 1 for 1 line
．． (R-Y)i+1,1 for one line is stored as (Y')i, by line memories 14A to 18B during one horizontal period.
1.1 + (Y′)i,! , 2. ．． (B-Y)i
, 1+ (B-Y)i, 2. (RY)l+1,
1+ (R-Y)i+1, 2 are output at the same time after a while, and (Y')i, I+1, 1 are output during the next horizontal period.
+ (Y')i, I+1, 2. (B-Y)t, 1+ (
B-Y)i, 2. (RY)l+1. I+ (R-
Y) 1+1.2 are output at the same time with the same time. Then, in the second half of the second field, the two field memos UMO, UMO, of the third frame memory 12C are
Two lines (Y′
) i, i, 3. (Y“)i+1, 3.1 lines of (B
-Y)i, 3. (RY) DI for one line,
3, and two lines of (Y')i,I,4. (Y′)i, Il
l, 4.1 line of (B-Y)i, 4. (R-Y)1+1.4 for one line is from line memory 14A to
18B, (Y')i, 1.3 + during one horizontal period
(Y')i, 1, 4. , (B-Y)i,3+ (B-
Y) i, 4. (RY)1+1.3+(RY)i
+1 and 4 are output at the same time with the same time, and during the next horizontal period (Y')i, I+1, 3 + (Y')i, I+1
,4, (B-Y)i,3+ (B-Y)i,t,
(RY)i+1, 3+ (RY)i+1, 4 are output at the same time with the same time. In this way, when the video signals Y, RY, and B-Y obtained at the device output terminals 70, 72, and 74 are applied to a normal television receiver, the four moving images are combined into one normal-sized moving image. and displayed in interlaced format. In this composite screen, the number of pixels of Y is (352X2X240X2)
So, R-Y. The number of pixels of B-Y is (178X2X120X2),
High-density images can be obtained even when enlarged. [Effects of the Invention] By having the above-described configuration, the present invention provides the following effects. According to the video signal conversion device of the first aspect, four frame memories each consisting of two layers of field memories are provided for four screens, and both field memories of each frame are provided with Y, R-Y, or B-Y, respectively. are written at addresses corresponding to each other, and in the first half of the first field when reading, the first and second fields corresponding to the upper left screen and upper right screen are written at a constant cycle.
(Y)i, 1 . for two lines from the first and second field memories of the frame memory respectively. (Y)l+
1. I. (Y)i, 2. (Y)l+1.2. (RY)i for one line, 1. (RY)i, 2. (B - Y )l+1, 1 (B -Y )l+1 for one line.
2, and the delay means reads (Y) during l horizontal period.
i, 1+ (Y)i, 2. (RY)i, 1+ (
R-Y)i, 2. (B-Y)l+l,l+ (B-
Y) If 1 + ■, 2 are output at the same time with the same time, 1
(Y)1+1.1+ (Y)l+ during the next horizontal period
1.2. (RY)+, l+ (RY)i, 2.
(B-Y)1+1. t+(B-Y)l+1,2 are output simultaneously at the same time, and in the second half of the first field, the first and fourth frames of the third and fourth frame memories corresponding to the lower left screen and lower right screen are output at a constant cycle. (Y)j, 3.2 lines each from the second field memory. (Y)
l+1,3. (Y)j, 4°(Y)jul, 4.
(RY)j for one line, 3. (RY)j, 4.
(B-Y)l+1.3 for one line. (B-Y)
jul, 4 is read out, and (Y)j, 3+ (Y)j, 4. (RY)j,
3+(RY)j, 4. (B-Y)jul, 3+(B-
Y)l+1.4 are output at the same time and (Y)jul, 3+ (Y)jul during the next horizontal period.
,4. (RY)j, 3+ (RY)j, 4.
(B-Y)jul, 3+ (B-Y)jul, 4 are output simultaneously at the same time, and in the first half of the second field, the first and second frames of the first and second frame memories are output at a constant period. 2 lines each from field memory (
Y')i, 1, 1. (Y′)i, 1.2. (Y')
i, 1+1, l, (Y')i, l+1.2.1 line of (B-Y)i, 1°(B-Y)i, 2.1
(RY)l+1 for the line. t, (RY)l
+1, 2 is read and the delay means calculates (Y')i, t, 1+ (Y')i, t, z, (B-Y
)t, s+ (B-Y)i, 2. (RY)1+1
, 1+ (R-Y)l+1.2 are output simultaneously at the same time, and (Y')i, I+ are output during the next horizontal period.
I, l + (Y ′) i, l+1, 2. (B-Y
)*, t+ (B-Y)i, 2. (RY)l
+1, 1+ (RY) 1+1, 2 are output at the same time at the same time, and in the latter half of the second field, 2 are output from the first and second field memories of the third and fourth frame memories at a constant cycle. (Y ′)i for the line,
J, 3. (Y')i, J, 4. (Y′)i, l+
1,3. (Y')i, Jul, 4.1 lines of (B
-Y)j, 3. (B-Y)j, 4. (RY)jul for one line, 3. (RY)jul, 4 is read out, and (Y”)j, is read out during one horizontal period by the delay means.
3 + (Y')i, J, 4. (B-Y)j, 3+
(B-Y)j, 4. (RY)jul, 3+ (R-
Y)jul, 4 are output simultaneously at the same time, and (Y')i, Jul, 3 + is output during the next horizontal period.
(Y')i, Jul, 4. (B-Y)j, 3+(B-
Y)j, 4. (RY)l+1.3+ (RY
)jul, 4 are output at the same time at the same time, so the four videos before conversion can be made into one composite video using the EtaRase method and displayed with high density on a regular TV receiver at a regular screen size. I can do it. According to the video signal conversion device of claim 2, the device includes a presettable address counter, and in the device of claim 1,
Y, R-Y in the first field memory of each frame memory
When writing , store the first write address, and then when writing Y, B-Y to the second field memory, load the stored first address into the address counter and write the first address. By starting from the first . The corresponding address of the second field memory can be written to. According to the video signal conversion device of claim 3, the device includes a presettable address counter, and in the first half of the first and second fields during reading in the device of claim 1, the first
Y from frame memory. When reading R-Y, Y', or B-Y, store the first read address, and then store the first read address when reading Y, R-Y, or Y'B-Y from the second frame memory. By loading the first address stored in frame memory reading into the address counter and starting the read address from the first address, Y, R-Y or Y', B-Y are read, and in the second half of the first and second fields, Y, R-Y or B-Y are read from the third and fourth frame memories at mutually corresponding addresses by similar operations. Since the signals Y" and B-Y are read out, complex readout control can be performed with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a video signal conversion device according to an embodiment of the present invention, FIG. 2 is a diagram showing the address structure of each of the frame memories 12A to 12D of the embodiment, and FIG. , a block diagram showing a specific configuration of a circuit that controls writing and reading of the frame memories 12A to 12D, FIG. 4 is a timing diagram for explaining the write operation of the frame memories 12A to 12B, and FIG. , a timing diagram showing the write operations of the frame memories 12A to 12D in frame cycles, FIG.
FIG. 7 is a timing diagram for explaining the read operation of frame memories 12A to 12D according to the embodiment.
FIG. 8 is a timing diagram showing the operation of the line memories 14A to 18B according to the embodiment, and FIG. )iI, FIG. 10 is a diagram showing the loading timing of preset value (0000)H when switching from the main screen to the lower screen in the reading operation of the embodiment, and FIG. FIG. 2 is a diagram showing an image format of a pre-conversion video signal to which the present invention is applied. 12A-12D... Frame memory, MO, Ml.
...Field memory, 14A to 18B...Line memory, 20...Frame memory control circuit, 22
... Memory select circuit, 30 ... Write address generation circuit, 32 ... Multiplexer, 34 ... Address counter, 36 ... Latch circuit, 40 ... Read address generation Circuit, 42... Multiplexer, 44... Address counter, 46... Latch circuit, 50... Address switching circuit, 52... Multiplexer, 54... Latch circuit, 60 ...Output line memory control circuit.

Claims (3)

[Claims] (1) The luminance signal Y is given in a non-interlaced manner within one frame, and the color difference signals R-Y and B-Y are alternatively and alternately given after the luminance signal Y during each horizontal period. This is a video signal converter for converting a video signal in such a format into a video signal that can be displayed as a moving image on a television receiver, wherein each frame memory stores Y, R-Y of the video signal. first, second, third, and fourth frame memories each consisting of a first field memory and a second field memory for storing Y and B-Y of the video signal; and four frames according to the format. The video signal of the first
, write to the second, third, and fourth frame memories simultaneously, and write Y, R-Y and Y, B-Y given in a pair of consecutive horizontal periods for each video signal at mutually corresponding addresses in each frame. a write control means for respectively writing to the first and second field memories of the memory; and a write control means for writing to the first and second field memories of the memory, respectively, and writing control means for writing to the first and second field memories of the first frame memory corresponding to the upper left screen at a constant cycle in the first half of the first field at the time of reading. (Y)i, l, (Y)i+1, 1, 1 line (R-) from the second field memory, respectively.
Y) i, 1 and 1 line of (B-Y) i+1, 1 are read out, and 2 lines of (Y) are each read from the first and second field memories of the second frame memory corresponding to the upper right screen. i, 2 (Y) i + 1, 2, 1 line of (RY) i, 2 and 1 line of (B-Y
)i+1, 2, and in the second half of the first field, (Y)j, two lines each from the first and second field memories of the third frame memory corresponding to the lower left screen are read at a constant cycle. 3, (Y)j+1, 3, 1
Line (R-Y)j, 3 and 1 line (B-
Y)j+1, 3 are read out, and two lines of (Y)j, 4, (Y) are read from the first and second field memories of the fourth frame memory corresponding to the lower right screen.
)j+1, 4, 1 line of (RY)j, 4 and 1
Lines of (B-Y)j+1, 4 are read out, and in the first half of the second field at the time of reading, one line of (B-Y)j+1, 4 is read out from the first and second field memories of the first frame memory at regular intervals. RY)i+1, 1 and 2 lines of (Y')i, 1, (Y')i+1, 1, 1 line of (B-Y)i, 1 are read out, and the second frame memory is read out. (RY)i+1, 2, and 2 for one line from the first and second field memories, respectively.
(Y') i, 2, (Y') i+1, 2, one line's worth of (B-Y) i, 2 is read out, and in the second half of the second field, the third field is read out at a constant period. 1 each from the first and second field memories of the frame memory.
Lines (R-Y)j+1, 3 and 2 lines (
Y')j, 3, (Y')j+1, 3, 1 line of (B
-Y)j, 3 and one line of (RY)j+1, 4 and two lines of (Y')j, 4 from the first and second field memories of the fourth frame memory, respectively. , (Y')j+1, 4, 1 line (
B-Y) readout control means for reading out the first and second field memories of the first frame memory in a predetermined period in the first half of the first field at the time of readout; (Y) for 2 lines read out
i, 1, (Y)i+1, 1, (R-Y)i for 1 line
, 1, one line of (B-Y)i+1,1 and two lines of (Y)i read out in a predetermined order from the first and second field memories of the second frame memory.
,2,(Y)i+1,2,(RY)i for 1 line,
2. Input (B-Y)i+1,2 for one line, and (Y)i,1+(Y)i,2,(
RY)i, 1+(RY)i, 2, (B-Y)i+1
, 1+(B-Y)i+1, 2 are output at the same time and at the same time, (Y)i+1, 1+(
Y)i+1,2,(RY)i,1+(RY)i,2
, (B-Y)i+1, 1+(B-Y)i+1, 2 are output simultaneously at the same time, and in the second half of the first field, the first and second frames of the third frame memory are 2 lines of (Y)j, 1, (Y)j+1, 1, 1 line of (RY)j, 1, 1 line of (B -Y)j
+1, 1 and 2 lines of (Y)j, 2, (Y)j+1, 2, 1 line of data read out in a predetermined order from the first and second field memories of the fourth frame memory. (RY)j, 2, (B-Y)j+ for 1 line
1, 2, and during the subsequent 1 horizontal period (Y)j,
1+(Y)j, 2, (RY)j, 1+(RY)j,
2, (B-Y)j+1, 1+(B-Y)j+1, 2 are output simultaneously at the same time, and (Y)j+1, 1+(Y)j+1, 2, (R- Y)j,
1+(R-Y)j, 2, (B-Y)j+1, 1+(B-
Y) Output j+1 and j+1 and 2 at the same time at the same time, and in the first half of the second field during reading, the first and second field memories of the first frame memory are output in a predetermined order during a certain period of time. Two lines read (Y')
i, 1, (Y') i+1, 1, 1 line (R-Y)
i+1, 1, (B-Y) i, 1 for one line and (Y' for two lines read out in a predetermined order from the first and second field memories of the second frame memory)
)i, 2, (Y')i+1, 2, 1 line (R-Y
)i+1, 2, input (B-Y)i, 2 for one line, and then (Y')i, 1+(Y)i during one horizontal period
,2,(RY)i+1,1+(RY)i+1,2,
(B-Y)i, 1+(B-Y)i, 2 are output at the same time and (Y')i+ during the next horizontal period.
1,1+(Y)i+1,2,(RY)i+1,1+(
R-Y)i+1, 2, (B-Y)i, 1+(B-Y)i
. line (Y')j, 1, (Y'
) j+1, 1, 1 line of (RY)j+1, 1, 1
line (B-Y)j, 1 and two lines (Y')j, 2, (Y
') j+1, 2, 1 line of (RY)j+1, 2,
Input (B-Y)j, 2 for one line, and then 1
During the horizontal period (Y')j, 1+(Y')j, 2, (R-
Y)j+1, 1+(RY)j+1,2,(B-Y)j
, 1+(B-Y)j, 2 are output simultaneously at the same time, and (Y')j+1, 1+(Y
')j+1, 2, (RY)j+1, 1+(RY)j
1. A video signal conversion device comprising: delay means for simultaneously outputting +1, 2, (B-Y)j, i+(B-Y)j, 2 at the same time. (2) The write control means includes a presettable address counter and an address store means for storing the first write address when writing Y and RY to the first field memory of each of the frame memories. ;When writing Y and B-Y to the second field memory, load the stored first write address into the counter and write Y.
, an address loading means for generating the same write address as for RY, and an address for simultaneously applying the write address generated by the counter to the first, second, third and fourth frame memories. A video signal conversion device comprising: an output means. (3) The read control means includes a presettable address counter, and stores a first read address when reading Y, R-Y or Y, B-Y from the first frame memory in the first half of each field. However, in the latter half of each field, Y', R
- an address store means for storing the first read address when reading Y or Y', B-Y; in the first half of each field, Y
, R-Y or Y, B-Y, the stored first address is loaded into the address counter to generate a read address corresponding to the read address of the first frame memory, and the second half of each field is read. In the section, Y', RY or Y is stored from the fourth frame memory.
', B-Y, an address loading means for loading the stored first address into the counter to generate a read address corresponding to the read address of the third frame memory. The video signal conversion device according to claim 1.