JP3158737B2 - Generating circuit for video signal for still image - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a video signal for a still picture from video signals of first and second fields which are inputted alternately.

[0002]

2. Description of the Related Art In a conventional still image display by a pause function of a VTR or a video disk player, the same video signal as in the first field is output in the second field as shown in FIG. 9A, or as shown in FIG. As described above, the intra-field interpolation video signal (shown by diagonal lines) formed from the pixel signals of the first field in the second field is output, and a frame screen having only the resolution of the field is displayed. This is to prevent a field flicker from appearing in a moving portion or the like due to a movement between fields, which causes image quality deterioration.

[0003]

However, a still image is originally intended for viewing the image at that moment in detail, and the visual resolution of a human is higher than that of a still image. At the time of displaying a still image, there is a problem that the resolution degradation is noticeable.

Accordingly, the present invention provides a circuit for generating a still image video signal capable of displaying a high-resolution still image without the appearance of field flicker.

[0005]

According to the present invention, there is provided a correlation determining circuit for determining a correlation between video signals of first and second fields for each pixel, and a correlation determining circuit for determining video signals of first and second fields. And a switch circuit for alternately selecting the video signal of the first or second field and the video signal output from the adaptive composition circuit for each field based on the determination result of The video signal of the first and second fields constitutes a video signal of one frame of an interlaced system, and the correlation determination circuit is more vertical than the video signal of one of the video signals of the first and second fields. Forming an interpolated video signal whose pixel position in the direction coincides with that of the other field, and interpolating this interpolated video signal with the video signal of the other field. Compared with those for determining a correlation for each pixel. Further, the present invention provides a correlation determining circuit for determining a correlation between video signals of the first and second fields for each pixel, and a video signal of the first and second fields based on the determination result of the correlation determining circuit. An adaptive synthesizing circuit for synthesizing the first and second fields, and a switch circuit for alternately selecting a video signal of the first or second field and a video signal output from the adaptive synthesizing circuit for each field; The video signal of the first field constitutes a video signal of one frame of the interlaced system. In the adaptive synthesizing circuit, the pixel position in the vertical direction of the video signal of one field of the video signal of the first and second fields is the other. An interpolated video signal corresponding to that of the field is formed, and the interpolated video signal and the video signal of the other field are determined by a correlation determination circuit. It is to synthesize for each pixel based on.

[0006]

According to the present invention, a video signal for a still picture is obtained by using video signals of the first and second fields, and a video signal for only the first or second field is used. A relatively high-resolution still image can be displayed.

A video signal obtained by adaptively synthesizing the video signals of the first and second fields on a pixel-by-pixel basis based on the result of the correlation judgment between the video signals of the first and second fields and the video signal of the first or second field. The signal is alternately selected for each field and a video signal for a still image is obtained. In a portion of the video signal of the first and second fields where there is no correlation, a video signal obtained by adaptively combining other video signals is used. By approaching the video signal of the first or second field that is output in the field No. 1, the appearance of field flicker can be prevented.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, an interlaced video signal SV0 reproduced from a VTR or a video disc player is supplied to a field memory 2 constituting a delay circuit (one field period) via an input terminal 1. In the still image display mode, the contents stored in the field memories 2 and 3 are fixed, and the video signal of the same field is repeatedly output in each field.

The video signal SV1 output from the field memory 2 and delayed by one field period is supplied to the delay circuit (1
(Field period), to the field memory 3, the correlation determination circuit 4, and the adaptive synthesis circuit 5,
The video signal SV2 output from the field memory 3 and delayed by two fields (one frame period) is supplied to the correlation determination circuit 4, the intra-field interpolation circuit 6, and the fixed terminal on the a side of the changeover switch 7.

In the interpolation circuit 6, when the video signal SV2 is an odd field video signal, an intra-field interpolation video signal whose vertical pixel position matches that of the even field is formed, while the video signal SV2 is an even field video signal. If it is a video signal, an intra-field interpolated video signal whose vertical pixel position matches that of the odd field is formed (see the second field in FIG. 9B). Interpolated video signal SVc output from interpolation circuit 6
Is supplied to the adaptive synthesis circuit 5.

When a still image is displayed by simply using video signals of an odd field and an even field which constitute a video signal of one frame of the interlace system, there are areas where field flicker is noticeable and areas where the field flicker is not noticeable. Generally, an area where field flicker is noticeable is a moving image area, and an area where the field flicker is not noticeable is a still image area. The correlation determination circuit 4 outputs a correlation determination signal γ as a signal indicating a noticeable ratio of field flicker. The correlation determination signal γ is formed by considering the conspicuous rate of field flicker as the amount of motion between fields.

FIG. 2 shows the configuration of the correlation determination circuit 4. In the figure, a video signal SV2 output from a field memory 3 is supplied to an intra-field interpolation circuit 41 constructed in the same manner as the interpolation circuit 6 described above.
An interpolated video signal SVc is formed as in.
The interpolation video signal SVc output from the interpolation circuit 41
Is supplied to an adder 42, which performs subtraction from the video signal SV1 output from the field memory 2.

Here, the vertical pixel position of the interpolated video signal SVc matches that of the video signal SV1,
In the adder 42, pixel signals existing at the same spatial position in two consecutive fields are sequentially compared.

Output signal of the adder 42 (comparison error signal)
Is converted to an absolute value by an absolute value circuit 43, then multiplied by a predetermined weighting coefficient α by a multiplier 44, and output as a correlation determination signal γ. That is, the correlation determination signal γ is expressed as shown in Expression 1.

[0016]

(Equation 1)

In FIG. 2, the absolute value circuit 43 and the multiplier 44 may be constituted using a ROM conversion table.

Returning to FIG. 1, the correlation judgment signal γ output from the correlation judgment circuit 4 is supplied to the adaptive synthesis circuit 5 as a control signal. In the adaptive synthesis circuit 5, the field memory 2
The output video signal SV1 and the interpolated video signal SVc output from the interpolation circuit 6 are adaptively synthesized according to the correlation determination signal γ to form an adaptive synthesized video signal SVa. That is, the adaptive synthesized video signal SVa is expressed by the following equation (2).
As shown in the figure, the function f of SV1, SVc, and γ (SV1, SV
c, γ).

[0019]

(Equation 2)

As an example of the function f (SV1, SVc, γ), the function shown in Equation 3 can be considered. Here, Th is a threshold, and β is a certain coefficient.

[0021]

(Equation 3)

FIG. 3 shows the configuration of the adaptive synthesis circuit. In the figure, a video signal SV1 output from a field memory 2 is supplied to a multiplier 51, and an interpolated video signal SVc output from an interpolation circuit 6 is input to a multiplier 5.
2 is supplied.

Reference numerals 53 and 54 denote ROs constituting a conversion table.
The threshold value Th and the correlation determination signal γ output from the correlation determination circuit 4 are supplied to the ROMs 53 and 54 as input address data. The coefficients of (1−γ ′) and γ ′ in the function of Equation 3 are output from the ROMs 53 and 54, and are output from multipliers 51 and 52, respectively.
Supplied to

The output signals of the multipliers 51 and 52 are added by an adder 55, and the adder 55 outputs an adaptive composite video signal SVa based on the function of Equation 3. In the adaptive synthesized video signal SVa, the ratio of the interpolated video signal SVc formed from the video signal SV2 increases and the ratio of the video signal SV1 decreases as the correlation determination signal γ increases and the ratio of the noticeable field flicker increases.

Returning to FIG. 1, the adaptive synthesized video signal SVa output from the adaptive synthesizing circuit 5
Supplied to the fixed terminal on the side. The control signal CTL is supplied to the changeover switch 7 from the control circuit 8. When the control signal CTL is at a low level "0", it is connected to the a side, and when the control signal CTL is at a high level "1", it is connected to the b side. .
As will be described later, the changeover switch 7 is kept connected to the a side in the moving image display mode, and is alternately connected to the a side and the b side for each field in the still image display mode.
The output video signal S is output from the changeover switch 7 to the output terminal 9.
V3 is derived.

The control signal CTL is formed as follows. That is, a field pulse FP indicating the start of each field of the video signal SV0 is supplied to the control circuit 8 from the input terminal 11, and the video signal SV0 is an odd field (odd) or an even field (e).
ven) from the input terminal 12, and a mode identification signal MID from the input terminal 13 indicating whether the display mode is the moving image display mode or the still image display mode. Here, the field identification signal FID has a high level “1” in an odd field and a low level “0” in an even field.
Becomes The mode identification signal MID has a low level “0” in the moving image display mode and has a high level “1” in the still image display mode.

The field identification signal FID is supplied from the input terminal 12 to the register 14. This register 1
4 is supplied with a latch pulse LP from the input terminal 15 at the timing when the display mode is switched. Note that, even though not described above, the display mode is changed in synchronization with the field pulse FP.

The register 14 latches the field identification signal FID with the latch pulse LP, and the signal SLD output from the register 14 is
Supplied to

FIG. 4 shows the configuration of the control circuit 8. In the figure, a mode identification signal MID is supplied to one input terminal of an AND circuit 81. The field pulse FP is supplied to the clock terminal of the D flip-flop 82. The signal obtained at the non-inverting output terminal Q of the flip-flop 82 is supplied to the A-side input terminal of the selector 83. The signal obtained at the inverted output terminal (Q bar) of the flip-flop 82 is supplied to the input terminal on the B side of the selector 83, the data terminal D of the flip-flop 82, and the other input terminal of the AND circuit 81. Control signal CTL is obtained from AND circuit 81.

The signal SLD is supplied to the selector 83 as a control signal. In this selector 83, the signal SLD
Is high level "1", the signal supplied to the input terminal on the A side is selected as the output signal, while the signal SLD
Is low level "0", the signal supplied to the input terminal on the B side is selected as the output signal.

The signal SA output from the selector 83 is supplied to an input terminal on the A side of the selector 84. This selector 84
Is supplied with a field identification signal FID. The selector 84 is supplied with the mode identification signal MID as a control signal. In this selector 84, the signal MID
Is high level "1", the signal supplied to the input terminal on the A side is selected as the output signal, while the signal MID
Is low level "0", the signal supplied to the input terminal on the B side is selected as the output signal. This selector 8
4 outputs a field identification signal FDID.

Next, the operation of the control circuit 8 will be described.

First, the case where the mode identification signal MID is at the low level "0" and the mode is the moving image display mode will be described.

In this case, the mode identification signal MID is at the low level "0" (shown in FIG. 5B), and the control signal CTL output from the AND circuit 81 remains at the low level "0" (FIG. 5C). Illustrated). Further, in this case, the mode identification signal MID is at the low level “0”, and the field identification signal FID supplied from the selector 84 to the input terminal on the B side.
Is output as is as the field identification signal FDID (shown in FIGS. D and E). 5A shows the field pulse FP, and the numbers 0, 1, 2,... Indicate the field numbers.

Next, a case where the mode identification signal MID is at the high level "1" and the mode is the still image display mode will be described. However, it is assumed that the video signal SV2 (SV0) is in the odd field at the timing of switching from the moving image display mode to the still image display mode.

In this case, the mode identification signal MID is at the high level "1" (shown in FIG. 6B), and the signal obtained from the AND circuit 81 at the inverted output terminal (Q bar) of the flip-flop 82 is used as the control signal CTL. It is output (shown in FIG. F).

In this case, the signal SLD becomes high level "1" (shown in FIG. 8E), and is obtained from the selector 83 at the non-inverting output terminal Q of the flip-flop 82 supplied to the input terminal on the A side. The signal is output as a signal SA (shown in FIG. G). The mode identification signal MID is at high level "1", and the output signal SA of the selector 83 supplied to the input terminal on the A side is output from the selector 84 as a field identification signal FDID (shown in FIG. ). 6A shows the field pulse FP, FIG. 6C shows the latch pulse LP, and the numbers 0, 1, 2,... Indicate the field numbers.

Next, the case where the mode identification signal MID is at the high level "1" and the mode is the still image display mode will be described. However, it is assumed that the video signal SV2 (SV0) is in the even field at the timing of switching from the moving image display mode to the still image display mode.

In this case, the mode identification signal MID is at high level "1" (shown in FIG. 7B), and a signal obtained from the AND circuit 81 at the inverted output terminal (Q bar) of the flip-flop 82 is used as the control signal CTL. It is output (shown in FIG. F).

In this case, the signal SLD goes to a low level "0" (shown in FIG. 8E), and is supplied to the inverted output terminal (Q bar) of the flip-flop 82 supplied from the selector 83 to the input terminal on the B side. The obtained signal is output as signal SA (shown in FIG. G). The mode identification signal MID is at high level "1", and the output signal SA of the selector 83 supplied to the input terminal on the A side is output from the selector 84 as a field identification signal FDID (shown in FIG. ). 7A shows the field pulse FP, and FIG. 7C shows the latch pulse LP, and the numbers 0, 1, 2,... Indicate the field numbers.

Returning to FIG. 1, the control signal CTL output from the control circuit 8 is supplied to the changeover switch 7 as described above, and the field identification signal FDID is output to the output terminal 16.

In this example, when the mode identification signal MID is at the low level "0" and the moving image display mode is set, the control signal CTL supplied to the changeover switch 7 becomes the low level "0" and the changeover switch 7 It remains connected to the a side (see FIG. 5C). Therefore, the field memory 3
The output video signal SV2 is output as it is as a video signal SV3 (illustrated in FIG. F).

The field identification signal FDID output to the output terminal 16 is at a high level "1" when the video signal SV3 is an odd field, and is at a low level "0" when the video signal SV3 is an even field. Therefore, it represents the attribute of the video signal SV3 (see FIG. 5D).

Next, when the mode identification signal MID is at the high level "1" and the mode is the still image display mode, the control signal CTL supplied to the changeover switch 7 is alternately set to the low level "0" and the control signal CTL for each field. It becomes high level "1". (A) Consider a case where the video signal SV2 is an odd field at the timing of switching from the moving image display mode to the still image display mode.

In this case, in the odd field, the control signal C
TL becomes low level "0", and the changeover switch 7 is connected to the a side, while in even fields, the control signal CTL becomes high level "1", and the changeover switch 7 is connected to the b side (see FIG. 6F). ). Therefore, the video signal SV2 is output as the video signal SV3 in the odd field, while the adaptive combined video signal SVa is output as the video signal SV3 in the even field (illustrated in FIG. 6I).

FIG. 8A shows the relationship between the video signal SV3 and the video signals SV2 and SV1, where the odd field of the video signal SV3 is the video signal SV2 itself, and the even field of the video signal SV3 is formed from the video signal SV2. An adaptive synthesized video signal S obtained by adaptively synthesizing an interpolated video signal SVc (see a hatched circle) and a video signal SV1.
Va.

The field identification signal FDID output to the output terminal 16 is at a high level "1" when the video signal SV3 is an odd field, and is at a low level "0" when the video signal SV3 is an even field. Therefore, it represents the attribute of the video signal SV3 (see FIG. 6H). (B) Consider a case where the video signal SV2 is an even field at the timing of switching from the moving image display mode to the still image display mode.

In this case, in the even field, the control signal C
TL becomes low level "0" and the changeover switch 7 is connected to the a side, while in odd fields, the control signal CTL becomes high level "1" and the changeover switch 7 is connected to the b side (see FIG. 7F). ). Thus, in the even field, the video signal SV2 is output as the video signal SV3, while in the odd field, the adaptive combined video signal SVa is output as the video signal SV3 (shown in FIG. 7I).

FIG. 8B shows the video signals SV3 and SV2,
The relationship of SV1 is shown, the even field of the video signal SV3 is the video signal SV2 itself, and the odd field of the video signal SV3 is the interpolated video signal SVc (see the hatched circle) formed from the video signal SV2 and the video signal SV1. Is adaptively synthesized into an adaptively synthesized video signal SVa.

The field identification signal FDID output to the output terminal 16 becomes low level "1" when the video signal SV3 is an even field, and becomes high level "0" when the video signal SV3 is an odd field. Therefore, it represents the attribute of the video signal SV3 (see FIG. 7H).

In this example, in the still image display mode, the video signal SV2 and the adaptive combined signal SVa are alternately output to the output terminal 9 as the video signal SV3 every field. In the adaptive combined signal SVa, the ratio of the interpolated video signal SVc formed from the video signal SV2 increases and the ratio of the video signal SV1 decreases as the correlation determination signal γ increases and the field flickering ratio increases.

Therefore, according to the present embodiment, a video signal for a still image is obtained by using the video signals of the odd and even fields, and a high-resolution still image can be displayed. The video signal SV1 in the adaptive synthesized video signal SVa increases as the field flicker becomes more conspicuous.
, The appearance of field flicker can be prevented.

[0053]

According to the present invention, a video signal for a still picture is obtained by using video signals of the first and second fields, and only the video signal of the first or second field is used. A still image with a higher resolution than that of a still image can be displayed.

Also, the video signal of the first or second field and the video signal of the first or second field adaptively synthesized with the video signal of the first and second fields on the basis of the correlation judgment result of the video signal of the first and second fields. The signal is alternately selected for each field and a video signal for a still image is obtained. In a portion of the video signal of the first and second fields where there is no correlation, a video signal obtained by adaptively combining other video signals is used. By approaching the video signal of the first or second field that is output in the field of, the appearance of field flicker can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a correlation determination circuit.

FIG. 3 is a block diagram illustrating a configuration of an adaptive synthesis circuit.

FIG. 4 is a block diagram illustrating a configuration of a control circuit.

FIG. 5 is a timing chart showing the operation of the control circuit in the moving image display mode.

FIG. 6 is a timing chart showing an operation of the control circuit in a still image display mode.

FIG. 7 is a timing chart showing the operation of the control circuit in the still image display mode.

FIG. 8 is a diagram for explaining an output video signal in a still image display mode.

FIG. 9 is a diagram for explaining a conventional still image display in a VTR or the like.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2, 3 Field memory 4 Correlation judgment circuit 5 Adaptive synthesis circuit 6 In-field interpolation circuit 7 Changeover switch 8 Control circuit 9 Delay circuit 10 Output terminal

──────────────────────────────────────────────────続 き Continued on the front page (72) Kunio Kawaguchi, 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Akemi Noda 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-1-175385 (JP, A) JP-A-2-17986 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N5 / 91-5/956

Claims (2)

(57) [Claims] 1. A correlation determining circuit for determining a correlation between video signals of a first and a second field for each pixel, and a video signal of the first and second fields based on a determination result of the correlation determining circuit. An adaptive synthesizing circuit for synthesizing each pixel; and a switch circuit for alternately selecting a video signal of the first or second field and a video signal output from the adaptive synthesizing circuit for each field. The video signal of the first and second fields constitutes a video signal of one frame of the interlaced system, and the correlation determination circuit is more vertical than the video signal of one of the video signals of the first and second fields. An interpolated video signal whose pixel position coincides with that of the other field is formed. Generator of still picture video signal and judging the correlation to each pixel compares the signal. 2. A correlation judging circuit for judging a correlation between video signals of first and second fields for each pixel, and a video signal of the first and second fields based on a judgment result of the correlation judging circuit. An adaptive synthesizing circuit for synthesizing each pixel; and a switch circuit for alternately selecting a video signal of the first or second field and a video signal output from the adaptive synthesizing circuit for each field. The video signal of the first and second fields constitutes a video signal of one frame of the interlaced system. In the adaptive synthesizing circuit, the video signal of one of the video signals of the first and second fields is more vertical than the video signal of one field. An interpolated video signal whose pixel position coincides with that of the other field is formed. Generator of still picture video signal, characterized by combining for each pixel on the basis of a signal of the determination result of the correlation determination circuit.