JPH03232188A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device with less power consumption in the standby state by providing a voltage decreasing circuit whose output connects to a peripheral circuit. CONSTITUTION:A VCC level drop circuit is connected to other peripheral circuits than VBL, S2P, VGG. In this case, the VCC level drop circuit decreases the level of the power supply for other peripheral circuits than the VBL, S2P, VGG circuits more than the normal VCC level in the standby state to prolong the refresh period without changing the storage state of the memory cell and to make the VBB level (base level) shallow, the leakage from the cell to the substrate is decreased and the channel leakage of a CMOS transistor (TR) is reduced. Thus, the power consumption at the standby state is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to reducing the power consumption of a semiconductor memory device (hereinafter referred to as MOS dynamic RAM) that requires periodic refreshing, particularly during standby.

[Conventional technology]

Conventional MOS dynamic RAMs do not have a structure that changes the Vcc level of the internal circuit.

That is, in the conventional MOS dynamic RAM, refresh is required periodically, and data is periodically rewritten to the memory cells. The internal V at that time
The CC was constant at each part, and there was no step-down or step-up.

[Problem to be solved by the invention]

In recent years, there has been an increasing demand for low standby power type MOS dynamic RAMs that can sufficiently retain information in memory cells even with battery backup, and low power consumption has been a major problem.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor memory device that consumes less power during standby.

[Means to solve the problem]

The semiconductor memory device according to the present invention has a VCC level step-down circuit connected to other peripheral circuits except vBL1S2P and Voa.

[Effect]

The Vee level step-down circuit of the present invention can extend the refresh cycle without changing the storage state of the memory cell by lowering the power supplies of peripheral circuits other than VBL, S2P, and voo to lower than the normal VCC level during standby. Since the VBB level (base potential) becomes shallower, leakage from the cell to the board is reduced, and channel leakage of the CMO3 transistor is also reduced, power consumption during standby can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a Vce step-down circuit showing an embodiment of the present invention. In the figure, Nch transistor (Ia)
(lb) and Pchl-transistor (2a) (2b) constitute a switching circuit of the Vce step-down circuit, and Nch)
The transistor (1a) uses the signal PD that becomes high in the power-down mode as the input signal of the gate, and the gate and source (or drain). The Nch transistor (1b) uses the inverted signal of the PD signal as a gate signal input, has a source (or drain) connected to VCC, and a drain (or source) connected to a peripheral circuit. Peh) For transistor (2a), the inverted signal of RD is used as the input signal of gate 1-, Vec is connected to the source (or drain), and Nc connected to the diode is connected to the drain (or source).
Connected to the gate and source (or drain) of the hh transistor (3). Pch transistor (2b) is RD
The signal is the input signal of the gate, and the source (or drain) is V c (the drain (or source) is connected to the peripheral circuit. (4) is N to invert the RAS and CAS signals.
07 circuit, (5) is the inverted RASCAS signal, W ,
D IN, A address.

This is a NOR circuit that receives a signal as input.

FIG. 2 is a circuit diagram of the memory cell array section of the present invention. In the figure, (6) is a bit line pair, and (7) is a word 1
m! , +81 is the transfer gate, (91 is the Pchh transistor of the sense amplifier, a■ is the N of the sense amplifier
eh) transistor, (11) is Nch transistor, (
12) is the I10 gate.

Next, the operation will be explained.

In the operation timing chart of Figure 3 ζ and @ path of Figure 1 and Figure 2, when RAS is high and CAS is high during standby, and the other W, D IN, and Address signals are all low, PD The signal becomes high level, transistors (la) and (2a) are turned on, transistors (1b) and (2b) are turned off, and the VC of the peripheral circuit is turned on.
The C level is stepped down by the number of stages of diode-connected Nch transistors (3). Thereby, VBB
The level becomes shallower. Refresh failure mode is always H
This is an L error, and leakage from the memory cell to the board is considered, but since the vBB level becomes shallow, it is possible to operate with a longer refresh cycle.

Also, when powering down, vBL N S2P %”
Since the GO power supply voltage remains the same as usual, the storage state of the memory cell remains unchanged, and there is no change in the read margin or the like.

〔Effect of the invention〕

As described above, according to the present invention, during standby, "B"
L % S 2P s ” O (By lowering the power supply voltage other than l, the VBB level becomes shallower and the refresh period can be lengthened, so the standby current is reduced, and the channel leakage of the CMO3 transistor is also reduced, so the same result can be achieved. effective.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a Vce step-down circuit showing an embodiment of the invention of B, FIG. 2 is a circuit diagram of a memory cell array section which is an embodiment of this invention, and FIG. 3 is an operation timing chart of the circuit. In the figure, (la) (lb) is Neh! - Ransistor, (2a) (2b) (Pch) Ransistor, (3)
are diode-connected Nch and transistor, (4) is N07 circuit, (5) is NOR circuit, (6) is pit line pair, (7) is word line, (8) is transfer gate,
(9) is a Peh transistor, Ql (11) is Nch)
- transistor, (12) indicates I10 gate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A semiconductor memory device comprising a V_C_C level step-down circuit whose output is connected to peripheral circuits other than the V_B_L, S_2P, and V_G_G generation circuits.