JPH03231385A - Data carrier - Google Patents

Abstract

PURPOSE:To facilitate the setting of data and to directly write data in a data carrier by controlling the reverberation of a resonance circuit, based on a signal read out of a data reading-out means connected to the resonance circuit. CONSTITUTION:A write/read-out control unit executes waveform shaping of an output of a data receiving circuit 21 and gives it to a shift register 22 of 8 bits. Subsequently, first 2 bits and last 2 bits are compared by digital comparators 23, 24, respectively. In these comparators 23, 24, a discrimination code held in the shift register is provided, and a coincidence output is detected by an AND circuit 25. When a coincidence signal is obtained from the AND circuit 25, the operation of the shift register 22 is stopped and its middle 4 bits are saved in a register 26, and from this register 26, serial data is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data carrier used in an article identification system such as a tool for a machine tool, a part in a factory, a product management system, or a distribution system.

[Conventional technology]

In order to mechanize the management of tools in conventional machine tools and the identification of parts and products on assembly lines in factories, a system for identifying and managing various items such as tool parts and products is required. Therefore, as in Japanese Patent Application Laid-Open No. 1-151832, a data carrier having a memory is provided in the object to be identified, necessary information is written in the memory of the data carrier by data transmission from the outside, and the information is read out as necessary. An article identification system has been proposed.

As shown in FIG. 8, such a data carrier has a resonant circuit 51 connected to a receiving coil, a waveform shaping circuit 52 that shapes the signal obtained from the resonant circuit, and is composed of a gate array, a CPU, etc. Data is written into the memory 54 via the memory control unit 53, or read out based on a given command, and the vibration of the resonance circuit 51 is absorbed by the vibration absorption circuit 55, thereby transmitting the data.

(Problems to be Solved by the Invention) However, such conventional data carriers are configured to be able to mount a relatively large capacity memory. Therefore, the memory control section composed of a gate array, a CPU, etc. becomes complicated, and since a memory with a large capacity is used, the cost cannot be reduced. Therefore, it has the disadvantage that it cannot be used in cases where such a large-capacity memory is not required and a small-capacity memory, for example, a few bits to several tens of bits, is sufficient.

Further, conventional data carriers have the drawback that data cannot be written to them without using a write/read control unit, and data cannot be identified by looking at the data carrier. Furthermore, since it is necessary to back up the data in the memory with a battery, there is a drawback that the lifespan of the data carrier is determined by the battery.

The present invention has been made in view of the problems of conventional data carriers, and it is possible to reduce the capacity and eliminate the need to write data using a write/read control unit, allowing data to be written directly to the data carrier. The technical challenge is to be able to write .

[Means to solve the problem]

The present invention provides a data setting means for setting multiple bits of data, a resonant circuit for receiving an intermittent signal with a constant duty ratio, a waveform shaping circuit for smoothing and shaping the received output obtained by the resonant circuit, and a waveform shaping circuit for smoothing and shaping the received output obtained by the resonant circuit. data reading means for reading data from the data setting means based on a signal with a predetermined duty ratio given by the circuit; and vibration connected to the resonant circuit and controlling reverberation of the resonant circuit based on the signal read from the data reading means. It is characterized by having an absorption circuit.

[Effect]

According to the present invention having such features, arbitrary data is directly written in advance by the data setting means of the data carrier. When receiving data, an intermittent signal with a constant duty ratio is applied from the outside, so that the waveform is shaped by a waveform shaping circuit within the data carrier, and data is sequentially read out based on the pulses. The read signal is then applied to a vibration absorption circuit connected to the resonant circuit to absorb the vibration and transmit the data to the outside.

[Embodiment] FIG. 1 is a block diagram showing the configuration of a data carrier according to an embodiment of the present invention. In this figure, the data carrier has a resonant circuit 1 consisting of a receiving coil L and a capacitor C, and one end of the resonant circuit 1 is connected to a rectifier circuit 2 for rectifying a signal and a voltage detection circuit 3 for detecting its output level. be done. Further, a waveform shaping circuit 4 for shaping the waveform of the signal is connected to the resonance circuit 1. The waveform shaping circuit 4 detects the envelope of the applied signal and discriminates it at a predetermined level to obtain a received signal corresponding to signal discontinuation, and its output is sent to a falling detector 5 and, for example, eight D It is applied to a shift register 6 consisting of flip-flops (FF) 6-0 to 67. Further, the output of the voltage detection circuit 3 is given to these DFFs 6-0 to 6-7 as a reset signal,
Furthermore, a monostable multi-bibreak (MM) 7 is provided. The monostable multi-by-break 7 delays the applied reset signal for a predetermined period of time, and sends the delayed signal to the multiplexers 80 to 80.
Give it to 8-7. Multiplexers 8-0 to 8-7 output 8-bit data setting circuits 9-0 to 9-7 and 0FF.
8-1 to 8-7.8-00 outputs are connected to the input terminals respectively, and these inputs are selected to output DFFs 8-0 to 8-7.
give to Data setting circuits 9-0 to 9-7 provide data to shift register 6 consisting of D flip-flops 6-0 to 6-7. Also, shift register DFF6
The output of -0 and the output of the falling detector 5 are connected to the AND circuit 10.
given to. The AND circuit 10 controls the vibration absorption circuit 11 based on these AND signals. The vibration absorbing circuit 11 is connected to both ends of the resonant circuit 1 as shown in FIG. 1, and short-circuits both ends of the resonant circuit by a signal applied from the outside.

Here, the data carrier is configured so that the operator can arbitrarily set data using the data setting circuit 9. For example, among the 8 bits of data to be set, the first and last 2 bits are used as an identification code, as will be described later, so the other 4 bits of data are arbitrary set data by the user. The data carrier 12 is shown in FIG. 2(a).
As shown in the figure, there is a circular opening 13a-13 in the data setting area.
d, and a wire is stretched between them. One end of the wire is connected to a power source, and the other end is grounded through a resistor and connected to the input ends of a multiplexer to form data setting circuits 9-2 to 9-5.

Since the data setting circuits 9-0.9-1.9-6 to 9-7 set the identification code, the data carrier 12 itself is not provided with an opening so that the user cannot set it arbitrarily.

In this way, any code can be set very easily by cutting the wire.

Also, instead of setting data by cutting wires,
As shown in FIG. 2(b), a dip switch may be provided and data may be set using the dip switch. Here, the data setting circuit 9 and the data setting section of the data carrier constitute data setting means for arbitrarily setting data by the user, including the shift register 6, multiplexers 8-0 to 8-7. The fall detector 5 and the AND circuit 10 constitute data reading means for reading out set data.

Next, the operation of this embodiment will be explained with reference to the waveform diagram in FIG. In this figure, (a) to (i) are a in Figure 1.
-i is a waveform diagram corresponding to i. In this embodiment, data writing is set by the user by cutting the wire, so only data reading is performed. FIG. 3 is a time chart when reading data. At the time of reading, the write/read control unit sends a signal with a constant duty ratio, for example, 50%, at time t, as shown in FIG. 3(a). Output. Then, the signal is received via the resonant circuit l, and transmitted via the rectifier circuit 2 and the voltage detection circuit 3 to a time t delayed by a predetermined time from the time t1, as shown in FIG. 3Cb).
2, a reset signal RES is applied from the voltage detection circuit 3 to the clear input terminal CL of the shift register 6, and all DFFs of the shift register 6 are cleared.

Then, as shown in FIG. 3(C), at the rising edge of the output of the waveform shaping circuit 4, the clock signal is transmitted to the clock input terminal of the shift register 6 at t4, and the code is set at that time. 8-bit data of circuit 9 is read through multiplexer 8. Now, at time t, a predetermined time after the time is reset, the output from monostable multivibrator 7 is given to the selection input terminals of multiplexers 8-0 to 8-7, and from then on, shift register 6 enters circulation mode. . And time t.

Thereafter, when a rising pulse as shown in FIG. 3(g) is obtained from the output of the falling detector 5, the data is shifted by the shift register 6. Therefore, the serial signals set as shown in FIG. 3(5) are sequentially read out. The vibration absorption circuit 11 operates based on the AND of the output from the DFF 6-0 and the falling detection signal. At this time, the vibration absorbing circuit 11 closes the switching elements connected to both ends of the resonant circuit 1, so that reverberation is prohibited during the period when this signal is applied, as shown in FIG. 3(a).

Therefore, both ends of the resonant circuit l have a constant duty ratio, and when the logic signal is H, there is reverberation, and when the logic signal is 0, a signal without reverberation is obtained. This signal is similarly detected on the read/write head side (not shown), so the read/write head can read the signal written in the shift register based on the presence or absence of reverberation.

Now, when 8 bits or more are read out continuously, the same data is repeatedly output. Data reading is not necessarily performed in 8-bit units, and it is necessary to be able to read data even if data reading is stopped midway. Next, the structure of the identification code that makes this possible will be explained. The data length is, for example, 8 bits, and as shown in Figure 4, the first two bits a and b and the last two bits c and d are used as the identification code ID, and the 4 bits between are bits that the user can use arbitrarily. .

Here, the identification code has the following limitations.

That is, the first identification code "ab" and the last identification code rc
If the ID codes are matched, the data will be read out in a circular manner, making it impossible to determine which ID code is the first one. Therefore, a, b and c, d cannot be matched at the same time. Therefore, in the above embodiment, as shown in FIG. 2.3, ra, b'rc, d' and rll'
The case where the pattern 'O1l is used as an identification code (ID) is shown.

Now, on the write/read control unit side, it is necessary to be able to read out the data written by the user accurately even if it reads from the middle of the 8-bit data thus obtained. FIG. 5 is a diagram showing an example of such a code identification circuit. In the figure, the write/read control unit shapes the waveform of the output of the data receiving circuit 21 and supplies it to the 8-bit shift register 22. The first two bits and the last two bits are compared by digital comparators 23 and 24, respectively. These comparators 23 and 24 contain an identification code previously held in a shift register, for example, in the above-mentioned embodiment, ``RAB''-r.
Comparators are provided such that llJ, rcd, 1=rO1, and the -dispersed outputs of these are detected by an AND circuit 25. Further, a register 26 for temporarily holding data is connected to the intermediate 4-bit output terminal of the shift register 22.

Then, when a match signal is obtained from the AND circuit 25, the operation of the shift register 22 is stopped and the intermediate 4
The bits are saved in the register 26, and the serial data is read from the register 26.

In this way, any data written in the shift register of the data carrier can be read out again.

Next, FIG. 6 is a block diagram showing the configuration of a data carrier according to a second embodiment of the present invention. In this figure, the same parts as in the embodiment described above are given the same reference numerals, and detailed explanation will be omitted. In this embodiment as well, a rectifier circuit 2, a voltage detection circuit 3, and a waveform shaping circuit 4 are connected to the resonant circuit 1, and the output of the waveform shaping circuit 4 is given to a fall detection circuit 5.

Further, the output of the waveform shaping circuit 4 is applied to an 8-bit Johnson counter 31. 8-bit Johnson counter 31
is the 8 input bits 0 to 7 based on the input signal.
It sequentially outputs H level signals, and the output thereof is given to an OR circuit 40 via AND circuits 32-39. The other input terminals of the AND circuits 32 to 39 are connected to the data setting circuit 9 described above. AND circuit 32
.about.39 supplies each AND output of the Johnson counter 31 to the OR circuit 40. The OR circuit 40 provides the logical sum signal to the AND circuit 31. The AND circuit 31 connects and disconnects the resonant circuit 1 via the vibration absorbing circuit based on the AND of the outputs of the rise detector 5 and the OR circuit 40. Here, Johnson counter 31 AND circuits 32-39. OR circuit 40. The AND circuit 41 constitutes data reading means for sequentially reading out the data set by the data setting section.

Next, the operation of this embodiment will be explained with reference to the waveform diagram in FIG. When a signal intermittent at a predetermined duty ratio is sent to the data carrier side from a write/read control unit (not shown) in the same way as in FIG. 3(a), FIGS. 7(a) to (d)
), it is reset before power is supplied to each part. Thereafter, a clock signal is applied to the Johnson counter 31 at predetermined intervals, and thereafter, as shown in FIG. 7(e), each output terminal bit 0 to
Bit 7 sequentially outputs signals with different timings depending on the clock signal. By ANDing this signal and the data setting circuit 9, an OR circuit 40 is generated as shown in FIG. 7(f).
Since the signal is read out via the above-mentioned first embodiment, the presence or absence of reverberation is controlled by the output set as in the first embodiment described above.

Therefore, the write/read control unit can read out the signal depending on the presence or absence of reverberation.

In this embodiment, the data setting circuit of the data carrier has an 8-bit configuration, but it goes without saying that the present invention can be applied to other configurations as well. For example, when using a shift register with a 16-bit configuration, the first 4 bits and the last 4 bits may be used as the identification code, and arbitrary 8-bit data may be written between them.

Also, the number of bits at the beginning and end of the identification code does not necessarily have to be the same (although any number can be selected).

〔Effect of the invention〕

As described above in detail, according to the present invention, the user can set the data with his or her own hands, so the data can be set extremely easily, and the data can be
I can approve. Furthermore, since data can be retained without using batteries, the lifespan is not limited by the battery life and can be extremely long, and environmental resistance can also be greatly improved. Further, data can be repeatedly read by applying a signal with a predetermined duty ratio from the outside. Furthermore, even if reading is stopped midway, intermediate write data sandwiched between identification codes can be reliably read. Therefore, it is possible to construct a small capacity data carrier with an extremely simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data carrier according to an embodiment of the present invention, FIG. 2 is an external view of the data carrier,
Figure 3 is a waveform diagram showing the waveforms of various parts when reading data, Figure 4 is a diagram showing an example of data including an identification code written to the shift register, and Figure 5 is used on the write/read control unit side. FIG. 6 is a block diagram showing the configuration of a data carrier according to a second embodiment of the present invention, FIG. 7 is a waveform diagram showing waveforms of each part, and FIG. FIG. 1 is a block diagram showing an example of a conventional data carrier. 1--------Resonance circuit/Waveform shaping circuit/Shift register pie break 9.9-0 to 9-7・, Vibration absorption circuit 3-m----・Voltage detection circuit 4 5-... -Rise detector 6 7...One-shot multi 8-1 to 8-7...Multiplexer data setting circuit 11 31...-Johnson counter

Claims (1)

[Claims] (1) a data setting means for setting multiple bits of data; a resonant circuit for receiving an intermittent signal with a constant duty ratio; and a waveform shaping circuit for smoothing and shaping the received output obtained by the resonant circuit; data reading means for reading data from the data setting means based on a signal with a predetermined duty ratio given by a waveform shaping circuit; A data carrier characterized by having a vibration absorption circuit that controls reverberation of the data carrier.