JPH03229382A - Data carrier - Google Patents

Abstract

PURPOSE:To obtain a data carrier of small capacity in a simple constitution by using a shift register as a memory so as to hold the data once written as they are and hereafter reading out repetitively the data external application of a signal having a prescribed duty ratio. CONSTITUTION:The signals of different duty ratios are received by a resonance circuit 1 and shaped by a waveform shaping circuit 2 in a data writing state. Then a shift pulse is applied to a shift register 5 from the shaped signal and at the same time written into the register 5 as a write signal. When this write signal is outputted from the register 5, the input of the register 5 is switched by a signal switch means 9. So that the subsequent signal writing operations are inhibited and the data are circulated in the register 5. In a reading state, the signal read out of the register 5 is applied to the circuit 1. Thus the vibrations of the circuit 1 are absorbed and the data are transmitted to the outside. In such a simple constitution, the capacity of a data carrier can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data carrier used in an article identification system such as a tool for a machine tool, a part in a factory, a product management system, or a distribution system.

[Conventional technology]

In order to mechanize the management of tools in conventional machine tools and the identification of parts and products on assembly lines in factories, a system for identifying and managing various items such as tool parts and products is required. Therefore, as in Japanese Patent Application Laid-Open No. 1-151832, a data carrier having a memory is provided in the object to be identified, necessary information is written in the memory of the data carrier by data transmission from the outside, and the information is read out as necessary. An article identification system has been proposed.

As shown in FIG. 6, such a data carrier has a resonant circuit 31 connected to a receiving coil, a waveform shaping circuit 32 that shapes the signal obtained from the resonant circuit, and is configured with a gate array, a CPU, etc. Data is written into the memory 34 via the memory control unit 33, or read based on a given command, and the vibration of the resonance circuit 31 is absorbed by the vibration absorption circuit 35, thereby transmitting the data.

[Problem to be solved by the invention]

However, such conventional data carriers are configured to be able to mount a relatively large capacity memory. Therefore, the memory control section composed of a gate array, a CPU, etc. becomes complicated, and since a memory with a large capacity is used, the cost cannot be reduced. Therefore, it has the disadvantage that it is not suitable for cases where such a large capacity memory is not required and a small memory capacity, for example, a few bits to several tens of bits, is sufficient.

The present invention was made in view of the problems of the conventional data carrier, and is suitable for reducing the capacity and holds a small amount of data with an extremely simple structure, and is capable of holding a small amount of data using a conventional write/read control unit. The technical problem is to be able to use it as is to write data and read that data.

[Means to solve the problem]

The present invention uses a resonant circuit that receives a PWM signal with a duty ratio that differs depending on write data including an identification code in the transmission mode, and a fixed duty ratio in the reception mode, and a waveform that smooths the received output obtained from the resonant circuit. A waveform shaping circuit that shapes the signal, a shift register that circulates and holds data in which the signal obtained from the waveform shaping circuit is given as a shift pulse, and a shift register that uses the output of the shift register to shift the human power given to the shift register from the output of the shaping circuit. It has a signal switching means for switching to the output of the register, and a vibration absorption circuit for controlling the reverberation of the resonant circuit based on the signal read from the shift register when a signal with a constant duty ratio is given in the reception mode. It is characterized by:

[Effect]

According to the present invention having such characteristics, signals having different duty ratios are applied when writing data to a data carrier, and the signals are received by the resonant circuit and shaped by the waveform shaping circuit.

A shift pulse is then given to the shift register from this signal, and is also written into the shift register as a write signal. When the signal is outputted from the shift register, the signal switching means switches the input of the shift register to inhibit further writing of the signal and circulate the data within the shift register. At the time of reading, the signal read from the shift register is applied to a resonant circuit to absorb the vibration and transmit the data to the outside.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a data carrier according to an embodiment of the present invention. In this figure, the data carrier has a resonant circuit 1 consisting of a coil L for transmission and reception and a capacitor C, and supplies a PWM modulation signal given from the outside to a waveform shaping circuit 2. “The waveform shaping circuit 2 detects the envelope of the given signal and discriminates it at a predetermined level, thereby obtaining a received signal that corresponds to signal discontinuities.
Its output is given to a multiplexer (MPX) 3 and a monostable multibibreak (MM) 4. The monostable multivibrator 4 delays the applied received signal by half a cycle, and its output is applied to the shift register 5 as a shift pulse.

The shift register 5 is composed of, for example, 8 bits, and the output of the multiplexer 3 is given to the data input terminal, and the data output terminal is connected to the set input terminal of the flip-flop (FF) 6, the input terminal of the AND circuit 70, and the other terminal of the multiplexer 3. given to the input end. A clear signal source 8 is also provided, which is comprised of a resistor and a capacitor connected in series to the power supply, and an inverter connected to the midpoint of the resistor and capacitor. The clear signal source 8 supplies a clear signal that goes to the H level after the power is turned on and goes to the L level after a predetermined time delay to the clear input terminal of the shift register 5 and the reset input terminal of the flip-flop 6. The flip-flop 6 switches the input of the multiplexer 3 according to its Q output, and when the Q output is at L level, it switches the output (Yo) of the waveform shaping circuit 2 mentioned above, and when it is at H level, it switches the data out input (Yl) of the shift register 5. Provided to the input side (IN) of the shift register. Here, the multiplexer 3 and the flip-flop 6 constitute a signal switching means 9 for switching the input signal to the shift register 5.

Now, the output of monostable multivibrator 4 is AND circuit 7
It is also given to The AND circuit 7 provides its AND output to the monostable multivibrator 10 when reading data. The monostable multivibrator 10 operates for a short time in response to data read from the shift register 5, and its output is given to the vibration absorption circuit 11. The vibration absorption circuit 11 stops reverberation of the received signal by closing a switching element that connects both ends of the resonant circuit 1 to ground when an H level signal is applied. A backup battery 12 for holding data in the shift register 5 is also attached to this data carrier.

When writing data to the data carrier, the shift register 5 and flip-flop 5 are reset using the clear signal source 8, and thereafter signals with different duty ratios are sent to the receiving coil of the data carrier at regular intervals. To do something. Writing/writing to such data carriers
The configuration of the read control unit is the same as that shown in the prior art example described above.

Next, the operation of this embodiment will be explained. First, when the power is turned on before writing data, the clear signal source 8 applies an H level signal to the shift register 5 and flip-flop 6 for a short time, clearing the shift register 5 and resetting the flip-flop. Thereafter, a waveform in which a signal with a constant period T is intermittent at a duty ratio corresponding to the data to be written is input from a write/read control unit (not shown). For example, when the logic is "1", the duty ratio is 70%, and when the logic is r□, the duty ratio is 30%.
) is output as shown in FIG. 2 and applied to the receiving coil L1. Then, the signal is received by the resonant circuit 1, envelope-detected by the waveform shaping circuit 2, and discriminated at a predetermined level, thereby obtaining a signal as shown in FIG. 2(C). This signal is applied to the monostable multi-high break 4, and is applied to the shift register 5 as a signal with a duty ratio of approximately 50% delayed by A period from the rising time as shown in FIG. 2 ((1). Since the flip-flop 6 has been reset, the output of the waveform shaping circuit 2 is directly written to the shift register 5 via the multiplexer 3.Since the shift register 5 has an 8-bit configuration, the output of the waveform shaping circuit 2 is written as is in the shift register 5 as shown in FIG. 2(e). As shown in the figure, when 8 bits of data are written, the output of the data output terminal of the shift register 5 becomes H level.For this reason, the flip-flop 6 is inverted, and from then on, the output of the shift register 5 is directly sent to the multiplexer. 3 becomes the input to the shift register 50. Therefore, even if data is transmitted, the data is not written repeatedly, and the data in the shift register 5 is circulated, and the data is held in the shift register 5.Here, In order to change the shift register 5 from the write mode to the circulation mode, the first data to be written must be "1".In this way, the signal is written to the shift register 5 as shown in FIG. 2(e). After that, data writing ends.

Next, data reading will be explained. When reading data from a data carrier, the write/read control unit outputs a signal with a constant duty ratio, for example 50%, at the same cycle as the data write cycle described above, as shown in FIG. 3(a). Then, resonant circuit 1. Waveform shaping circuit 2
The signal is shaped by the waveform shaping circuit 2.
The signal shown in Figure (b) is output. A signal delayed by half a period is obtained from the monostable multi-by-break 4 as shown in FIG. 3(C), and this signal is applied to the shift register 5 as a shift pulse. Therefore, signals are read out from the shift register 5 in response to the shift pulses as shown in FIG. 3(d). As shown in FIG. 3(e), the AND circuit 7 outputs a signal that becomes H level when the logic signal "l" is read out, and becomes "L" level when the logic signal "Oj" is read out. This signal is then given by the monostable multivibrator 10 to the vibration absorption circuit 11 as a vibration absorption control signal for a short period of two periods or less. Since the vibration absorbing circuit 11 closes the switching elements connected to both ends of the resonant circuit 1, reverberation is prohibited during the period when this signal is applied, as shown in FIG. 3(a).

Therefore, as shown in FIG. 3(a), when the logic signal is H with a constant duty ratio at both ends of the resonant circuit 10, there is reverberation, and when the logic signal is 0, a signal without reverberation is obtained. Since this signal is detected in the same way on the read/write head side (not shown), the read/write head writes the signal to the shift register 5 as shown in FIG. 3 (9) and (b) based on the presence or absence of reverberation. Signals can be read out.

Now, when 8 bits or more are read out continuously, the same data is repeatedly output. Data reading is not necessarily performed in units of 8 bits, and it is necessary to be able to read data even if data reading is stopped midway. Next, the structure of the identification code that makes this possible will be explained. For example, the data length is 8 bits, and as shown in Fig. 4(a), the first two bits a, b and the last two bits c, d are the identification code ID, and the 4 bits between can be used as desired by the user. Bit.

Then, the possible code pattern of the identification code is the fourth one.
The result is shown in Figure (b). However, the pattern of the identification code cannot be arbitrarily determined as 1=, and there are the following restrictions. That is, the first identification code a needs to be 1 in order to switch the shift register from write mode to circulation mode. Therefore, patterns ■ to ■ cannot be taken. Furthermore, if the first identification code "ab" and the last identification code "cd" match, the data is read out in a circular manner, making it impossible to determine which one is the first identification code. Therefore a
, b, c, and d cannot be matched at the same time, and patterns ■ and ■ are impossible. Therefore, the possible identification code patterns are either ■ or ■■ in FIG. 4(b). In the above-mentioned embodiment, as shown in FIG. 2-3, a pattern of ■ is used as an identification code (ID).

Now, on the write/read control unit side, we can obtain 8
It is necessary to be able to read out the data written by the user accurately even if the data is read from the middle of the 7-bit data. FIG. 5 is a diagram showing an example of such a code identification circuit. In the figure, the write/read control unit shapes the waveform of the output of the data receiving circuit 21 and supplies it to the 8-bit shift register 22. The first two bits and the last two bits are compared by digital comparators 23 and 24, respectively. This comparator 2
3 and 24 are identification codes previously held in the shift register, for example, in the above embodiment, ``rab''=rl.
lJ,'cd'=r.

1'', and the AND circuit 25 detects the coincidence outputs of these comparators. Further, a register 26 for temporarily holding data is connected to the intermediate 4-bit output terminal of the shift register 22.

Then, when a match signal is obtained from the AND circuit 25, the operation of the shift register 22 is stopped and the intermediate 4
The bits are saved in the register 26, and the serial data is read from the register 26.

In this way, any data written in the shift register of the data carrier can be read out again.

In this embodiment, the shift register of the data carrier has an 8-pin configuration, but it goes without saying that the present invention can be applied to other configurations as well. For example, when using a 16-bit shift register,
For example, the first 4 bits and the last 4 bits may be used as the identification code, and 8 bits of arbitrary data may be written between them. Also, the number of bits at the beginning and end of the identification code does not necessarily have to be the same (although any number can be selected).

〔Effect of the invention〕

As described above in detail, according to the present invention, a shift register is used as a data carrier memory. Therefore, once data is written, it is held as is, and thereafter the data can be read out repeatedly by applying a signal with a predetermined duty ratio from the outside. Furthermore, even if reading is stopped midway, intermediate write data sandwiched between identification codes can be reliably read. Therefore, it is possible to construct a small capacity data carrier with an extremely simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data carrier according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms of various parts when writing data, and FIG. 3 is a waveform diagram showing waveforms of various parts when reading data. Figure 4 shows an example of data including an identification code written to the shift register and an example of an identification code pattern, and Figure 5 shows an example of data including an identification code used on the write/read control unit side. A circuit diagram showing a readout circuit, and FIG. 6 is a block diagram showing an example of a conventional data carrier. 1 - Resonant circuit 2 - Waveform shaping circuit 3 Multiplexer 4. lO・-*Stable multi-bye break 5, 22---Shift register 9---Signal switching means I L-m----Vibration absorption circuit Figure (a) (b) Figure 6 Figure hand Continuing amendment (voluntary) 3゜4゜Indication of the case 1990 Patent Application No. 24789 Name of the invention Data carrier Relationship to the case Patent applicant
-Address: 10 Hanazono Tsuchido-cho, Ukyo-ku, Kyoto-shi, Kyoto Prefecture
1 name (294) OMRON Corporation
・-9 Representative Yoshio Tateishi

Claims (1)

[Claims] (1) In the transmission mode, the duty ratio varies depending on the write data including the identification code, and in the reception mode, the duty ratio is a resonant circuit that receives a PWM signal with a constant duty ratio, and smooths the received output obtained from the resonant circuit. a waveform shaping circuit that shapes a waveform; a shift register that receives a signal obtained from the waveform shaping circuit as a shift pulse and that circulates and holds data; and a waveform shaping circuit that shapes the input that is given to the shift register based on the output of the shift register. a signal switching means for switching from the output of the circuit to the output of the shift register; and a vibration absorber for controlling the reverberation of the resonant circuit based on the signal read from the shift register when a signal with a constant duty ratio is given in reception mode. A data carrier comprising a circuit.