JPH03286626A - Article identifying system - Google Patents

Abstract

PURPOSE:To attain the data transmission for a long range and employ digital circuits for all circuits by making the frequencies of transmission and reception between a write/read control unit and a data carrier different from each other and oscillating a signal from the data carrier side. CONSTITUTION:A write/read control unit 50 is provided with an ID controller 51 and a read/write head 52 and the transmission and reception frequencies are made to be different from each other. Moreover, a data carrier side 60 is provided with 1st and 2nd resonance circuits 61, 62 with a comparatively low Q, the write/read control unit 50 outputs a signal with 1st and 2nd duty ratio corresponding to a transmission data at transmission, the data carrier side receives the signal by the resonance circuits 61, 62 and obtains a reception clock corresponding to an envelope by using retriggerable monostable multivibrators 63, 64 and the signal is demodulated based on the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an identification system for tools used in machine tools, parts in factories, products used in product management, distribution systems, and the like.

[Conventional technology]

In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 9 are required.
A system is needed to identify and manage various items such as parts and products. Therefore, as shown in Japanese Patent Application Laid-Open No. 1-151831, a memory unit having a memory is provided in the object to be identified, and necessary information is written in such memory by data transmission from the outside, and the information can be used as needed. An article identification system that reads out this information has been proposed.

Such a conventional article identification system originates from a write/read control unit 1 and a data carrier 2 attached to the article. FIG. 5 is a block diagram showing the configuration of an ID controller 3 and a read/write head 4 that constitute a write/read control unit 1 used in a conventional article identification system. In this figure, the ID controller 3 has a transmission control circuit 10 and a reference clock generation circuit 11, and a transmission/reception switching signal T/R and a signal TXNRZ sent from a host computer (not shown) are used as a transmission clock TX.
It is given in synchronization with CLK. The transmission control circuit 10 generates a transmission signal based on these signals and supplies it to the oscillation circuit 12 of the read/write head 4. A transmitting coil L1 is connected to the oscillation circuit 12, and transmits an oscillation signal to the data carrier 2 intermittently at a constant frequency. Further, a resonant circuit 13 consisting of a receiving coil L2 and a capacitor C1 for receiving signals from the data carrier 2 is provided, and its output is demodulated by a demodulation circuit 14 and given to a reception control circuit 15. The reception control circuit 15 is supplied with a reference clock from the clock generation circuit 11, and outputs a reception signal based on the demodulated signal. Further, a shunt circuit 16 consisting of a resistor and a switching element is provided in parallel with the resonant circuit 13. A gate circuit 17 detects the transmission clock signal TXCLK during reception, and a fall detector 18 detects the fall of this gate signal.
is provided in the read/write head 4. The fall detector 18 short-circuits the switching element of the shunt circuit 16 connected in parallel to the resonant circuit 13 at the time of fall.

FIG. 6 is a block diagram showing the detailed configuration of the transmission control circuit 10. In the figure, a D crimp flop 21 holds the transmission signal TXNRZ during the timing of the transmission clock TXCLK, and its output is given to the counter 22. The counter 22 is a counter whose count-up value can be changed by the output of the flip-flop 21, and its output is applied to the reset signal of the RS flip-flop 23 when the count amplifier is used. The transmission clock signal is also applied to a rising edge detector 24 and a multiplexer 25. The rising edge detector 24 detects the rising edge of TXCLK, clears the counter 22, and clears the flip-flop 2.
3 cents. Flip-flop 23 provides its Q output to multiplexer 25. The multiplexer 25 applies the output of the flip-flop 23 during transmission and the output of TXCLK during reception to the oscillation circuit 11 as a transmission signal.

On the other hand, the data carrier 2 has a coil L3 as shown in FIG.
It has a resonant circuit 30 consisting of a capacitor C2 and a capacitor C2,
A bridge-type first full-wave rectifier circuit 31 is connected to both ends of the resonant circuit 30. 8 between the capacitor C3 for smoothing the output and the Zener diode ZDI for voltage crimp and the voltage detection.
32 are provided. The voltage detection circuit 32 provides a reset signal to the control circuit 33 when its output exceeds a certain level. Further, a second full-wave rectifier circuit 34 is provided at both ends of this resonant circuit 30, each having a diode, and its output is given to a comparator 35. The comparator 35 provides a clock signal to the control circuit 33 and also provides a signal for shaping the reference pulse to the AND circuit 33.
6. Also, its output is sent to the rising edge detector 37.
The signal is applied to the gate circuit 38 via. Gate circuit 38
T is a signal to be transmitted from the control circuit 33 at the time of transmission.
XNRZ is given, and a switching element 39 such as an FET is operated by the logical product thereof. A shunt circuit 40 consisting of a resistor and an analog switch is connected to the resonant circuit 30, and is configured to short-circuit the resonant circuit 30 by a switching element 39.

Further, the control circuit 33 is provided with a demodulation circuit 41.

As shown in FIG. 8, the demodulation circuit 41 includes a counter 42 that counts pulses from the AND circuit 36, and a flip-flop circuit 43 that determines whether or not there is a count-up output.
˜45, and demodulates the original NRZ signal. The control circuit 33 decodes the demodulated signal, separates the command and data, and controls the writing or reading of data in the memory 46 based on the command. Further, the data carrier 2 is equipped with a battery 47 that supplies power to each part.

Next, the operation of this article identification system will be explained with reference to a time chart. When transmitting data from the ID controller 3 side to the data carrier 2, the T/R switching signal is at H level as shown in FIG. 9(a), and the signal TXNRZ to be sent is at the H level as shown in FIG. ) as shown in T
It shall be given in synchronization with XCLK. At this time, the reference clock is a clock signal with a sufficiently high frequency, and D
The count-up value of the counter 22 changes depending on the output of the F+J block flop 21. For example, when the output is rH and the level is 70%, the counter 2
2 counts up, and when the output is at the "L" level, the count increases when the duty ratio reaches 30%. The flip-flop 23 is reset by this signal, and an oscillation control signal is applied to the oscillation circuit 12 via the multiplexer 25 as shown in FIG. 9(e). Therefore, oscillation circuit 1
2 outputs a signal as shown in FIG. 9(f).

On the other hand, when the data carrier 2 receives this signal, the resonant circuit 30 obtains the signal shown in FIG. 10(a). If this level is above a certain level, the voltage detection circuit 32 provides a reset signal to the demodulation circuit 41. Further, by full-wave rectifying and smoothing this signal and discriminating it at a predetermined level, the signal shown in FIG. 10(C) is obtained from the comparator 35. By applying this signal and the pulse signal obtained by the resonant circuit 30 to the AND circuit 36, a pulse signal as shown in FIG. 10(c) can be applied to the demodulation circuit 41. The demodulation circuit 41 resets the counter 42 every time the clock signal rises, and counts the number of pulses given in the next cycle. In this way, as shown in FIG. 10(e), the duty ratio of the counter 42 becomes 7.
When it is 0%, a count up signal can be obtained. The RS flip-flop 43 is set by this signal, and the RS flip-flop 43 is set as shown in FIG.

As shown in (b), two D flip-flops 44°4
5 can be used to demodulate the NR20 original signal.

Also, when transmitting data from data carrier 2, ID
The duty ratio is constant from the controller 3 side, for example 50.
% signal is always output (Fig. 9(e)).

(f)). Data carrier 2 receives this signal and
As shown in FIG.
The signal to be sent from 3 is the TXNR shown in Fig. 10 (i).
In the case of the Z signal, the AND condition is satisfied when r□, a shunt pulse is applied to the FET 39, the FET 39 is turned on, and the shunt circuit 40 is closed. Therefore, at this time, there is no reverberation as shown in Figure 10(a).
At other times, a reverberant signal is obtained in the resonant circuit 30. Then, as shown in Figure 9 (b) and (j), the TXC
A shunt pulse shown in FIG. 9(b) is obtained every time LK falls.

Then, the signal is demodulated by detecting the presence or absence of subsequent reverberation at the falling edge of the reception clock.

[Problem to be solved by the invention]

However, according to such conventional article identification systems,
Since the damped vibration of the resonant circuit is detected by the resonant circuit having the receiving coil of the read/write head, a low level signal must be received on the read/write head side. Therefore, there was a problem in that data transmission over long distances became difficult. Furthermore, in order to obtain reverberation in the resonant circuit of the data carrier, it is necessary to increase the Q of the resonant circuit. Therefore, the reverberation becomes large when data is transmitted, and reverberation also occurs in the clock pulse. Therefore, it is necessary to shape the clock signal using the comparator 34 and use the output thereof to provide a reference pulse to the demodulation circuit via an AND circuit, which has the drawback of requiring a comparator with large power consumption. Another drawback is that a full-wave rectifier circuit and a voltage detection circuit are required to obtain the reset signal. Furthermore, there are disadvantages in that the overall number of analog circuits is large, the mounting space is large, and the adjustment work is complicated.

The present invention has been made in view of the problems of the conventional article identification system, and aims to enable long-distance data transmission and digitization of circuits by separating the transmitting and receiving frequencies. Consider it a technical issue.

[Means to solve the problem]

The present invention relates to a data carrier having a memory that holds data, a memory control means that controls writing and reading of data to the memory, and a writing/reading device that transmits data to the data carrier and receives the transmitted data. An article identification system comprising: a control unit; a data carrier; a first resonant circuit having a first frequency as a resonant frequency; and a shaping circuit that shapes pulses obtained from the first resonant circuit. , a monostable multivibrator that is triggered by a pulse obtained from a shaping circuit and has an operation time longer than the pulse period, and is retriggered, and a signal based on changes in the duty ratio of the clock signal provided by the monostable multivibrator. A first oscillator whose resonant frequency is a second frequency different from the first frequency, and a second resonant circuit connected to the first oscillator. /read control unit, when transmitting data, selects the first . Second
and a first coil provided on a surface facing the data carrier. a second oscillator that intermittents oscillation of the first frequency based on a transmission pulse signal given by the transmission pulse generation means; The device is characterized in that it has a third resonant circuit provided on the surface of the resonant circuit, and a reception control circuit that reads data by shaping the output of the third resonant circuit.

[Effect]

According to the present invention having such characteristics, when transmitting from the write/read control unit side, signals having the first and second duty ratios are outputted in correspondence with the transmitted data. The data carrier receives this signal through a resonant circuit, uses a retriggerable monostable multivibrator to obtain a reception clock signal corresponding to the envelope, and demodulates the signal based on this. Furthermore, since the frequency of this signal is different from that of the third resonant circuit used for receiving the read/write head and the second resonant circuit used for transmitting the data carrier, no reverberation occurs. Therefore, a carrier clock signal is easily obtained using a low Q resonance circuit. Also, when receiving a signal to the write/read control unit, the write/read control unit sends out a transmission pulse signal with a third duty ratio, and a second frequency is resonated in response to the third duty ratio. Data is received by sending out an NRZ signal from the second resonant circuit that uses the frequency.

(Embodiment) Fig. 1 is a diagram showing the tank bottom of a write/read control unit according to an embodiment of the present invention.In this figure, the same parts as in the conventional example described above are given the same reference numerals, and a detailed explanation will be given. omitted.

In this embodiment, the write/read control unit 50 includes an ID controller 51. It has a read/write head 52. The ID controller 51 is similar to the conventional example described above, and the transmission control circuit 10. A reference clock generation circuit 11 and a reception control circuit 15 are provided. In this embodiment, the gate circuit I6 detects the pulse during transmission, the fall detector 17 detects the falling edge of the gate circuit I6, and the third gate circuit for reception uses the falling signal.
The shunt circuit 16 connected to the resonant circuit 53 is removed.

Now, in this embodiment, the oscillation of the oscillation circuit 12 is set to the first frequency f, and the resonant frequency of the resonant circuit 53 is set to the second frequency f.
2, the inductance of the receiving coil L5 and the capacitance of the capacitor C4 connected in parallel thereto are selected so that these frequencies, that is, the transmitting and receiving frequencies, are different. It is assumed that the Q of the resonant circuit 53 is kept relatively low.

Next, FIG. 2 is a block diagram showing the configuration of the data carrier 60 of this embodiment. In this figure as well, the same parts as those in the conventional example described above are given the same reference numerals and detailed explanations will be omitted. This data carrier 60 has a relatively low Q first. It has second resonant circuits 61 and 62. The resonant circuit 61 has the same resonant frequency f1 as the oscillation frequency of the oscillation circuit 12 of the read/write head 52, and the resonant circuit 62 has the same resonant frequency f2 as the resonant circuit 53 of the read/write head 52. . Now, in the resonant circuit 61, a diode D1 for half-wave rectification and a Zener diode ZD2 for clipping are connected between its cathode and the ground terminal.

These constitute a waveform shaping circuit, the output of which is given to the multi-by-break 63. The multivibrator 63 is a retriggerable monostable multivibrator having an operation time slightly longer than the period of the applied pulse, and its Q output is applied to the multivibrator 64.
The Q output is given to the control circuit 33 as a clock signal. The multivibrator 64 is a retriggerable multivibrator having an operating time longer than one cycle of the NRZ signal applied from the read/write head 52, and its output is applied to the control a circuit 33 as a reset signal.

The configurations of the control circuit 33 and the demodulation circuit 41 are the same as those of the conventional example described above, so detailed explanations will be omitted. Now, the signal TXNRZ sent from the control circuit 33 is transmitted to the second oscillation circuit 6.
given to 5. The oscillation circuit 55 has a plurality of cascade-connected inverters or gate circuits connected in a feedback manner,
This is an oscillation circuit consisting of a digital circuit that outputs a pulse signal at a constant cycle every time an input signal is applied, and its output is applied to a switch FET 66. The switch FET 66 outputs a signal by grounding the resonance circuit 62 connected between it and the power source.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG. 3.4. Write/read control unit 50
When transmitting a signal from the side, the transmission/reception switching signal T/R is at H level, as shown in FIG. 3(a), as in the conventional example described above. At this time, an NRZ signal to be sent out in synchronization with TXCLK is given. Then, as in the conventional example described above, a signal having a duty ratio corresponding to the signal to be transmitted is output. In this case, even if the oscillation circuit 12 oscillates intermittently, no reverberation occurs because the resonant frequency of the resonant circuit 53 is different from the transmitted frequency.

On the other hand, the data carrier 60 receives this signal through a resonant circuit 61 and is connected to a diode D1. By shaping the waveform with the Zener diode ZD2, the signal shown in FIG. 4(b) is obtained. In this case, since the Q of the resonant circuit 61 is low, if transmission is stopped, a shaped pulse train can be provided to the control circuit 33 with almost no reverberation.

The monostable multi-by-break 63 is triggered by the rise of this signal as shown in FIG. 4(C), and is continuously retriggered by each subsequent pulse period, so that the signal is sent as shown in FIG. 4(C). A signal with a constant period corresponding to the duty ratio of the signal is obtained.

Further, the reset signal shown in FIG. 4(d) can be obtained by the multivibrator 64 having an operation time of one cycle or more. In this case as well, when the duty ratio is large, the control circuit 33 provides a count-up output of the counter 42, thereby allowing the original NRZ signal to be detected.

On the other hand, when transmitting a signal from the data carrier 60,
As shown in FIG. 3(C), the read/write head 52 outputs a signal with a duty ratio of 50%, and the data carrier 6
0 is given this signal. In synchronization with this signal, the data carrier 60 outputs the NRZ signal to be transmitted to the oscillation circuit 65 as shown in FIG. 4(i). Oscillation circuit 65
Based on this signal, provides an oscillation pulse to the FE 766 as shown in FIG. 4(j). Therefore, both ends of the resonant circuit 62 are grounded when turned on, and a signal as shown in FIG. 4(b) is output. This frequency f2 is different from the frequency f, and the Q of the resonant circuit 61 is also low.
), no wraparound or the like occurs in the resonance circuit 61. This signal is detected by the resonance circuit 53 of the read/write end 52 and demodulated by the demodulation circuit 14. Other operations are similar to those of the conventional example described above. In this case, since the signal is sent from the resonant circuit of the data carrier, the data transmission distance can be increased without increasing the Q of the resonant circuit of the read/write head too much. Furthermore, since the frequencies of transmission and reception are greatly different, there is no loopback, and it is no longer necessary to transmit and receive data alternately. Furthermore, there is no need to use a shunt pulse or the like to stop unnecessary reverberation, and the circuit configuration can be simplified.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the frequencies of transmission and reception between the write/read control unit and the data carrier are different, and the signal is oscillated from the data carrier side, so that the attenuation is reduced. Compared to conventional data carriers that transmit signals depending on the presence or absence of vibration, the advantage is that data can be transmitted over long distances. Also, since the Q of each resonant circuit is low, there is no wraparound,
Also, reverberation can be reduced. Therefore, the circuit configuration is simplified and almost all circuits can be digitized.
It also becomes easier to integrate the circuit. Further, an effect can be obtained in that the current consumption of the data carrier receiving section can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of a write/read control unit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the structure of a data carrier of this embodiment, and FIG. 3 is a block diagram showing the structure of a data carrier of this embodiment. 4 is a waveform diagram showing the waveforms of each part of the data carrier of this embodiment. FIG. 5 is a block diagram showing the configuration of a conventional write/read control unit. 9 is a block diagram showing an example of a conventional data carrier, FIG. 7 is a block diagram showing the configuration of a transmission control circuit of a write/read control unit, FIG. 8 is a block diagram showing a data carrier demodulation circuit, and FIG. 1 is a waveform diagram showing waveforms at various parts of a conventional read/write head, and FIG. 10 is a waveform diagram showing waveforms at various parts of a conventional data carrier. Troller 52--Read/write head
53, 61, 6: 2-m----resonant circuit 6
0----Data carrier 63, 64-1---
−Retriggerable monostable multivibrator

Claims (1)

[Claims] (1) A data carrier having a memory that holds data, a memory control means that controls writing and reading of data to the memory, and a writing device that transmits data to the data carrier and receives the sent data. /readout control unit, wherein the data carrier comprises: a first resonant circuit having a first frequency as a resonant frequency; and shaping a pulse obtained from the first resonant circuit. a shaping circuit; a monostable multivibrator that is triggered by a pulse obtained from the shaping circuit and has an operating time longer than the pulse period; a demodulation circuit that demodulates a signal, a first oscillator whose resonant frequency is a second frequency different from the first frequency, and a second resonant circuit connected to the first oscillator. The write/read control unit has first and second duty ratios corresponding to the transmitted data signal when transmitting data, and has a constant third duty ratio when receiving data.
a transmission pulse generation means for generating a transmission pulse signal of a constant period having a duty ratio of , and a first coil provided on a surface facing the data carrier, the transmission pulse signal given by the transmission pulse generation means; a second oscillator that intermittents oscillation of the first frequency based on the second oscillator; and a third resonator that has a resonance frequency different from the oscillation frequency of the second oscillator and is provided on a surface facing the data carrier. An article identification system comprising: a circuit; and a reception control circuit that reads data by shaping the output of the third resonant circuit.