JPH03230614A - Input circuit - Google Patents

Abstract

PURPOSE:To keep a signal level in the just preceding state even when no external signal is inputted to an input terminal and the input terminal reaches a high impedance state by holding the potential level of the input terminal with the self-holding function of 1st and 2nd logic inversion circuits. CONSTITUTION:The transition voltage VR2 of the 1st logic inversion circuit 2 is designed to be lower than the transition voltage VIT of an input buffer circuit 13 and higher than the low level input voltage criterion VIL of an input circuit 1. Then the transition voltage VR4 of the 2nd logic inversion circuit 4 is designed higher than the transition voltage VIT of the input buffer circuit 13 and lower than the high level input voltage VIN of the circuit 1. Thus, even when no signal is fed to the input terminal 11 and the input terminal 11 goes to a high impedance state, the potential level delivered from the output terminal 12 of the input buffer circuit 13 to the internal circuit is kept to the just preceding state.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention includes an input buffer circuit inserted between an input terminal and an output terminal, and a pull-up transistor is provided on the input side of the input buffer circuit. It concerns connected input circuits.

<Prior Art> FIG. 3 is a circuit diagram showing an example of a conventional input circuit incorporating a pull-up transistor.

Reference numeral (10) in FIG. 3 is an input circuit configured between an external signal line and an internal circuit (none of which is shown) in the integrated circuit. The input terminal (11) to be connected, the output terminal (12) to be connected to the internal circuit, and the input terminal (1
1) and an output terminal (12), and a pull-up transistor (14) for this input buffer circuit (13).

The input cover and F circuit (13) includes a P-channel field effect transistor (15) (hereinafter referred to as PMOSFET (15)) and an N-channel field effect transistor (16).
(hereinafter referred to as NMOS-FET (16)). The 2MO3-FET (15) (7) gate terminal (G) and the NMOS-FET (16) (7) gate terminal (G) are connected to each other, and the input terminal (1
1). In addition, PMO5-FET (1
5) drain terminal (D) and NMO5-FET (16
) are connected to each other and to the output terminal (12). On the other hand, 2MO3-F
The source terminal (S) of ET (15) is connected to the high potential side power supply (■D
In addition, the source terminal (S) of the NMOS-FET (16) is connected to the low potential side chamber tA (VGND).

Furthermore, the pull-up transistor (14) is a PMOS
-FET, whose source terminal (
S) is connected to a high potential power source (Vo), while the gate terminal (G) is connected to a low potential power source (VCHD). The drain terminal (D) is the input terminal (
11) and a pyo that constitutes the input amplifier circuit (13)
s-FET (15) and NMOS-FET (16)
are connected to each gate terminal (G) of. In the following description, this pull-up transistor (14) will be referred to as a pull-up PMOS-FET (14).

Next, the operation of this input circuit (10) will be explained.

When the signal level (V18) applied to the input terminal (11) is higher than the transition voltage (V7) of the input buffer circuit (13) (VIN>VIT), the input buffer circuit (1
3) 2MO3-FET (15) becomes cut off,
As a result of the NMOS-FET (16) becoming conductive, the output terminal (12) is connected to the low potential side power supply (VCHD) and transmits a low potential level to the internal circuit. Conversely, when the signal level (VIM) applied to the input terminal (11) is lower than the transition voltage (VIT) of the input buffer circuit (13) (V+s<Vat), the 2MO3-FET (
15) becomes conductive, and NMOS-FET (16)
As a result, the output terminal (12) is connected to the high potential side power supply (vDD) and transmits the high potential level to the internal circuit.

That is, as explained above, this input buffer circuit (13) functions as an inverter, but in this case, the pull-up PMOS-FET (14) has its gate terminal (G) fixed at a low potential level. Because there are
It is always in a conductive state. Therefore, the input terminal (1
The potential of 1) is determined by the output resistance of the signal source that supplies the signal via the external signal line and the pull-up PMO.
It is determined by resistance division with the resistance in the conductive state (on resistance) of SFET (14).

Therefore, when considering the high level input voltage standard (VIM) and low level input voltage standard (VIL) in the input circuit (10) in order to make the input buffer circuit (13) function normally as an inverter, it is necessary to When the input signal level (VIM) is higher than the high-level input voltage standard (V□), the potential of the input terminal (11) becomes higher than the transition voltage (V+7), and the signal level (VIN ) is at a low potential level below the low-level input voltage standard (Vat), the transistor size of the pull-up PMOS-FET (14) is adjusted so that the potential of the input terminal (11) is lower than the transition voltage (Vat). is being designed.

Furthermore, the input buffer circuit (+3) as an inverter
PMOS-FET (15) and NM
The transistor size of O5-FET (16) is the pull-up PMOS-FET designed as described above.
(14) is designed to satisfy the high level input voltage standard (■, ) and low level input voltage standard (V +t) of the input circuit (10). That is, transition voltage (■, T), high level input voltage standard (
The relationship between VIM) and the low level input terminal standard (vIL) is: ■1□>VIT>VIL.

By the way, when no signal is supplied to the input terminal (11) from the outside and the input terminal (11) becomes a high impedance state, the pull-up PMOS-FET (+4)
is always conductive, so the input buffer circuit (
13) PMO5-FET (15) and NM
As a result, a high potential level is supplied to the gate terminal (G) of the OS-FET (16) via the pull-up PMOS-FET (14).
(15) enters the cut-off state, and NMOS-FET (1
6) becomes conductive, and the output terminal (12) transmits a low potential level to the internal circuit.

If this pull-up PMOS-FET (14) is not present, when the input terminal (11) becomes a high impedance state, the PMOS-FET (15) and NMOS-FET in the input buffer circuit (13)
(16) both become conductive, and both these FETs
A large through current flows through (15) and (16), causing both F
ET (15) and (16) are destroyed.

In other words, when the pull-up PMOS-'FET (14) is in a high impedance state, the input terminal (11)
By forcing the potential of NM to a high potential level, NM
While the OS-FET (16) is made conductive, the PMO
By cutting off SFET (15), through current is prevented.

<Problems to be Solved by the Invention> The input circuit (10) incorporating the conventional pull-up PMOS-FET (14) has a problem in that the input terminal (11) is not applied with an external signal to the input terminal (11). When the high impedance state is entered, the potential of the input terminal (11) is forced to a high potential level by the pull-up PMO5-FET (14), so when the high impedance state is entered, Regardless of whether the signal level (VIN) applied to the input terminal (11) just before that is a high potential level or a low potential level, the level transmitted to the internal circuit is fixed at the low potential level. Therefore, such an input circuit (lO) cannot be applied to an internal circuit whose state must not change even when it is in a high impedance state, such as a clock input or reset input of a flip-flop circuit. The problem was that it was not possible.

This invention was devised to solve the above-mentioned inconvenience, and when an external signal is not input to the input terminal and the input terminal enters a high impedance state, the signal level immediately before this is maintained. The purpose is to provide an input circuit that can

Means for Solving the Problems> An input circuit according to the present invention includes an input buffer circuit inserted between an input terminal and an output terminal, and a circuit between the input side of the input buffer circuit and a high potential side power supply. and a pull-down NM connected between the input side of the input buffer circuit and the low potential side power supply.
a first transistor connected between the OS-FET and the input terminal and the gate terminal of the pull-up PMOS-FET;
a logic inversion circuit, the input terminal and the pull-down N
a second logic inversion circuit connected between the gate terminal of the MOS-FET, and a transition voltage of the first logic inversion circuit is set lower than a transition voltage of the input buffer circuit; The present invention is characterized in that a transition voltage of the second logic inversion circuit is set higher than a transition voltage of the input buffer circuit.

<Function> The function of the above configuration of the input circuit according to the present invention is as follows.

When the signal level applied to the input terminal is higher than the high-level input voltage standard designed to transition the input buffer circuit to one state, this applied signal level naturally It becomes higher than each transition voltage of the logic inversion circuit No. 2. Therefore, the potentials supplied from the first and second logic inverting circuits to the gate terminals of the pull-up PMO5-FET and the pull-down NMOS-FET become low potential levels, and the pull-up PMO
While the S-FET becomes conductive, the pull-down N
MO5-FET is in a cut-off state.

If the signal is no longer supplied from this state and the input terminal becomes a high-impedance state, the signal level applied to the input terminal immediately before that was higher than the high-level input voltage standard, so The first and second logic inversion circuits keep their outputs at the previous low potential level, and the pull-up PMO
5-FET conduction state and pull-down NMOS -
The cut-off state of the FET will be maintained as it is.

Conversely, when the signal level applied to the input terminal is lower than the low-level input voltage standard designed to transition the input buffer circuit to the other state, this applied signal level will naturally Since it is lower than each transition voltage of the first and second logic inversion circuits, the potential supplied from the first and second logic inversion circuits to each gate terminal of the pull-up PMOS-FET and the pull-down NMO5-FET is It becomes a high potential level, and PMOS-F for pull-up
While ET is in the cutoff state, NMO5 for pulldown
-FET becomes conductive. Even if the signal is no longer supplied from this state and the input terminal becomes a high-impedance state, the signal level applied to the input terminal immediately before that was lower than the low-level input voltage standard. The first and second logic inversion circuits maintain their outputs at the previous high potential level, and the cut-off state of the pull-up PMO5-FET and the conductive state of the pull-down NMO5-FET are maintained as they are. Become.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 shows a circuit diagram of an input circuit according to an embodiment of the present invention.

In Fig. 1, the symbol (1) is an input circuit configured between an external signal line and an internal circuit (none of which is shown) in the integrated circuit, and (11) is an input circuit configured between the input circuit (1) and the external signal line. The input terminal to be connected, (12) is the output terminal to which the input circuit (1) is connected to the internal circuit, and (13) is the input buffer inserted between the input terminal (11) and the output terminal (12). It is a circuit. This input buffer circuit (13) consists of a PMOS-FET (15) and an NMOS
-FET (16), and is configured to have an inverter function. The circuit configuration of this input buffer circuit (13) is the same as that of the conventional example explained in FIG. 3, so the same reference numerals are given here and the explanation thereof will be omitted.

In addition, the code (14) in the figure is a PMOS-F for pull-up.
ET, whose source terminal (S) is high potential measurement a(V
n++) and its drain terminal (D
) is the input terminal (11) and input buffer circuit (13)
PMO5-FET (15) and NMOS-F
ET (16) and each gate terminal (G). In addition, this pull-up PMOS-FET
Although the gate terminal (G) of (14) is connected to the low potential side power supply (Vcso) in the conventional example, in this example, it is connected to the output terminal of the first logic inverting circuit (2). It is connected. The input terminal of this first logic inversion circuit (2) is connected to the input terminal (11) of the input circuit (1).
)It is connected to the.

Furthermore, in this embodiment, the pull-down NMOS-
A FET (3) and a second logic inversion circuit (4) are used. And this NMOS-FE for pull-down
T (3) has its source terminal (S) on the low potential side a
(VcNo), and its drain terminal (D) is connected to the input terminal (11) and the 2MO3-FET (15) and NMOS-FET (1) in the input buffer circuit (13).
6), and the gate terminal (G) is connected to the output terminal of the second logic inversion circuit (4). On the other hand, the input terminal of this second logic inversion circuit (4) is connected to the input terminal (11).

FIG. 2 shows the relationship between each transition voltage. First, the transition voltage (V
R□) is the transition voltage (VI
? ) and higher than the low-level input voltage standard (Vat) of the input circuit (1). The transition voltage (VR-) of the second logic inverting circuit (4) is higher than the transition voltage (VI?) of the human-powered Huffa circuit (13), and also meets the high-level input voltage standard of the input circuit (1). (VIN). That is,
Vlll>VI14>VI ding>VRz>VIL.

By the way, for boat fishing, 2MO3-FET and NMOS-F
The approximate value of the transition voltage of an inverter with a CMO3 structure consisting of ET can be obtained using the following equation.

to 1+ β9 2 = β.

In this formula, the meaning of each symbol is: VT)l: Inverter transition voltage ■. . : High potential side is source level VTMP : Dark value voltage of 2MO3FET■7□ :N
Threshold voltage K of MOS-FET: Conductance ratio βp of 2MO3-FET and NMOS-FET: Conductance β of PMO5FET, :NM
Conductance of O5-FET At this time, each voltage is based on the low potential side power supply level.

And conductance β7. β8 is the respective MO
When the gate width of the S-FET is W and the gate length is L, it is approximately proportional to W/L. Therefore, by appropriately designing the transistor size (gate width, gate length) of the 2MO3-FET and NMOS-FET that constitute the inverter, it is possible to control the transition voltage of the inverter.

Next, the operation of the input circuit (1) according to this embodiment will be explained.

First, the operation when a signal is applied to the input terminal (11) from the outside will be described.

The signal level (VIN) applied to the input terminal (11) is the high level input voltage standard (Vllll) of the input circuit (1).
, and therefore, when its signal level (V+s) is higher than the transition voltage (Vat) of the input buffer circuit (13), the two constituting the input buffer circuit (13)
MO3-FET (15) is cut off and NMOS
-FET (16) becomes conductive. Therefore, the output terminal (12) is connected to the low potential power supply (■.HD), and transmits a low potential level to the internal circuit. Note that this operation is similar to the conventional example.

At this time, the signal level (■,) applied to the input terminal (11) is the transition voltage (VRZ) of the first logic inversion circuit (2) and the transition voltage of the second logic inversion circuit (4). Since the voltage is higher than the voltage (V□4), the first logic inverting circuit (2
) is supplied to the gate terminal (G) of the pull-up PMOS-FET (14) at a low potential level.

Therefore, the pull-up PMOS-FET (14) becomes conductive, and the potential supplied from the second logic inversion circuit (4) to the gate terminal (G) of the pull-down NMOS-FET (3) also becomes a low potential level. NM for pulldown
OS-FET (3) enters the cut-off state.

Also, contrary to the above case, the signal level (V's) applied to the input terminal (11) is lower than the low level input voltage standard (VIL) of the input circuit (1), and therefore,
The signal level (VIN) is the input buffer circuit (13)
When the transition voltage (VI?) is lower than the transition voltage (VI?), the 2MO3-FET (15) in the input buffer circuit (13) becomes conductive, and the NM05-FET (16) becomes cutoff. Therefore, the output terminal (12) is connected to the high potential side fi.
(voo) and transmits a high potential level to the internal circuitry.

Note that this operation is also similar to the conventional example.

At this time, the signal level (■,) applied to the input terminal (11) is the transition voltage (VR□) of the first logic inversion circuit (2) and the transition voltage of the second logic inversion circuit (4). (V□), the potential supplied from the first logic inversion circuit (2) to the gate terminal (G) of the pull-up PMOS-FET (14) becomes a high potential level. As a result, the pull-up PMOS-FET (14) is cut off, and the potential supplied from the second logic inversion circuit (4) to the gate terminal (G) of the pull-down NMO5-FET (3) is also at a high potential level. NMO for pulldown
S-FET (4) becomes conductive.

Next, the operation when no signal is supplied from the outside to the input terminal (11) and the input terminal (11) enters a high impedance state will be described.

From a state where the signal level (Vll) applied to the input terminal (11) is higher than the high level input voltage standard (VIM) (S<the potential of the output terminal (12) in this state is a low potential level) to a high impedance state When the first
The second logic inverting circuits (2) and (4) keep their outputs at the previous low potential level, and the pull-up PMO
N for conduction state and pull-down of S-FET (14)
The cut-off state of MOS-FET (3) is maintained as it is.

In other words, the input terminal (11) is connected to the pull-up PMO5-
T high potential side is (■.,) through FET (t4)
PMOS-FET (15) and NMOS-FET in the input buffer circuit (13)
A high potential level is continuously supplied to the gate terminal CG of (16), and the PMOS-FET (15) is maintained in the cut-off state and the NMOS-FET (16) is maintained in the conductive state. Therefore, the potential transmitted from the output terminal (12) to the internal circuit is maintained at the same low potential level as before entering the high impedance state.

Furthermore, as mentioned above, when the NMOS-FET (16) is in the conductive state, the PMOS-FET (15) is in the cut-off state, so that a through current is prevented from flowing through both FETs (15) and (16). Its original function will also be demonstrated.

Also, contrary to the above case, the signal level (vIN) applied to the input terminal (11) is set to the low level input voltage standard (
VIL) is lower than the state (output terminal (in this state)
12) becomes a high impedance state from a high potential level), the first and second logic inverting circuits (2) and (4) keep their outputs at the previous high potential level and pull The cut-off state of the up PMO5-FET (14) and the conductive state of the pull-down NMOS-FET (3) are maintained as they are.

That is, the input terminal (11) is a pull-down NMOS-
Since it is connected to the low potential side power supply (VGND) via FET (3), P in the input buffer circuit (13)
MO5-FET (15) and NMOS-FET (
A low potential level is continuously supplied to the gate terminal (G) of the output terminal (16), and the conduction state of the PMOS-FET (15) and the cut-off state of the NMOS-FET (16) are maintained, so that the output terminal (12) The potential transmitted from to the internal circuit will be maintained at the same high potential level as before entering the high impedance state. In addition, in this case, P
When MOS-FET (15) is conductive, NMOS
- Since FET (16) is in the cut-off state, both FETs
(15) and (16) also perform their original function of preventing through current from flowing.

As described above, according to this embodiment, even when no external signal is input to the input terminal (11) and the input terminal (11) enters a high impedance state, the pull-up P
MOS-FET (14), NMOS-F for pulldown
ET (3) and the first and second connected to these
As a result, the potential level of the input terminal (11) is held at the previous signal level by the self-holding function of the logic inversion circuits (2) and (4), and as a result, the potential transmitted from the output terminal (12) to the internal circuit is also the same as the previous one. It is possible to maintain this level.

By the way, in the above operation explanation, input terminal (11
), the signal level (VIN) immediately before the external signal is no longer input to the high-level input voltage standard (VI
M> or lower than the low-level input voltage standard (Vat) has been described, but as an exceptional operation, when no signal is input to the input terminal (11), this input circuit When the integrated circuit including (1) is powered on, the potential level (VIN) of the input terminal (11) may become V hole 4≧VIN≧Vat.

When such a state occurs, the output of the first logic inversion circuit (2) becomes a low potential level and the pull-up P
At the same time as MOS-FET (14) becomes conductive,
The output of the second logic inversion circuit (4) becomes a high potential level, and the pull-down NMOS-FET (3) also becomes conductive, causing a large amount of current to flow through both FETs (14) and (3). There is a risk that both FETs (14) and (3) may be destroyed, or that the potential transmitted from the output terminal (12) to the internal circuit will always be forced to a high potential level. However, the above problem can be solved by appropriately designing the resistance (on resistance) in the conductive state of the pull-up (14) and pull-down NMOS-FET (3).

That is, if the on-resistances of both FETs (1 4) and (3) are (R14) and (R3),
The potential level (VIN) of the input terminal (11) is R.

VIN=VDD’ RI4+R3 It is expressed as

Therefore, when the power is turned on, the potential level (VIN) of the input terminal (11) is lower than the transition voltage (Vat) of the first logic inversion circuit (2), that is, (V, N<V, .
), both FETs (1 4).

By designing the on-resistance (R., ) of (3), (Ri), the first and second logic inverting circuits (2),
The outputs of (4) are both at a high potential level, making it possible to turn off the pull-up PMOS-FET (14) and turn on the pull-down NMOS-FET (3).

Further, the potential level (V IN) is higher than the transition voltage (Vat4) of the second logic inversion circuit (4), that is,
PM for pull-up so that (VIN>V114)
OS-FET (1 4) and pull-down NMOS
-On resistance (RI4) of FET (3), (R3
), when the power is turned on, the outputs of the first and second logic inversion circuits (2) and (4) both become a low potential level, and the pull-up PMOS-FE
T (1 4) is in conductive state, NMOS- for pull-down
FET (3) can be turned off.

As a result, in both cases, both FETs (1 and 4).

(4) It is possible to prevent a through current from flowing. In the former case (V+s<V++t), the potential transmitted from the output terminal (12) to the internal circuit is forced to a high potential level, and in the latter case (VIN>V114), the potential transmitted to the internal circuit is forced to a high potential level. The potential at which the current occurs is forced to a low potential level.

<Effects of the Invention> As explained above, in the present invention, the first logical inversion having a transition voltage lower than the transition voltage of the input buffer circuit between the input terminal and the gate terminal of the pull-up PMOS-FET is provided. A second logic inversion circuit having a transition voltage higher than the transition voltage of the input buffer circuit is connected between the input terminal and the gate terminal of the pull-down NMOS-FET. Therefore, even if a signal is no longer supplied to the input terminal and the input terminal enters a high-impedance state, if the signal level applied to the input terminal immediately before that is higher than the high-level input voltage standard, the pull-up While the conduction state of the pull-down PMOS-FET and the cut-off state of the pull-down NMOS-FET are maintained, when the signal level applied immediately before is lower than the low-level input voltage standard,
As a result of maintaining the cut-off state of the pull-up PMOS-FET and the conductive state of the pull-down NMO5-FET, the potential level transmitted from the output terminal of the human cover sofa circuit to the internal circuit can be maintained at the previous state.

In addition, if the on-resistance of the pull-up PMO5FET and the pull-down NMOS-FET is set so that the potential level of the input terminal is lower than the transition voltage of the first logic inversion circuit, or if the potential level of the input terminal is Second
If the transition voltage is set to be higher than the transition voltage of the logic inversion circuit, a through current will be generated in the pull-up PMOS-FET and pull-down NMO5-FET when the power is turned on with no signal input. This has the effect of preventing the flow of water.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an input circuit according to an embodiment of the present invention;
FIG. 2 is a diagram showing the relationship between each transition voltage, and FIG. 3 is a circuit diagram of a conventional input circuit. In the figure, (1) is an input circuit, (2) is a first logic inversion circuit, (3) is a pull-down NMO5-FET, (
4) is the second logic inversion circuit, (11) is the input terminal, (1
2) is the output terminal, (13) is the input buffer circuit, (14
) is the pull-up PMO8-FET, (■...) is the high potential side power supply, (■GNゎ) is the low potential side power supply, (Vat) is the transition voltage of the input buffer circuit, (V+o) is the high voltage of the input circuit. The level input voltage standard, (VIL) is the low level input voltage standard of the input circuit, (V++z) is the transition voltage of the first logic inversion circuit, and (V□) is the transition voltage of the second logic inversion circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (3)

[Claims] (1) An input buffer circuit inserted between the input terminal and the output terminal, and a P-channel field-effect transistor (hereinafter referred to as a pull-out transistor) connected between the input side of this input buffer circuit and the high-potential side power supply. an N-channel field effect transistor (hereinafter referred to as a pull-down NMOS-FET) connected between the input side of the input buffer circuit and the low potential side power supply; a first logic inversion circuit connected between the gate terminal of the pull-up PMOS-FET; and a second logic inversion circuit connected between the input terminal and the gate terminal of the pull-down NMOS-FET. a transition voltage of the first logic inversion circuit is set lower than a transition voltage of the input buffer circuit, and a transition voltage of the second logic inversion circuit is set lower than a transition voltage of the input buffer circuit. The input circuit is characterized in that the input voltage is also set high. (2) The on-resistance of the pull-up PMOS-FET and the pull-down NMOS-FET is set so that the potential level of the input terminal is lower than the transition voltage of the first logic inversion circuit. An input circuit according to claim (1). (3) The on-resistance of the pull-up PMOS-FET and pull-down NMOS-FET is set so that the potential level of the input terminal is higher than the transition voltage of the second logic inversion circuit. An input circuit according to claim (1).