JPH03230536A - Semiconductor device - Google Patents

Abstract

PURPOSE:To simplify judgement of the intactness of profile by constituting a conducting layer in a ring type on the peripheral part. CONSTITUTION:In a semiconductor element 1, a low resistance metal layer 2 as a conducting layer is formed by plating process and the like, while a cutting margin 1a for a dicing saw is left. The metal layer 2 is formed in a ring type along the peripheral part of the upper surface of a semiconductor element 1. When a damage is generated in the outer shape of the semiconductor element 1 itself, the damage is generated at the same time also in the metal layer 2. Whether the damage is present is measured as the change of electric resistance of the metal layer 2, by using a pair of probe electrodes 3, 3. Thereby the quality can very easily be judged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention mainly relates to a semiconductor element that is picked up from the state of being stuck on an expandable tape and mounted on a desired substrate or the like.

[Conventional technology]

In semiconductor device mounting work, when picking up a semiconductor device chip from an expanded tape, it is important to judge the quality of the external shape of the chip and eliminate chips and knobs that have chipping that may develop into cracks. This is extremely important for improving the quality of devices (ensuring yield).

However, with conventional semiconductor chips, no processing is applied to the chip itself to provide a clue as to whether the external shape is good or bad. Computer processing is performed to extract the external shape and make a determination.

[Problem to be solved by the invention]

Such a conventional optical discrimination device itself has a complicated structure and is an expensive equipment. Furthermore, in order to obtain a clear image that serves as a reference for determination, adjustment work such as angle and position adjustment of illumination is required for each type of semiconductor element chip, resulting in poor work efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element whose external shape can be determined extremely easily.

[Means to solve the problem]

In order to achieve the above object, the present invention is characterized in that a conductive layer is formed in a ring shape on the periphery.[Function] Since the ring-shaped conductive layer is formed on the periphery of the upper surface of the semiconductor element, If a physical defect or the like occurs at the peripheral edge of a semiconductor element, this conductive layer is also damaged or defective, and this state can be extracted as an electrical characteristic value of the conductive layer.

〔Example〕

A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

This semiconductor element 1 has a cutting margin 1a of a dicing saw at the peripheral edge of its upper surface, and has a low resistance metal layer 2 which is a conductive layer.
is formed by plating or the like. The metal layer 2 is formed in a ring shape along the periphery of the upper surface of the semiconductor element 1, so that at the same time as a defect occurs in the external shape of the semiconductor element 1 itself, a defect also occurs in the metal layer 2. (
(See Figure 2(b)).

That is, if the metal layer 2 is not damaged by dicing as shown in FIG. 2(a), it can be determined that the external shape of the semiconductor element 1 is appropriate, and the chipping 1 is not damaged as shown in FIG. 2(b).
If b occurs and the metal layer 2 is damaged, it can be determined that the external shape of the semiconductor element 1 is inappropriate.

The presence or absence of this damage, that is, the quality of the external shape of the semiconductor element 1, is determined when picking up the semiconductor element 1 from the expanded tape during the mounting work of the semiconductor element 1. ) is extremely important in achieving this goal. Therefore, the presence or absence of this damage can be determined by Cj using a pair of probe electrodes 3.3 as a change in the electrical resistance value of the metal layer 2, as shown in FIG. The measurement results can be used to determine whether or not to pick up the semiconductor element 1 and mount it on a board or package. Note that instead of the metal layer 2, a diffused resistor formed on the surface may be used.

When the resistance value of the semiconductor element 1 as shown in FIG. 2(a) is measured using a pair of probe electrodes 3, 3, the measured value becomes almost the designed low resistance value, and there is no damage to the metal layer 2.
That is, it can be determined that the external shape of the semiconductor element 1 is appropriate. Similarly, when the resistance value of the semiconductor element 1 in which chipping 1b has occurred on the peripheral edge as shown in FIG. It can be determined that the external shape of No. 1 is inappropriate. Specifically, the metal layer 2 is T i /
P t / A u (A u : 5000 A
) with a width of 10 μm, the resistance value per mm of length will be approximately 60Ω. If this metal layer 2 is formed, for example, at a position 10 μm from the edge of the semiconductor element 1, chipping 1b of 20 μm or more can be reliably monitored.

A pair of probe electrodes 3, 3 in contact with the metal layer 2 of the semiconductor element 1 are connected to a measuring section 4, and the measuring section 4 measures the metal layer 2.
The electrical resistance value is measured. At the time of mounting, a large number of semiconductor elements 1 are pasted on an expandable tape 5, and a probe electrode 33 is pressed against this to measure the resistance value of the metal layer 2.

Based on this measured value, a control device (not shown) determines whether or not to pick up the semiconductor element 1. If the semiconductor element 1 is to be picked up, a pickup device (not shown) is driven; if not, the next semiconductor element 1 is driven. It is possible to move on to measuring the resistance value of the element 1.

In this way, defects in the external shape of the semiconductor element 1 are removed from the metal layer 2.
, and the electrical resistance value of metal layer 2 is replaced by CI
By determining this, it is possible to determine whether the external shape of the semiconductor element 1 is good or bad. Therefore, by configuring this semiconductor element as in the embodiment, the device can be extremely simplified and determination can be made in a short time.

Furthermore, since the metal layer 2 is simply formed on the surface of the semiconductor element 1, the manufacturing cost of the semiconductor element 1 does not increase significantly. Furthermore, by adjusting the width and formation position of the metal layer 2, the standard for determining the quality of the semiconductor element 1 can be arbitrarily set in accordance with various types of elements.

On the other hand, based on the measured electrical resistance value, the semiconductor element 1
By determining whether or not to pick up a defective semiconductor element 1, the trouble of picking up a defective semiconductor element 1 can be saved, and the mounting work can be made even more efficient.

Note that in this embodiment, the metal layer 2 is formed on the top surface of the semiconductor element 1, but the metal layer 2 may be embedded inside the peripheral portion or may be formed on the bottom surface. . In other words, it is sufficient that the semiconductor element 1 is formed at a position where the external shape of the semiconductor element 1 is damaged at the same time as the contact portion of the probe electrode 3 is damaged.

〔Effect of the invention〕

As described above, according to the present invention, the quality of the external shape can be confirmed as defects in the conductive layer formed on the peripheral edge.
This has the effect of making it extremely easy to determine whether it is good or bad.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a semiconductor chip according to an embodiment of the present invention, FIG. 2 is a plan view showing the chip in its defective state, and FIG. 3 is a side view showing the chip in its defective state. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 1a... Cutting allowance, ]b... Chipping, 2... Metal layer. Fig. 1 Judging the quality of the chip Fig. 2 Fig. 3

Claims (1)

[Claims] A semiconductor device characterized in that a conductive layer is formed in a ring shape at a peripheral portion.