JPH03230536A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03230536A JPH03230536A JP2635190A JP2635190A JPH03230536A JP H03230536 A JPH03230536 A JP H03230536A JP 2635190 A JP2635190 A JP 2635190A JP 2635190 A JP2635190 A JP 2635190A JP H03230536 A JPH03230536 A JP H03230536A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metal layer
- damage
- external shape
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 abstract description 24
- 239000000523 sample Substances 0.000 abstract description 6
- 238000007747 plating Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 5
- 230000002950 deficient Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、主としてエキスバンドテープ上で貼着された
状態からピックアップされ、所望の基板等へ実装される
半導体素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention mainly relates to a semiconductor element that is picked up from the state of being stuck on an expandable tape and mounted on a desired substrate or the like.
半導体素子の実装作業において、エキスバンドテープ上
から半導体素子チップをピックアップする際に、チップ
の外形形状の良否を判定し、クラックに発展するような
チッピングを有するチ・ノブを排除することは、その後
のデバイスの品質の向上(歩留りの確保)を図る上で極
めて重要である。In semiconductor device mounting work, when picking up a semiconductor device chip from an expanded tape, it is important to judge the quality of the external shape of the chip and eliminate chips and knobs that have chipping that may develop into cracks. This is extremely important for improving the quality of devices (ensuring yield).
しかるに、従来の半導体素子チップはチップ自体に外形
形状の良否を判別する手掛かりとなるような処理が施さ
れることはなく、−前曲には、テレビモニタ等により入
力した半導体素子チップの画像を計算機処理し、その外
形形状を抽出して判定するようにしている。However, with conventional semiconductor chips, no processing is applied to the chip itself to provide a clue as to whether the external shape is good or bad. Computer processing is performed to extract the external shape and make a determination.
このような従来の光学的な判別装置は、それ自体構造が
複雑で、高価な設備となっていた。また、判定の基準と
なる鮮明な画像を得るため、半導体素子チップの種類毎
に照明の角度や位置調整等の調整作業が必要で作業能率
が悪いものとなっていた。Such a conventional optical discrimination device itself has a complicated structure and is an expensive equipment. Furthermore, in order to obtain a clear image that serves as a reference for determination, adjustment work such as angle and position adjustment of illumination is required for each type of semiconductor element chip, resulting in poor work efficiency.
本発明は、外形形状の良否の判定を極めて簡単に行い得
る半導体素子を提供することをその目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element whose external shape can be determined extremely easily.
本発明は上記目的を達成すべく、周縁部に導電層をリン
グ状に形成したことを特徴とする特〔作用〕
リング状の導電層が半導体素子の上面の周縁部に形成さ
れているので、半導体素子の周縁部に物理的な欠損等が
生じていると、この導電層も損傷を受は欠損しているこ
ととなり、この状態は導電層の電気的特性値として抽出
することができる。In order to achieve the above object, the present invention is characterized in that a conductive layer is formed in a ring shape on the periphery.[Function] Since the ring-shaped conductive layer is formed on the periphery of the upper surface of the semiconductor element, If a physical defect or the like occurs at the peripheral edge of a semiconductor element, this conductive layer is also damaged or defective, and this state can be extracted as an electrical characteristic value of the conductive layer.
第1図および第2図を参照して本発明の実施例に係る半
導体素子について説明する。A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.
この半導体素子1は、その上面の周縁部にダイシングソ
ーの切り代1aを存して導電層である低抵抗の金属層2
がメツキ処理等により形成されている。金属層2は半導
体素子1の上面の周縁部に沿ってリング状に形成されて
おり、半導体素子1自体の外形形状に欠損が生じると同
時にこの金属層2にも欠損が生じるようになっている(
第2図(b)参照)。This semiconductor element 1 has a cutting margin 1a of a dicing saw at the peripheral edge of its upper surface, and has a low resistance metal layer 2 which is a conductive layer.
is formed by plating or the like. The metal layer 2 is formed in a ring shape along the periphery of the upper surface of the semiconductor element 1, so that at the same time as a defect occurs in the external shape of the semiconductor element 1 itself, a defect also occurs in the metal layer 2. (
(See Figure 2(b)).
すなわち、ダイシングにより第2図(a)のように金属
層2が損傷しなければ、半導体素子1の外形形状は適切
であると判断でき、第2図(b)のようにチッピング1
bが生じて金属層2が損傷していれば、半導体素子1の
外形形状は不適切と判断できる。That is, if the metal layer 2 is not damaged by dicing as shown in FIG. 2(a), it can be determined that the external shape of the semiconductor element 1 is appropriate, and the chipping 1 is not damaged as shown in FIG. 2(b).
If b occurs and the metal layer 2 is damaged, it can be determined that the external shape of the semiconductor element 1 is inappropriate.
この損傷の有無、すなわち半導体素子1の外形形状の良
否の判別は、半導体素子1の実装作業において、エキス
パンドテープ上から半導体素子1をピックアップする際
に、その後のデバイスの品質の向上(歩留りの確保)を
図る上で極めて重要である。そこで、この損傷の有無は
、第3図に示すように金属層2の電気的抵抗値の変化と
して一対のプローブ電極3.3を用いてCj定すること
ができる。その測定結果は、半導体素子1をピックアッ
プして基板やパッケージに実装するか否かの決定に用い
ることかできる。なお、金属層2に代えて、表面に形成
した拡散抵抗体でもよい。The presence or absence of this damage, that is, the quality of the external shape of the semiconductor element 1, is determined when picking up the semiconductor element 1 from the expanded tape during the mounting work of the semiconductor element 1. ) is extremely important in achieving this goal. Therefore, the presence or absence of this damage can be determined by Cj using a pair of probe electrodes 3.3 as a change in the electrical resistance value of the metal layer 2, as shown in FIG. The measurement results can be used to determine whether or not to pick up the semiconductor element 1 and mount it on a board or package. Note that instead of the metal layer 2, a diffused resistor formed on the surface may be used.
一対のプローブ電極3,3により第2図(a)こ示すよ
うな半導体素子1の抵抗値を測定すると、測定値はほぼ
設計された低抵抗値となり金属層2に損傷が無いこと、
すなわち半導体素子1の外形形状が適切であることが判
別できる。同様に第2図(b)に示すような周縁部にチ
ッピング1bが生じている半導体素子1の抵抗値を測定
すると、測定値は高抵抗値となり金属層2に損傷がある
こと、すなわち半導体素子1の外形形状が不適切である
ことが判別できる。具体的には、金属層2をT i /
P t / A u (A u : 5000 A
)を幅10μmで形成すると、長さ1mm当たりの抵抗
値は約60Ωとなる。そして、この金属層2を例えば半
導体素子1のエツジから10μmの位置に形成しておけ
ば、20μm以上のチッピング1bは確実にモニタが可
能となる。When the resistance value of the semiconductor element 1 as shown in FIG. 2(a) is measured using a pair of probe electrodes 3, 3, the measured value becomes almost the designed low resistance value, and there is no damage to the metal layer 2.
That is, it can be determined that the external shape of the semiconductor element 1 is appropriate. Similarly, when the resistance value of the semiconductor element 1 in which chipping 1b has occurred on the peripheral edge as shown in FIG. It can be determined that the external shape of No. 1 is inappropriate. Specifically, the metal layer 2 is T i /
P t / A u (A u : 5000 A
) with a width of 10 μm, the resistance value per mm of length will be approximately 60Ω. If this metal layer 2 is formed, for example, at a position 10 μm from the edge of the semiconductor element 1, chipping 1b of 20 μm or more can be reliably monitored.
半導体素子1の金属層2に接触する一対のプローブ電極
3,3は測定部4に接続され、この測定部4で金属層2
の電気的抵抗値を測定される。半導体素子1は実装に際
し、エキスパンドテープ5上に多数貼着されており、こ
れにプローブ電極33が押し当てられ金属層2の抵抗値
が測定される。A pair of probe electrodes 3, 3 in contact with the metal layer 2 of the semiconductor element 1 are connected to a measuring section 4, and the measuring section 4 measures the metal layer 2.
The electrical resistance value is measured. At the time of mounting, a large number of semiconductor elements 1 are pasted on an expandable tape 5, and a probe electrode 33 is pressed against this to measure the resistance value of the metal layer 2.
この測定値に基づいて図外の制御装置により半導体素子
1をピックアップするか否かが決定され、ピックアップ
する場合にはピックアップ装置(図示せず)を駆動させ
るし、ピックアップしない場合には次の半導体素子1の
抵抗値の測定に移るようにすることができる。Based on this measured value, a control device (not shown) determines whether or not to pick up the semiconductor element 1. If the semiconductor element 1 is to be picked up, a pickup device (not shown) is driven; if not, the next semiconductor element 1 is driven. It is possible to move on to measuring the resistance value of the element 1.
このように、半導体素子1の外形形状の欠損を金属層2
の欠損として置き換え、金属層2の電気的抵抗値をCI
定することで、半導体素子1の外形形状の良否を判定で
きる。したがって、この半導体素子を実施例のように構
成することで装置がきわめて簡素化でき、短時間で判定
が可能になる。In this way, defects in the external shape of the semiconductor element 1 are removed from the metal layer 2.
, and the electrical resistance value of metal layer 2 is replaced by CI
By determining this, it is possible to determine whether the external shape of the semiconductor element 1 is good or bad. Therefore, by configuring this semiconductor element as in the embodiment, the device can be extremely simplified and determination can be made in a short time.
また、単に半導体素子1の表面に金属層2を形成するだ
けなので、半導体素子1の製造コストが特段にアップす
ることもない。さらに、金属層2の幅や形成位置を調整
することで、半導体素子1の良否の基準を各種の素子に
合わせて任意に設定できる。Furthermore, since the metal layer 2 is simply formed on the surface of the semiconductor element 1, the manufacturing cost of the semiconductor element 1 does not increase significantly. Furthermore, by adjusting the width and formation position of the metal layer 2, the standard for determining the quality of the semiconductor element 1 can be arbitrarily set in accordance with various types of elements.
一方、測定された電気的抵抗値に基づいて半導体素子1
をピックアップするか否かを判定するれば、不良な半導
体素子1をピックアップする手間が省け、実装作業をよ
り一層効率化することもできる。On the other hand, based on the measured electrical resistance value, the semiconductor element 1
By determining whether or not to pick up a defective semiconductor element 1, the trouble of picking up a defective semiconductor element 1 can be saved, and the mounting work can be made even more efficient.
なお、本実施例では、半導体素子1の上面に金属層2を
形成するようにしているが、金属層2は周縁部の内部に
埋め込まれていてもよく、下面に形成するようにしても
よい。すなわち、プローブ電極3の接触部を除き半導体
素子1が外形形状が損傷を受けたときに同時に損傷を受
ける位置に形成されていればよい。Note that in this embodiment, the metal layer 2 is formed on the top surface of the semiconductor element 1, but the metal layer 2 may be embedded inside the peripheral portion or may be formed on the bottom surface. . In other words, it is sufficient that the semiconductor element 1 is formed at a position where the external shape of the semiconductor element 1 is damaged at the same time as the contact portion of the probe electrode 3 is damaged.
以上のように本発明によれば、外形形状の良否を、その
周縁部に形成した導電層の欠損として確認できるので、
良否の判別がきわめて容易になる効果を有する。As described above, according to the present invention, the quality of the external shape can be confirmed as defects in the conductive layer formed on the peripheral edge.
This has the effect of making it extremely easy to determine whether it is good or bad.
第1図は本発明の一実施例に係る半導体チップの斜視図
、第2図はその欠損状態を示す平面図、第3図は欠損の
、4111定状態を示す側面図である。
1・・・半導体素子、1a・・切り代、]b・チッピン
グ、2・・・金属層。
芙旅例のす・ツブ
第1図
チップの良否の判別
第 2図
第3図FIG. 1 is a perspective view of a semiconductor chip according to an embodiment of the present invention, FIG. 2 is a plan view showing the chip in its defective state, and FIG. 3 is a side view showing the chip in its defective state. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 1a... Cutting allowance, ]b... Chipping, 2... Metal layer. Fig. 1 Judging the quality of the chip Fig. 2 Fig. 3
Claims (1)
半導体素子。A semiconductor device characterized in that a conductive layer is formed in a ring shape at a peripheral portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2635190A JPH03230536A (en) | 1990-02-06 | 1990-02-06 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2635190A JPH03230536A (en) | 1990-02-06 | 1990-02-06 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03230536A true JPH03230536A (en) | 1991-10-14 |
Family
ID=12191046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2635190A Pending JPH03230536A (en) | 1990-02-06 | 1990-02-06 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03230536A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101451889A (en) * | 2007-12-04 | 2009-06-10 | 富士能株式会社 | Systematic error correction method of interferometer |
-
1990
- 1990-02-06 JP JP2635190A patent/JPH03230536A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101451889A (en) * | 2007-12-04 | 2009-06-10 | 富士能株式会社 | Systematic error correction method of interferometer |
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