JPH03228443A - Input data synchronizing circuit - Google Patents

Abstract

PURPOSE:To easily select the synchronizing clock in a short time, and also, to simplify the input circuit of a Biphi-L code by utilizing a fact that a displacement point always exists in the center of a bit of a Biphi-L signal, and detecting its displacement point. CONSTITUTION:Inverters 13, 14, NAND gates 10, 11, an OR gate 12, an exclusive NOR gate 9, and flip-flops 4-8 are used. In such a state, the circuit is constituted of means 5, 6 and 9 for inputting a Biphi-L signal in which a displacement point exists in the middle of a bit and detecting a variation of data of the Biphi-L signal during an 'H' level by a synchronizing clock, and means 4, 7 for switching the synchronizing clock to that which is inverted in the case there is no variation by a result of detection the variation of the data. In such a way, a small circuit scale is enough, and the clock can be synchronized normally and quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input data synchronization circuit, and particularly to an input circuit for a PCM signal using a Biφ-recode.

[Conventional technology]

In conventional input data synchronization circuits of this type, the clock generated from the phase-locked loop circuit may be inverted and synchronized with the input data, and the inverted clock is used to synchronize Biφ-.
When L code is converted to NRZ-L code, the data is inverted, so check the contents of the data converted to NRZ-L, and if it is detected that the data is inverted, invert the input clock and try again. Check the input data,
I was entering data.

[Problem to be solved by the invention]

In the conventional input data circuit described above, there are two cases in which the phase difference between the input signal and the synchronized clock output from the phase-locked loop circuit is 90 degrees (positive phase) and 270 degrees (negative phase). However, when the input data is Biφ-L code, if the phase difference is 270 degrees and synchronization occurs, the data will be input inverted.

Therefore, in conventional input data synchronization circuits, data is input using a positive-phase or reverse-phase clock from a phase-locked loop circuit, and a check is made to see if the contents of the input data are inverted. Only when necessary, the clock is manually inverted, the input data is input again, and the data is checked. Therefore, a data inversion check circuit is required, which has the drawback of increasing the circuit scale.

In addition, a check code to determine whether or not the data is inverted is required in the data, and since the check code is determined for each check code, there is a drawback that it takes time until the clocks are properly synchronized.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input data synchronization circuit which solves the above-mentioned drawbacks, requires a small circuit scale, and quickly synchronizes clocks normally.

[Means to solve the problem]

The configuration of the input data synchronization circuit of the present invention is to input a Biφ-L signal with a shift point in the middle of the bits, and detect changes in data of the Biφ-L signal between “H” levels using a synchronization clock. The present invention is characterized by comprising a first means and a second means for switching the synchronization clock to an inverted one if there is no change as a result of detecting the change in the data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an input data synchronization circuit according to an embodiment of the present invention.

In FIG. 1, the present embodiment includes inverters 13, 14, NAND gates 10, 11, OR gate 12, exclusive NOR gate 9, flip-flops 4, 5, 6,
7.8.

In this embodiment, the input Biφ-L signal 1 is input to each of the inputs of the flip-flop 5, which is read at the rising edge of the clock, and the flip-flop 6, which is read at the falling edge of the clock.

The Q output of flip-flops 5 and 6 that read data is
Exclusive NOR (EX-NOR) to detect data deviations
Input to gate 9. The output of the EX-NOR gate 9 is input to the flip-flop 7.
By inputting the Q output of CLK to the toggle flip-flop 4, the clock 2 from the phase-locked loop is switched between positive phase and negative phase. In addition, by inputting the output of the flip-flop that detects the shift point to the flip-flop 8, and inputting the Q output of the flip-flop 8 to the reset (R) signal of the flip-flop 7, the input clock 2
Immediately after the switching is performed, the detection of the shift point of the Biφ-reference signal 1 is interrupted. At the output of the OR gate 12, Biφ-L
A synchronous clock 3 having a phase difference of 90'' from the signal is obtained.

The operation of this embodiment is as shown in the time chart of FIG. 2, when Biφ-L signal 1 and clock 2 are synchronized with opposite phases, and when "0" data is input. teeth,
Since there is a data shift at the "H" level of the synchronous clock 3, the outputs of the two flip-flops 5 and 6 are different from each other, so the output of the EX-NOR gate 9 goes to the "L" level. Therefore, clock switching is not performed. However, when the data of the Biφ signal 1 changes from "0" to "1", the 'H' level continues at an interval of 1 bit, and there is no deviation point between the 'H' level of the synchronized clock 3. .

Therefore, since the output of flip-flop 5.6 becomes the same data, the output of EX-NOR gate 9 becomes "H" level. By reading the output of the EX-NOR gate 9 into the flip-flop 7 at the rising edge of the synchronous clock 3, the output of the flip-flop 7 rises. This rise inverts the output of the toggle flip-flop 4 that selects the positive phase or negative phase of the clock 2, and the synchronous clock 3 is switched to the negative phase of the clock 2. On the other hand, the output of flip-flop 7 is input to the D input of flip-flop 8, and the synchronous clock 3
By reading at the rising edge of , the flip-flop 7, which detects the shift point for 1.5 bits after switching, is in a disabled state, and malfunctions due to switching are prevented.

After this switching operation, between the "H" level of the synchronous clock 3,
There will always be a shift point of the Biφ− signal l.

In this embodiment, as a means for automatically selecting the positive phase and negative phase clocks output from the phase-locked loop circuit, the method is not based on the content of the data, but is based on the midpoint of the bits, which is a characteristic of the Biφ-recode. The determination is made based on the correlation between the data bit and the clock.

FIG. 3 is a circuit diagram showing an input data synchronization circuit according to another embodiment of the present invention.

In FIG. 3, this embodiment has an ANDNO gate, 11
．． 16, an OR gate 12, an inverter 13, a flip-flop 4, a monostable multivibrator 17, and a shift point detector 15.

In this embodiment, the shift point detector 15 of the Biφ signal 1 is used, and the shift output of the signal and the synchronization clock 3 are input to the AND game) 16, and when the synchronization signal 3 is at the 11H'' level, Pick up the deviation point and input it to the retriggerable monostable multivibrator 17. Set the pulse width of the monostable multivibrator 17 to Biφ
- Set it to about 1.2 times of 1 bit of L signal 1) [.

As shown in FIG. 4, when the Biφ signal 1 and the clock 2 are synchronized with opposite phases, the Biφ signal 1 becomes “0”.
Alternatively, if "1" continues, a clock is input to the multivibrator 17 for each bit, so this output is always "1".
becomes H. Here, the Biφ-ri signal l becomes “0”, '1
”, the monostable multivibrator 1
The 7 clock inputs are 1.5 bits apart. Therefore, the output of the multivibrator 17 becomes "L" level once. Taking advantage of this fact, the clock 2 is switched. This embodiment has the advantage that the switching circuit is simplified.

According to this embodiment, in a Biφ signal input circuit having a phase-locked loop circuit, the bias of the B1φ signal present at the °H” level of the clock output from the phase-locked loop circuit as a data input clock is obtained. The transition point was detected and synchronized with the Biφ-L signal with a phase difference of 90 degrees.
The feature is that a positive phase or negative phase clock can be selected.

〔Effect of the invention〕

As explained above, the present invention takes advantage of the fact that a shift point always exists at the center of the bit, which is a characteristic of the Biφ-L signal, and has a detection circuit for the shift point, thereby making it possible to generate synchronized clocks. can be selected easily and in a short time, and Biφ-
This has the effect of simplifying the input circuit for the code.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an input data synchronization circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of FIG. 1, and FIG. 3 is a circuit diagram of another embodiment of the present invention. FIG. 4 is a timing diagram showing the operation of FIG. 3. l...Biφ-L signal, 2...Clock generated by phase lock roof, 3. Old...B
Synchronous clock with a phase difference of 90 degrees from the iφ signal, 4.
...Toggle flip float two j, 5. 6,7゜8...D type flip-flop, 9...mark...
EX-NOR gate, 10.11...AND
Gate, 12...OR gate, 13.14...
... Inverter, 15 ... Deviation point detector,
16...AND gate, 17...Retriggerable monostable multivibrator.

Claims (2)

[Claims] (1) Input the Biφ-L signal that has a shift point in the middle of the bit, and input the Biφ-L signal that has a shift point in the middle of the bit, and
A first means for detecting a change in the data of the φ-L signal, and a second means for switching the synchronization clock to an inverted one if there is no change as a result of detecting the change in the data. An input data synchronization circuit featuring: (2) Claim (1) wherein the first means includes first and second flip-flops that read at the rising edge and falling edge of the clock, respectively, and an exclusive NOR gate that receives the output of the flip-flop as input. Input data synchronization circuit described in section.