JPS5838027A - Phase difference detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a phase difference detecting output which always corresponds to the phase difference of two pulses, by controlling the inversion of an exclusive logical sum output of two pulses, in response to an output of a latch circuit latched in a prescribed timing. CONSTITUTION:Pulses WP and RP from a write controlling counter and a readout controlling counter are respectively applied to 1-bit counters 4 and 5, the output of which is applied to an exclusive OR circuit 10 of a phase difference detecting circuit 6. The output of the circuit 10 is applied to a terminal D of a latch circuit consisting of an FF12 and an exclusive OR circuit 11. In matching a clock CL of the FF12 to the pulse WP, a -Q output of the FF12 goes to 0 or 1 depending on 1 or 0 of the output of the circuit 10 at the falling time of the WP. Since the output of the circuit 10 and the -Q output of the FF12 are inputted to a circuit 11, the output of the circuit 11 goes to 1 at the falling time of the WP, and when the output of the circuit 10 is at 1, the output remains unchanged and when 0, the output is inverted. Thus, a detecting output proportional to the phase difference between the pulses WP and RP can be obtained independently of the initial state of the counters 4 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase difference detection circuit that detects a phase difference between three types of pulses such as a write clock and a read clock of a Batzer memory.

In the PCM signal receiving device, the received PCM signal is stored in the buffer memory using the clock extracted from the received PCM signal.
It has been adopted to synchronize the received PCM signal with the clock in the receiver by convolving the signal and reading the buffer memory using the clock in the receiver. In this case, a buffer memory of about 4 to 8 bits is used, and the phase difference between the writing timing to a position in the buffer memory and the reading timing from that position is determined by the period t-1 until writing to the same position. Generally, the period is 180'.

For example, as shown in FIG. 1, data Din synchronized with the write clock WCL is input, and the write clock WCL'
Data Din is sequentially written into the Batzer memory memory via a gate circuit controlled by the output of a write control counter l that counts t. The buffer memory 2 is read out via a gate circuit controlled by the output of the read control counter 3 that counts the read clock RCL t, and output data D out synchronized with the read clock RCL K is obtained.

The read clock RCL is output from the phase locked loop (PLL) 8, and is based on the phase difference between the output of the write control counter 1 and the output of the read control counter 3, that is, the write pulse and the read pulse for the same position in the buffer memory. The phase difference with the pulse is controlled to be 180°If-. Therefore, in addition to the write and read pulses wp and Rpt from the write control counter l and the read control counter 3, which determine the write timing and read tie setting for the same position in the batza memory 2, In addition to these output tube phase difference detection circuits 6, an output corresponding to the phase difference is added to an integrating circuit F to generate a phase synchronized circuit 80 control signal.

Assuming that the pulses WP and BP are shown in FIG. 2 (a) and (b), ! The output of bit counter 4.5 is shown in the same figure (C).

(A) When the phase difference detection circuit 6 is constructed of an exclusive OR circuit 9 as shown in FIG. 3, its output is as shown in FIG. 2(e). That is, the pulse WP
, BP is 180', the phase difference detection circuit 6
The output of the phase lock circuit 8 is in a stable state when the output is the pulse of the data 5o- and the level of the force pulse 4.

Furthermore, if the phase difference between the pulses wp,, RP is other than 180', the duty of the output pulse of the phase difference detection circuit 6 is other than the group corresponding to the phase difference, and the output level of the integrating circuit 7 is Therefore, the phase of the read clock RCL is controlled so that the integrated output level of the phase synchronized circuit 8 is in the expanded stable state.

However, depending on the initial state of the 1-bit counter 4.5,
If the phase difference between the pulses WP and RP is different by more than 1800, the duty of the output pulses of the phase difference detection circuit 6 will be different. For example, in Figure 314), Φ)
are the pulses WP and RP, and when the phase difference φ1 is 180° as shown by the solid line, the output of the 1-bit counter 4.5 is as shown in (0), (d) or (f), (b) in the same figure. The output of the phase difference detection circuit 6 is the fourth one (・) in the figure.
This is what is shown in X-ray (6). The outputs shown in Fig. 4 (・) and ω are simply inverted in phase, and both are due to the duty group.
Since the pulse is , the phase synchronization circuit 8 is in a stable state.

However, if the pulses WP and RP have a phase difference of φ1 and φ2, the output of the 1-bit counter S is the 41st!
I<2) changes as shown by the dotted line (d) or -, and thereby the output of the phase difference detection circuit 6 changes as shown by the dotted line ←) or (b) in Figure 4.

In other words, the phase difference detection circuit 6 when the phase difference φ1 is 18G'
Assuming that the output wavelength is 11tT1, when the phase difference is φ2, the pulse width of TI<'rg in FIG.
In addition, since the pulse width is 'I'1)T3 in the Kitsutsu diagram (turn), the level of the control signal applied to the phase synchronization circuit 8 is different, and negative feedback is likely to occur in the case shown in the rattan diagram (・). Assuming that the phase locked circuit $ operates to advance the phase of the read clock RCL, in the case shown in 4th wA (b), positive feedback is applied and the phase of the read clock ILCL operates to further lag the phase. . And I (Russ RP is sgo
' Due to the delay, the 1-bit counter 4.
1112) Output line connection 480(a), (Since the phase relationship is as shown in #, phase synchronization pull-in is performed.

As described above, in the conventional phase difference detection circuit, when clock disturbance occurs and the phase condition falls into a region where positive feedback is required, the time required for phase locking becomes longer. That is, there is a drawback that even if the phase difference is the same, the phase difference detection control may be different.

The present invention has been made to improve the above-mentioned drawbacks, and it is an object of the present invention to provide a phase difference detecting power that can always correspond to the phase differences of eight types of pulses. The disaster examples will be explained in detail below.

Figure S is a block diagram of an embodiment of the present invention. The phase difference detection circuit 6 has exclusive OR circuits 10, 11 and 7 circuits 7a and 7a, and exclusively outputs the output of the 1-bit counter 4.5. input to the OR circuit 10, and its exclusive OR circuit 1O
The OtH voltage is used as the data terminal of the 7x70x and one input of the exclusive OR circuit 11. A pulse WPXaRPt-clock is applied to the clock terminal C of the flip 70 tube U.

FIG. 6 is an explanatory diagram of the operation, and shows the pulses WP, RP! applied to the x-bit counters 4, s. Assuming that the outputs shown in FIG. 6 (a) and (b) are the same as those explained in FIGS. 3 and 4, their outputs are as shown in FIG. 6 (c),
It will be as shown in (d), (・), or (f). The flip-flop reads the input from the data terminal at the falling edge of the clock CL.If the clock CL' is set to clock CL', an exclusive or Regardless of whether the output of circuit 10 is @1" or @O", flip 70 knob 12 (DQ terminal is @0"
Or @11. Therefore, when the outputs of the 1-bit counters 4 and 5 are shown in FIGS. 6(a) and 6(d), the
At the falling edge of P, the output of the exclusive OR circuit 10 is @11.
Therefore, the mutual terminals of the three-piece float are 101. Output of exclusive OR circuit 10 and 7 lip 70 tube uo
The outputs of the mutual terminals are applied to the exclusive OR circuit 11, and the output of the exclusive OR circuit 10 is outputted from the exclusive OR circuit 11.

Also, the output of the 1-bit counter 4.5 is shown in Figure 6 (.).

In the case shown in (f), the output of the exclusive OR circuit 10 becomes "1" at the falling edge of the pulse wp, so the flip-flop 120Q terminal becomes "1". Therefore, the output of the exclusive OFF circuit 10 becomes "1". It is inverted and outputted by the exclusive OR circuit 11. That is, whether the output of the 1-bit counter 4.5 is as shown in FIG. 6(e), (d) or (6), (f), the phase difference is The output of the detection circuit 6 corresponds to the phase difference between the pulses WP and BP, as shown in FIG.

The above-mentioned embodiment deals with the case where, as the phase difference between the pulses WP and RP increases, the pulse width of the phase difference detection output pulse increases, thereby applying negative feedback to the phase locked circuit. On the other hand, if you want to reduce the pulse width of the phase difference detection output pulse and apply negative feedback, you can do this by inputting the Q terminal output of the flip-flop to the exclusive OR circuit 11. become. In addition, when used as the clock CL of the pulse RP t 7 lip flop 1, 7 lip flop 1
The relationship between the Q terminal 2 and the exclusive OR circuit 11 is as follows:
This is the opposite of the case described above.

FIG. 7 shows how the integral value of the phase difference signal changes when the phase difference between wp and RP shifts at a constant speed, which means the phase synchronization pull-in characteristic. The curve (-) in the same figure has a triangular wave shape, which is the characteristic of the conventional example. In other words, when controlling the phase difference with a PLL, negative feedback occurs in the characteristic range B of the upper right slope, and when phase synchronization is performed, positive feedback occurs in the characteristic range B of the upper left slope, leading to the next stable point. Therefore, the time required for phase synchronization may become longer.

If the embodiment of the present invention is applied to this, FIG.
) Since negative feedback is always applied, phase synchronization can be achieved at high speed.

As explained above, the present invention provides the first output of the output signals WP, RP, etc. from the write control counter 1 and the read control counter 3.
1! : Add the second pulse to the first and second 1-bit counters 4.5 and 4.5-
In the phase difference detection circuit that detects the phase difference between the first and second 1-bit counters 4.!I, the outputs of the first and second 1-bit counters 4.! An exclusive OR circuit W, a latch circuit such as a flip-flop U that holds the output of the exclusive OR circuit 10 at the falling edge of the first or eighth pulse, and The initial state of the first and second 1-bit counters 4.! Regardless of the above, a detection output proportional to the phase difference between the first and eighth pulses will be obtained.

Therefore, when applied to the control of the write clock and read clock in a buffer control system, the phase difference between the write pulse and the read pulse can be detected and phase synchronization can be carried out at high speed. It goes without saying that the present invention can be applied not only to detecting a phase difference for phase synchronization, but also to detecting a phase difference between two types of constant period pulses.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a Batza memory control circuit equipped with a phase difference detection circuit, Fig. 2 is a diagram explaining the operation of phase difference detection,
FIG. 3 is a block diagram of a conventional phase difference detection circuit, FIG. 4 is a diagram explaining the operation of the conventional phase difference detection, FIG. 5 is a block diagram of an embodiment of the present invention, and FIG. 6 is an explanation of its operation. 7 are explanatory diagrams of phase synchronization pull-in characteristics using a conventional example and a second embodiment of the present invention. 4.5 is a 1-bit counter, 6 is a phase difference detection circuit, 10
, 11 is an exclusive OR circuit, and the river is a clip 7a tube. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Hisa Okabe Tamamushi (3 others) Figure 2 Figure 3 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] The first and second pulses each having a constant period are added to the first and 801st bit counters, and the outputs of the first and second 1-bit counters are added to calculate the phase difference between the first and second pulses. In the phase difference detection circuit for detecting, a first exclusive OR circuit which adds the outputs of the first and second 1-bit counters; a latch circuit that latches with a constant tie voltage synchronized with the pulse of the latch circuit, and a second exclusive OR circuit that controls whether or not to invert and output the output of the tenth exclusive OR circuit according to the output of the latch circuit. A phase difference detection circuit having a t-% signal.