JPH03226047A - Composite exchange system - Google Patents

Abstract

PURPOSE:To process the line exchange and the packet exchange unitaly by placing a memory unit having plural storage spaces as a switch at a cross point and using the unit in common for sent isochronism data and packet data. CONSTITUTION:An isochronism data 2(C1) on an input port 100 is inputted to an identification separation circuit 10, where identification is implemented and the data is sent to an incoming line 110 as an isochronism data 4(C1). A channel switch 200 selects a prescribed memory unit 204 and the data is stored in a timing 121. Then a packet data 1(P11) on the input port 100 is stored in all memory units 201, 204, 207 connecting to the incoming line 110 as a packet data 3(P11). Thus, the memory units 201-209 are used in common for both the data being the isochronism data 4(C1) and the packet data 5(P11) at the identification separation circuit 10 from the composite data inputted to the input ports 100-102.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a composite switching method that combines line switching and packet switching necessary for the unified exchange processing of multimedia data such as voice, data, and video. %] When transmitting multimedia data such as audio, data, and video, it is desirable to be able to handle all of these data using the same communication system, but in reality, due to the differences in the characteristics and characteristics of the multimedia data, each It is common to use an exchange method that is appropriate to the characteristics and nature of the information.

For example, in a public network, a circuit-switched network is used for real-time data such as audio and video, and a packet-switched network is used for burst-based data such as computer data.

Another exchange system currently proposed that has lost its share in multimedia data exchange is the American A.N.
SI X, 3T, F being considered by the 9.5 committee
There are DD I-II. This FDDI-II is a ring network consisting of a double ring 301 as shown in FIG. 3(a) and a node 302 that connects a terminal 303 to the network, and the access method is based on a slotted ring method. As shown in FIG. 3(b), the time-division slot multiplexing format is used, and as shown in FIG.
4 Mbps), and by dynamically dividing and using the wideband channel 314 between circuit switching and packet switching, it is possible to achieve both circuit switching and packet switching. Here, the selection of whether to use the 16 wideband channels 314 as circuit switching or packet switching is determined by the programming template prepared corresponding to the wideband channel 314 of the cycle ladder 312 in the header section 311. This can be determined by setting the format.

[Problems to be Solved by the Invention] However, in the first conventional example, the multimedia data is exchanged using different exchange methods depending on the characteristics of the data, such as circuit switching and packet switching. Therefore, there is little flexibility in network configuration, and the burden of maintenance and management is large.

Also, in the second conventional example, the access method is based on a slotted ring method, so it is suitable for a ring type network as shown in FIG. 3(a), but the access method shown in FIG. As shown in FIG. 4(b), nodes 410 are arranged in a distributed manner and links 42 connect between the nodes 410.
In a lattice network or triangular network that is constructed by connecting zeros, it is necessary to distribute data in all directions, and a distribution method that sequentially transmits data in a fixed order, such as the ring network in Figure 3 (a), is necessary. The problem is that it cannot be applied.

[Means for Solving the Problems] According to the present invention, in order to exchange input ports and output ports, a matrix is constructed between the incoming and outgoing lines of the communication path switch, and a plurality of switches are installed at the intersections of the matrix. A memory unit having a storage space is installed, and this memory unit is commonly used for logically multiplexed and transmitted isochronous data and packet data to centrally process circuit switching and packet switching. By converting isochronous data into time-division multiplexed data, a composite switching system is obtained, which is characterized in that time-division switching and packet switching are processed in an integrated manner.

[Function] In addition to making it possible to centrally exchange and process multimedia data with different characteristics such as audio, data, and video, it also has a high degree of freedom in network configuration and is flexible for future expansion and changes. This makes it possible to take appropriate measures. Furthermore, by making it possible to use existing terminals without imposing any special burden on peripheral devices, it is possible to increase the generality of the network.

[Example〕 The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. 1st
According to the figure, embodiments of the invention include input ports 100-1.
02, an identification separation circuit 10 whose input is connected to the input port loo~1゜2, and an input line 110~1 which is a data input.
12, and timing 120 to 12, which are timing inputs.
2 is a communication path switch 20 connected to the identification and separation circuit 10;
0, the combining circuit 3o to which the output lines 130-132 of the communication path switch 200 are connected, the output ports 140-142 connected to the output of the combining circuit 30, the identification and separation circuit 1O, and the switching control unit 4o. the input information line 11, the output information line 31 connected to the exchange control section 40 and the synthesis circuit 3o, and the address & clock 41 supplied from the exchange control section 40 to the communication path switch 200.

Further, FIG. 2 is a block diagram showing the detailed configuration of the communication path switch 200.

The communication path switch 200 connects incoming lines 110 to 112 and outgoing line 1.
In order to perform an exchange between 30 and 132, incoming lines 110 to 1
12 and the output lines 130 to 132 constitute a matrix switch. Then, memory units 201 to 209 are connected between the incoming and outgoing lines at each intersection and have the intersection positions of the matrix as addresses; Address & clock 41 and timing 12 that provides write synchronization timing
It consists of 0 to 122.

To explain the memory units 201 to 209 in a little more detail, each of the memory units 201 to 209 has a plurality of storage spaces, and includes a write circuit that controls data writing to an arbitrary address location in this storage space, and a write circuit that controls data writing from an arbitrary address location. It consists of a read circuit that controls data read. This write circuit writes write data from input lines 110 to 112 into the storage space at timings 120 to 122 synchronized with the write data according to the write address from the address & clock 41. Further, the read circuit is activated by a read clock from the storage space specified by the read address from the address & clock 41, and is read from the output lines 130 to 41.
132 to read the data.

In FIG. 1, isochronous data 2 (C,) and packet data 1 (p++
), isochronous data 8 (C,) on output port 141
, packet data 7 (Pl, ) on output port 142
We will explain the case of outputting to . It is assumed that this correspondence between input ports and output ports is determined at the time of call setup, and is stored in the exchange control unit 40 as control information.

First, the isochronous data 2 (C,) on the input port 100 is input to the identification/separation circuit IO, where it is identified and if it is determined to be isochronous data, that fact is input to the input information 1
1 to notify the exchange control unit 40. Then, at the same time as updating the control information regarding the data, it is sent to the incoming line 110 as isochronous data 4 (C,). At this time, the identification and separation circuit 10 generates a timing 121 that synchronizes the input data with the clock of the exchange control system. Isochronous data 4 (CI) is the memory unit address and the memory unit in the memory unit that are determined by the correspondence of call connections stored as control information in the exchange control unit 40.
Address information is sent to channel switch 200 through address & clock 41. In the communication path switch 200, a predetermined memory unit 204 is selected, and the address within the memory unit is input to the write circuit of the memory unit 204, and the address in the memory unit is inputted to the memory address position specified by the write circuit. It is stored in the first memory address of the memory unit 204 at the timing 121. Next, packet data 1 (P+ +) on the input port 100 is processed in the same way as the isochronous data C1, but the difference is that it is necessary to separate the header of the packet data pH in the identification separation circuit 10. One thing is to notify this header to the exchange control unit 40 through the input information 11 and update the control information regarding this packet data.
l+) in all memory units 201.204.207 connected to the incoming line 110. The reason for this is that since isochronous data is fixed end-to-end, it only needs to be stored in one memory unit, whereas packet data is connected to the incoming line 110 because it searches for a free line and connects. This is because it is necessary to store the data in all memory units 201, 204, and 207 and make it readable for any outgoing line.

In this way, memory units 201-209 have input 1
Separation circuit 1 identifies and separates the composite data inputted to 00 to 102.
0, isochronous data 4 (C1) and packet data 5 (P,
, ) are commonly used for both data. The exchange function is performed by the memory switch 201 in the communication path switch 200.
209, and the switching control unit 40 determines the addresses and access order for the memory units 201 to 209 in the channel switch 200, according to the correspondence of call connections stored in the control information. The information is then sent to the communication path switch 200 through the address & clock 41.

Next, in the channel switch 200, the isochronous data C3 is first read out from the first memory address of the memory unit 204 to the outgoing line 131 according to the information, and the packet data pH is read out first, etc. according to the information. Temporal data CK is read out from any of the memory units 201 to 209 to the outgoing line 132, and then the memory unit 20
This is realized by reading from the fourth memory address of No. 4 to the output line 132.

Since the isochronous data 6 (CI) read onto the output line 131 as described above is the isochronous data 6 (C,) alone, the isochronous data 6 (C, ) The packet data 5 (P, , ) outputted from the output port 141 as composite data of only
Since it coexists with the isochronous data 6 (CK), the synthesis circuit 30 logically multiplexes the isochronous data 6 (C,) with the packet data 5 (P, ,) and outputs it as composite data. Output on port 142. At this time, the packet data 5 (P++) receives the header information managed by the control information of the exchange control unit 400 through the output information 31,
This header information and packet data 5 (P, .) are combined. Therefore, isochronous data 2 (C,) on input port 110 is output as isochronous data 8 (C,) on output port 141 by the circuit switching function according to the present invention, and packet data on input port 110 is output as isochronous data 8 (C,) on output port 141. 1 (Pz)
is output as packet data 7fpz) of the output port 142 by the packet switching function according to this embodiment. As shown in this embodiment, a switching system capable of processing line switching and packet switching in an integrated manner can be realized.

Next, FIGS. 5 and 6 are block diagrams showing the configuration of the second embodiment. The second embodiment is a case where the line data 2 of the first embodiment is time-division multiplexed.

Before explaining the operation of time division multiplexing, the time division multiplexed data 52 (C1, , C, 2
, C, 3, Cl4) and output port 1
The correspondence between 40 and 142 is determined at the time of call setup, and is stored as control information in the exchange control unit 40. In order to simplify the explanation of this embodiment, as shown in FIG. 4
) and the call connections of the output ports 140 to 142 are shown in the table below.

The exchange control unit 40 uses the input port 1 detected by the identification and separation circuit 10 for slot management of time division multiplexed data.
It receives the leading bit timing of the time division multiplexed data 52 on 00 to 102, initializes the input slot management counter that indicates the time division multiplexed data position, and puts it in a frame start state. Thereafter, the identification/separation circuit IO detects the start bit of each slot, and counts up the input slot management counter each time the timing is received. It is also possible to use the timing of the final bit of the slot data for this count-up timing. Based on the state of the manual slot management counter, the exchange control unit 40 selects the memory unit in the channel switch to which the slot data is to be input based on the correspondence of call connections for each slot and the contents of the input slot management counter. It generates an address and a memory address in the memory unit, and passes it through the address & clock 41 to the channel memory 2.
Send to 00. In addition, in the identification separation circuit 1O, timings 120 to 122 synchronized with the timing of the final bit and the tarok of the exchange control system are generated for each slot, and are used as write clocks for the memory units 201 to 209. Supplied to the control circuit. Here, it is also possible to use the timing of the start bit of slot data as the write timing. In the communication path switch 200, the slot data on the input lines 11O to 112 is stored in the memory location of the memory unit specified by the memory unit address generated by the exchange control section 40 and the memory address within the memory unit. This accumulated slot data is transferred to the memory unit 200 in the communication path switch 200 according to the memory unit address and the internal memory address generated by the exchange control unit 40 from the correspondence between the content of the output slot management counter and the call connection. 209 to the output springs 130 to 132, the time order of the slot data is changed, thereby realizing the functions of a time switch and a space switch at the same time. Melody 1 read out on the outgoing lines 130-132. Similar to the first embodiment, the packet data is logically multiplexed by a combining circuit 30 and output as composite data to output ports 140 to 142 according to the correspondence determined at the time of call setup. When the time division multiplexed data 52 and packet data 1 on the input port 100 are input to the identification/separation circuit IO, the identification/separation circuit IO sends the detection timing of the first bit of the data frame to the exchange control unit 40 and inputs the input slot management counter. Initializes to "°°0", displays the first slot data, and generates the memory unit 201 and the first memory address in the memory unit 201 as the storage address of the first slot data C11 from the correspondence between this data and the call connection. Based on the address, the communication path switch 200 stores the first slot data C11 in the first memory address position of the memory unit 201 at timing 120 synchronized with the last bit of the first slot.The first bit of the second slot data C12 Then, the input slot management counter is counted up and becomes "1", and from the correspondence between this data and the call connection, the first memory address of the memory unit 207 is generated as the storage address of the second slot data, and the first memory address of the memory unit 207 is generated as the storage address of the second slot data. 2 slot data C12 is stored in the first memory address location of memory unit 207.

The third and fourth slot data are stored in the same manner, and the third and fourth slot data are stored in the same manner.
Slot data CI3 is stored in the second memory address location of memory unit 201, and fourth slot data is stored in the first memory address location of memory unit 204. As for the packet data pH, it is stored at the fourth memory address location of the memory units 201.204.207 as in the first embodiment.

Next, the reading of the slot data stored in the memory units 201 to 209 starts with the output slot management counter initialized to "0" in the exchange control unit 40, and the content of the output slot management counter is "0" and the call connection is read. Based on the correspondence relationship, the memory unit address in the communication path switch 200 to be read to the first slot on the outgoing lines 130 to 132 and the memory address in the memory unit are read out to the second slot in the memory unit 201 for the outgoing line 130.
The memory address is generated as the first memory address of the memory unit 204 for the outgoing line 131, and the slot data C13 is read out as the first slot data in the outgoing line 130 in the communication path switch 200 according to the address information. and the slot data C is sent to the outgoing line 131.
14 is read out, and the output line 132 becomes empty data. next,
The output slot management counter of the exchange control unit 40 is “1”
Based on the correspondence between this data and the call connection, the memory unit 201 address for the outgoing line 130 is counted up as the memory unit address of the communication path switch 200.
A first memory address is generated, slot data C11 is read onto line 130 as second slot data, and output lines 131 and 132 become empty data. The third slot data can be considered in the same way, and slot data C1□ is read out to the outgoing line 132 as the third slot data, and the outgoing lines 130 and 131 become empty data. Furthermore, it goes without saying that the packet data pH is read out in the same manner as in the first embodiment.

As described above, the time division multiplexed data 56 and packet data 5 are read out to the outgoing lines 130 to 132, and are logically multiplexed by the synthesis circuit 30 as in the first embodiment and sent to the output ports 140 to 142 as composite data. Output. In this way, it is possible to realize a switching system that can centrally process time division switching and packet switching.

[Effects of the Invention] As described above, according to the present invention, 1) It becomes possible to centrally process circuit switching and packet switching, and multimedia data such as voice, data, and video can be networked using a single exchange. .

2) In addition, time-division exchange and packet exchange can also be processed centrally, further increasing the throughput of the network.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a communication path switch of the first embodiment, and FIG. ) is a diagram showing the topology of FDD I-II, FIG. 3(b) is a diagram showing the cycle format transferred on the FDDI-H network, and FIG. 4 is a diagram showing the cycle format transferred on the FDDI-H network. FIG. 5 is a diagram showing a network topology to which a composite switching system is applied in an example, and FIG.
FIG. 6 is a block diagram showing the configuration of the second embodiment. FIG. 6 is a block diagram showing the configuration of the communication path switch of the second embodiment. In the figure, 1, 3.5.7 is packet data, 2.4.
6.8 is isochronous data, 52.54.56.58 is time-divided isochronous data, 10 is an identification and separation circuit, 30 is a synthesis circuit, 40 is a switching control unit, and 200 is a communication path switch. , 201-209 indicate memory units.

Claims (2)

[Claims] (1) A means for separating and combining composite data that is logically multiplexed isochronous (real-time) data and packet data, and determining the correspondence between input ports and output ports at the time of call setup, and managing that correspondence. an input port into which composite data is input; an output port which outputs composite data; and an exchange means for performing exchange between the input port and the output port, the exchange means comprising a matrix for performing the exchange. has a memory unit having a plurality of storage spaces, the input composite data is separated into isochronous data and packet data by the separating means, and the isochronous data and packet data are separated according to the correspondence relationship of the call connection. The memory unit is commonly used as a data storage area for storage, and isochronous data and packet data are read out from the memory unit serving as the common storage area to the same outgoing line in accordance with the correspondence of call connections, and the A composite switching system characterized by processing circuit switching and packet switching in an integrated manner by combining the data and outputting the composite data to an output port as composite data. (2) Separate isochronous (real-time) data that is time-division multiplexed and composite data that is logically multiplexed packet data.
means for synthesizing, means for determining a correspondence relationship between input ports and output ports at the time of call setup and managing the correspondence relationship, and exchange means for exchanging between input ports and output ports; The means has a memory unit having a plurality of storage spaces of matrices for performing the exchange, and a management mechanism for managing temporal and spatial slot positions of time-division multiplexed isochronous data on the memory unit, The management mechanism realizes the functions of a time switch and a space switch, performs time division multiplexing by reading time division multiplexed data from the memory unit onto the same outgoing line, further reads packet data, and combines the data by the combining means. A composite exchange method characterized by processing time division exchange and packet exchange in a unified manner by outputting the data as composite data to an output port.