JPH0779247A - Cross connect device - Google Patents

Abstract

PURPOSE:To reduce a processing speed by making parallel extension large, and to easily adapt to a large capacity by operating a cross connect processing for each inside frame whose length is set as an optimal value to the length of each line time-division multiplexed and applied to an input port. CONSTITUTION:A function which divides the frame individually applied to input ports 121-12N into inside frames is load-distributed to transmitting circuits 111-11N, and a function which constitutes the frame to be transmitted output ports 151-15N from the inside frames is load-distributed to receiving circuits 141-14N. Therefore, the cross connect is operated for each inside frame whose length is set the optimal value to the length of each line which is time-division multiplexed and applied to the input ports 121-12N, so that the processing speed can be reduced by making parallel extension large. It is also possible to easily adapt to the large capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cross-connect device for performing line setting in a data transmission network in which a plurality of lines are synchronously multiplexed, each line being replaced or edited for each time slot.

[0002]

2. Description of the Related Art New synchronous multiple interface (SDH: S
ynchronous Digital Hierachy), 1.5Mb / s, 52Mb / s
A multi-rate line composed of a plurality of lines with different speeds such as s and 155 Mb / s is synchronously multiplexed and transmitted by time division.

In such a data transmission system, a cross-connect process is performed in which the multiplexed individual lines are replaced or edited on the time axis to perform switching or routing to set the lines.

FIG. 13 is a diagram showing a first configuration example of a conventional cross-connect device. In the figure, signals at a speed of 155 Mb / s are input to the input ports 132 ₁ and 132 ₂ of the cross-connect circuit 131, and the output ports 133 ₁ and 133 ₂ are subjected to cross-connect processing by this cross-connect device. The same speed signal is output. Output port 13 of cross-connect circuit 131
3 ₃ and 133 ₄ are connected to the input ports 135 ₁ and 135 ₂ of the cross connect circuit 134, respectively, and the output ports 136 ₁ and 136 ₂ of the cross connect circuit 134 are the input ports 132 ₃ and 1 of the cross connect circuit 131, respectively.
32 ₄ is connected. The output ports 136 ₃ and 136 ₄ of the cross connect circuit 134 are connected to the input ports 138 ₁ and 138 ₂ of the cross connect circuit 137, respectively.
Output ports 139 ₁ and 13 of the cross connect circuit 137
9 ₂ are connected to the input ports 132 ₃ and 132 ₄ of the cross connect circuit 134, respectively. The cross-connect circuits 131, 134, 137 are composed of general time switch circuits.

The cross-connect circuit 131 takes in the signal 141 of 155 Mb / s shown in FIG. 14 from the input ports 132 _{1 to} 132 ₄ and can directly perform cross-connect processing on the transmission rate unit of the signal.
Is subjected to the process sends to the output port 133 _1, 133 _2, for those that can not be subjected to such a process directly sends to the output port 133 _3, 133 _4.

[0006] cross-connect circuit 134 and 137 is connected to cross-connect 131 to the chain-like as described above, the signal 142 _{1 to 142 3} 3 52 Mb / s shown in FIGS 14, individually to the signal The same cross-connect processing as the cross-connect circuit 131 is performed on the 28 signals of 1.5 Mb / s included in.

Therefore, the output ports 133 ₁ and 133 ₂
Is obtained by cross-connecting the multi-rate lines input by being synchronously multiplexed to the input ports 132 ₁ and 132 ₂ . FIG. 15 is a diagram showing a second configuration example of a conventional cross-connect device.

In the figure, the multiplexing circuit 151 is 155M.
Input ports 152 ₁ to ₁ to which b / s signals are individually applied
52 ₄ has its output connected to an input of the isolation circuit 154 via a cross-connect circuit 153. Separation circuit 1
54 has an output port 155 ₁ to 155 _4.

In the cross connect circuit 153, the output of the multiplexing circuit 151 is connected to the data input of the memory 156, and the data output thereof is connected to the input of the separation circuit 154. The output of the read address counter 157 is connected to the read address input of the memory 156, and the output of the write address counter 158 is connected to the input of the read address counter and the write address input of the memory 156.

In the cross-connect device having such a structure, for example, when the serial / parallel expansion degree is 1 byte, the structure is the same as that of the time switch circuit generally used at a single speed, and the multiplexing circuit 151 has the input port 152 ₁ ~ 152
_With respect to the 155 Mb / s signal given by ₄ , serial-parallel expansion and multiplexing processing is performed for each of the 28 1.5 Mb / s signals described above. The write address counter 158 cyclically outputs a sequential address in synchronization with such processing, and the memory 156 sequentially stores the data obtained by the above processing in the storage area designated by the address.

Further, the memory 156 performs a read operation from the storage area corresponding to the address output by the read address counter 157, based on the content of the predetermined cross-connect processing, for the data thus accumulated. The demultiplexing circuit 154 takes in the data thus read, parallel-serially develops in synchronization with the read address 157, and further demultiplexes the output ports 155 ₁ ...
Output to 155 ₄ .

FIG. 16 is a diagram showing a third configuration example of a conventional cross-connect device. The difference between this configuration example and the conventional example shown in FIG. 15 is that a multiplexing circuit 162 having _three input ports 161 _{1 to} 161 3 is used instead of the multiplexing circuit 151.
And three output ports 16 instead of the separation circuit 154.
3 _{1-163 3} includes a separation circuit 164 having individually parallel conversion on the input port 161 ₁ to 161 ₃ circuit 16
5 ₁ 165 ₃ disposed further output ports 163 ₁ to
The parallel-serial conversion circuits 166 _{1 to} 166 ₃ are individually provided on 163 _3.
It is at the point where is placed.

[0013] In the cross-connect apparatus having such a construction, the serial-parallel conversion circuit 165 ₁ to 165 _3, a plurality of frames f ₁ ~f _n respectively on the input port 161 ₁ to 161 ₃
The transmission information (which is a unit of cross-connect processing) of each line arranged in the above is extracted, converted in parallel, and given to the multiplexing circuit 162. In addition, the parallel-serial conversion circuits 165 _{1 to} 165 ₃ are serial-parallel conversion circuits 166 ₁ to 165 _3.
166 ₃ to perform the opposite of the process.

That is, the lines distributed in a plurality of frames are developed in parallel and cross connected circuit 153
Therefore, in the cross-connect circuit, the operating speed of the internal circuit is kept low by setting the size per unit storage area of the memory (word length as a unit of the cross-connect process) large, as shown in FIG. The same cross-connect processing as in the conventional configuration is performed, and it is surely adapted to large capacity.

Further, in recent years, in order to uniformly and efficiently transmit various kinds of information having different communication speeds, communication times, characteristics of transmission information, etc., such information is multiplexed and transmitted in divided cell units asynchronously. Transfer mode (hereinafter "ATM (Asynch
ronous Transfer Mode). ) ”Is being adopted more often.

Conventionally, some input ports have different destinations A
In a data transmission system in which TM lines are provided in a multiplexed manner, and other input ports are provided with a synchronously multiplexed line (hereinafter referred to as "synchronous line"), a method of cross-connect processing is to use both The first method of separating the lines and performing cross-connect processing individually for each line type, and connecting the input / output ports with a slotted ring, and assigning the ATM (packet) line to any vacant slot The second method of accommodating and allocating the synchronous line fixedly to a specific slot and the third method of accommodating the synchronous line data in the ATM cell at the input port and performing the cross-connect process through a single ATM switch circuit There was a method.

[0017]

By the way, among the above-mentioned conventional cross-connect devices, the one shown in FIG.
For example, if it is necessary to perform cross-connect processing for every 1.5 Mb / s signal on all the frames provided to the input ports 132 ₁ and 132 ₂ , the cross-connect 1
31 and 134 do not need to perform cross-connect processing,
As the number of speed classes included in the multi-speed line increases, the redundancy of the link connecting the individual cross-connect circuits increases, the delay time in the link increases, and the circuit scale increases.

Further, in the conventional example shown in FIG. 15, since the cross-connect processing is performed for each line having the lowest speed, the speed of the processing performed in the device is increased, and the cross-connect processing especially for low-speed lines is performed. When the amount is large, the processing efficiency is lowered, and it has been difficult to increase the capacity while satisfying the requirement of real-time property.

Furthermore, in the conventional example shown in FIG. 16, in order to expand the parallelly expanded degree in the serial-parallel conversion circuit 165 ₁ to 165 ₃ are worn, the input port 161 ₁ to 161 ₃ and the output port 163 ₁ to 163 ₃ In this case, a plurality of frames must be temporarily stored, and the capacity of the memory to be installed in the entire device and the delay time of the cross connect process are large. In addition, for high-speed lines, the processing efficiency is lowered because they are once divided into small units and subjected to cross-connect processing.

Further, the processing amount of the cross-connect processing to be applied to each of the high speed line and the low speed line is generally unpredictable and cannot be arbitrarily set, so that the delay time is reduced, the circuit scale is reduced, and the size is increased. It has not been possible to satisfy all the adaptations to the capacity reduction in any of the above-mentioned conventional examples.

Furthermore, a synchronous line and A are given in a mixed manner.
In the above-mentioned first method of the cross-connect processing with respect to the TM line, although the cross-connect processing related to the ATM line is not always performed,
Hardware corresponding to such a line was installed in the device, and the circuit scale was large.

In the second method, the upper limit of capacity increase is determined by the speed of the ring, and a circuit for inserting and separating data into and from the high-speed ring is mounted at the input / output port. The circuit scale was large.

Further, in the third method, in order to accommodate the synchronous line in the ATM line on the input port side and to perform the opposite process on the output port side, a plurality of plural lines are processed in the same manner as in the conventional example shown in FIG. You have to store the frames temporarily,
The amount of memory to be installed in the entire device has increased. Also,
Regarding the synchronous line, in order to absorb variations in transfer time that occur when cross-connect processing is performed via the ATM switch circuit, it is necessary to add a cell loss monitoring circuit and other circuits. The transmission quality deteriorates due to the increase in cell loss.

An object of the present invention is to provide a cross-connect device capable of adapting to a large capacity and a mixture of ATM lines while reducing the circuit scale and delay time.

[0025]

The invention according to claim 1 takes in a multiplexed signal in which a plurality of lines are multiplexed from a plurality of input ports, and based on routing control information preset for these lines. In a cross-connect device that routes to a plurality of output ports, based on the configuration of multiple signals, a separating unit that separates the signals for each line, and a destination indicated by routing control information for each line separated by the separating unit. Each unit has an internal multiplexing unit that combines and multiplexes and outputs a corresponding frame individually to an output port, and an input unit that is individually arranged corresponding to an input port and an internal multiplexing unit that transmits the frame. Among the frames, an internal separation means for capturing a frame corresponding to a preset specific destination and separating the lines for each line, and an internal separation means. And a multiplexing unit that multiplexes the lines separated by the above to an output port corresponding to a specific destination with a preset configuration and sends the multiplexed line, and an output unit individually arranged corresponding to the output port. It is characterized by that.

According to a second aspect of the present invention, a multiplexed signal obtained by multiplexing a plurality of lines is fetched from a plurality of input ports,
In a cross-connect device that routes these lines to a plurality of output ports based on the destination information added to the transmission information, the separating unit that separates the signals for each line based on the configuration of the multiplex signal, and the separating unit Each separated line has an internal multiplexing means that combines and multiplexes for each destination indicated by the destination information, and sends out a frame individually corresponding to the output port, and is arranged corresponding to each input port. Input means, internal demultiplexing means for taking in a frame including preset specific destination information among the frames sent out by the internal multiplexing means, and demultiplexing for each line, and a line demultiplexed by the internal demultiplexing means To the output port corresponding to specific destination information in a preset configuration, and transmitting the multiplexed data. Characterized by comprising an output means disposed in correspondence with.

According to a third aspect of the present invention, in the cross-connect apparatus according to the second aspect, re-multiplexing means for multiplexing the frames sent from the input means corresponding to the individual input ports, and re-multiplexing. An ATM switch which takes in a plurality of frames multiplexed by means and performs routing based on the destination information included in each frame;
A plurality of frames routed by the M switch are separated for each destination indicated by the destination information, and a distribution unit that distributes to the output unit corresponding to the destination is provided.

According to a fourth aspect of the present invention, in the cross-connect device according to the first or second aspect, the frames individually sent from the input means corresponding to the individual input ports are fetched, and the routing control information is obtained. Alternatively, it is characterized by including a switch that faces each output means and performs routing based on the destination indicated by the destination information included in each frame.

According to a fifth aspect of the present invention, a multiplexed signal obtained by multiplexing a plurality of lines is fetched from a plurality of input ports,
For these lines, in a cross-connect device having a routing means for performing routing to a plurality of output ports indicated by preset routing control information, the paths that are individually vacant in the plurality of output ports are managed, An ATM line and a synchronous multiplex line, which are provided with an allocating means for allocating a vacant path of an output port corresponding to the destination in response to a request specifying a routing destination, and are multiplexed to the signal based on the structure of the multiplex signal The separating means for separating the synchronous line, the synchronous line relaying means for relaying to the routing means based on the routing control information, and the individual ATM lines separated by the separating means. Pass through the allocation means for the destination indicated in the cell of the line Asynchronous line relay means for receiving allocation and relaying to the routing means based on the routing control information corresponding to the path, and having input means individually arranged corresponding to the input ports. .

[0030]

In the cross-connect device according to the first aspect of the present invention, in the input means arranged corresponding to each input port, the separating means separates each line multiplexed into the multiplexed signal given to the corresponding input port. The output port corresponding to the destination is separated based on the structure of the signal, and the internal multiplexing means combines the separated lines for each destination indicated by the preset routing control information and further multiplexes. The frame corresponding to is constructed and output. On the other hand, in the output means arranged corresponding to such an output port individually, among the frames transmitted from the respective internal multiplexing means, the frame corresponding to the specific destination indicating the above-mentioned output port is The internal demultiplexing means takes in and demultiplexes for each line, and the multiplexing means multiplexes the demultiplexed lines in a preset configuration and outputs the multiplexed signal to its output port.

The above-mentioned frame is formed to have an optimum length according to the structure of the multiplexed signal given to each input port, and since cross-connect processing is performed for each frame, it is multiplexed into the same multiplexed signal. The parallel expansion degree can be set to a large value, and the processing speed can be reduced, as compared with the conventional example in which the minimum line of the lines is used as the processing unit of the cross-connect process.

In the cross-connect device according to the second aspect, the combination and multiplexing processing performed by the internal multiplexing means for each line separated by the separating means is the destination information added to the transmission information of each line. The cross-connect device differs from the cross-connect device according to claim 1 in that the process is performed for each destination.

Therefore, in the present invention, similarly to the cross-connecting apparatus according to the first aspect, the parallel expansion degree can be set to a value larger than that of the conventional example, and the processing speed is reduced. The cross-connect device according to claim 3, wherein the ATM
In the switch, the frames sent from the input means corresponding to the individual input ports are multiplexed and given by the re-multiplexing means, and the routing is performed based on the destination information individually included in these frames. Furthermore, the distribution means
In this way, the individual frames which have been routed while being multiplexed are separated for each destination based on the destination information of the frame, and distributed to the output means corresponding to the destination.

That is, in the cross-connect processing between the input and output ports, the routing processing for each frame of the same destination between the input means and the output means, which is particularly required to have high speed, is centrally performed by the ATM switch, The flow of the frame is unified and formed in a pipeline in the ATM switch, and the frame length can be set larger than that of the cross-connect device according to the second aspect, and the speedup can be surely supported.

According to a fourth aspect of the present invention, in the cross-connect device according to the first aspect or the second aspect, the routing process is performed for each frame of the same destination between the input means and the output means of the cross-connect device. This is performed by a switch having a plurality of ports individually corresponding to the input means and the output means.

Therefore, the operation speed is higher than that of the cross-connect device according to claims 1 and 2 in which the above-described frame flow is distributed into a plurality of frames via such a switch, and the frame flow is single. It is possible to increase the upper limit of.

According to the fifth aspect of the present invention, in the cross-connect device according to the fifth aspect, the demultiplexing means mixes and multiplexes the signals based on the structure of the multiplexed signals given to the corresponding input ports.
The TM line and the synchronous multiplex line are separated, and the synchronous multiplex line is relayed to the routing means via the synchronous line relay means. The asynchronous line relay means specifies the destination indicated in the cell of the line for the ATM line separated in this way, receives the allocation of the vacant path on the output port from the allocation means, and the routing control information corresponding to the path. Relaying to the routing means based on. The routing means takes in the synchronous multiplex line and the ATM line thus relayed, and performs routing to a plurality of output ports indicated by the preset routing control information.

Therefore, the cross-connect processing is integrated and reliably performed for the synchronous line and the ATM line that are mixed and multiplexed.

[0039]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment corresponding to the invention described in claim 1.

In the figure, the transmission circuits 11 _{1 to} 11 _N are
Each has an input port 12 _{1 to} 12 _N and an internal bus 1
3 to the receiving circuits 14 _{1 to} 14 _N. The receiving circuits 14 _{1 to} 14 _N have output ports 15 ₁ to ₁ respectively.
_Has 5 _N.

In the transmission circuit 11 ₁ , the input port 12 ₁ is connected to the input of the separation circuit 16 ₁ , and its first to fourth outputs are connected to the inputs of the memories 17 _{11 to} 17 ₁₄ , respectively. The output of the memory 17 _{11-17 14} is connected to the first to fourth input of the internal multiplexing circuit 18 _1, respectively, the output of which is connected to the internal bus 13. The control input of the separation circuit 16 ₁ is connected to the output of the separation control circuit 19 ₁ , and the control input of the internal multiplexing circuit 18 ₁ is connected to the output of the internal multiplexing control circuit 20 ₁ . Since the configurations of the transmission circuits 11 _{2 to} 11 _N are the same as the configurations of the transmission circuit 11 ₁ , the corresponding constituent elements of these transmission circuits are “ ₂ ” to “” as the first subscripts, respectively. _The same reference number with " _N " added is given, and the description thereof is omitted here.

In the receiving circuit 14 ₁ , the internal separation circuit 21 ₁
The internal bus 13 is connected to the input of the
First to fourth output of each memory 22 of _{1 11-22 14}
Connected to the input of. The outputs of the memories 22 _{11 to} 22 ₁₄ are respectively connected to the first to fourth inputs of the multiplexing circuit 23 ₁ , and the outputs thereof are connected to the output port 15 ₁ . The output of the internal separation control circuit 24 ₁ is connected to the control input of the internal separation circuit 21 ₁ , and the output of the multiplexing control circuit 25 ₁ is connected to the control input of the multiplexing circuit 23 ₁ . The receiving circuit 1
Regarding the configurations of 4 _{2 to} 14 _N , all of them are the receiving circuit 14 ₁
Therefore, the corresponding constituent elements of these receiving circuits have the first subscript " ₂ " to " _N " respectively.
The same reference number with "" is given, and the description thereof is omitted here.

Regarding the correspondence relationship between this embodiment and the constituent elements described in claim 1, the separation circuit 16 _k (k is “1”)
To any value of “N”, and the same applies hereinafter. ), Memories 17 _{k1 to} 17 _k4 and separation control circuit 19
_k corresponds to the demultiplexing means, the internal multiplexing circuit 18 _k and the internal multiplexing control circuit 20 _k correspond to the internal multiplexing means, the transmission circuit 11 _k corresponds to the input means, and the internal demultiplexing circuit 21 _k ,
The memories 22 _{k1 to} 22 _k4 and the internal separation control circuit 24 _k correspond to the internal separation means, the multiplexing circuit 23 _k and the multiplexing control circuit 25 _k correspond to the multiplexing means, and the reception circuit 14 _k.
Corresponds to the output means.

FIG. 2 is a diagram for explaining the operation of this embodiment. The operation of this embodiment will be described below with reference to FIGS. In the transmitting circuit 11 ₁ , the time division multiplexed signal having the frame structure shown in FIG. 2A is input to the input port 12 ₁ . The separation control circuit 19 ₁ includes the memories 17 _{1 to} 17 ₄
Control information indicating in advance which one of these memories should store the transmission information of the line (FIG. 2) formed for each field based on the above-mentioned frame structure. The separation circuit 16 ₁ separates the transmission information of each line given from the input port 12 ₁ for each line under the control of the separation control circuit 19 ₁ and stores it in the memories 17 _{1 to} 17 ₄ . Therefore, the memory 17 ₁ stores the line information shown in FIG. 2, the memory 17 ₂ stores the line information shown in FIG. 2, and the memory 17 ₃ stores the line information shown in FIG. The memory 17 ₄ stores the line information shown in FIG.

The internal multiplex control circuit 20 ₁ uses the internal bus 13
Frames sent and received via the Internet (hereinafter referred to as "internal frame")
Say. ) Has the identification information of the receiving circuits 14 _{1 to} 14 _N as the destination, and the control information indicating the type of the line to be accommodated and the arrangement on the time axis in advance. The internal multiplexing circuit 18 ₁ reads the transmission information stored in the memories 17 _{1 to} 17 ₄ under the control of the internal multiplexing control circuit 20 ₁ as shown by the dotted arrow in FIG. (b)) is formed and sent to the internal bus 13.

In the transmission circuits 11 _{2 to} 11 _N , the time division multiplexed signals input from the input ports 12 _{2 to} 12 _N are fetched under the control of the demultiplexing control circuits 19 _{2 to} 19 _N , respectively, and internal multiplexing control is performed. Similarly, an internal frame is sent to the internal bus 13 under the control of the circuits 20 _{2 to} 20 _N.

Of the receiving circuits 14 _{1 to} 14 _N , the transmitting circuit 1
1 In ₁ becomes the destination of the internal frame sent to the internal bus 13 from the receiving circuit (here, a reception circuit for simplicity 14 ₁
Only ), The internal separation control circuit 24 ₁ determines the timing at which an internal frame should be received from the internal bus 13 (identification information of the transmission circuit of the transmission source), the type of line accommodated in the internal frame, the arrangement on the time axis, and the like. Has control information indicating Under the control of the internal separation control circuit 24 ₁ , the internal demultiplexing circuit 21 ₁ takes in an internal frame given via the internal bus 13 and separates transmission information of a plurality of lines multiplexed into the frame for each line. Then, it is stored in the memories 22 _{11 to} 22 ₁₄ corresponding to each line.

The multiplexing control circuit 25 ₁ has the output port 15
Based on the structure of the frame to be sent to ₁ , the control information indicating the arrangement on the time axis of each line to be multiplexed in the frame is included. Under the control of the multiplexing control circuit 25 ₁ , the multiplexing circuit 23 ₁ reads the internal frames stored in the memories 22 _{11 to} 22 ₁₄ to form a frame, as indicated by the thin arrow in FIG. It is sent to the output port 15 ₁ .

That is, the function of dividing the frames individually given to the input ports 12 _{1 to} 12 _N into the internal frames is distributed to the transmitting circuits 11 _{1 to} 11 _N ,
The functions of forming the frames to be sent to the output ports 15 ₁ to 15 _N from the above-described internal frames are distributed to the receiving circuits 14 _{1 to} 14 _N , respectively.

As described above, according to the present embodiment, the cross-connect is made for each internal frame having a length set to an optimum value for the length of each line provided by time division multiplexing to the input ports 12 _{1 to} 12 _N. Since the processing is performed, the parallel expansion degree can be set to a large value and the processing speed can be reduced compared to the conventional example in which the minimum line of the lines given by multiplexing must be used as the processing unit. Moreover, it becomes possible to easily adapt to the increase in capacity. Further, in the present embodiment, as compared with the conventional example shown in FIG. 16, the serial-parallel conversion circuits 165 _{1 to} 165 ₃
Since the parallel expansion degree is expanded without adding the parallel-serial conversion circuits 166 _{1 to} 166 ₃ , the circuit scale and the delay time are reduced. Further, in this embodiment, the transmission circuit 11 ₁
.About.11 _N and receiving circuits 14 _{1 to} 14 _N , the cross-connect device is configured by arranging a plurality of modules having the same configuration. Therefore, the configuration is standardized and expansion is facilitated.

In this embodiment, the transmission circuits 11 ₁ to ₁ 1
1 _N accommodates a single input port, and the receiving circuits 14 ₁ to 1
Although 4 _N accommodates a single output port, the present invention is not limited to such a configuration and may accommodate a plurality of input ports and output ports, respectively.

[0052] Further, in this embodiment, all the lines given by multiplexing the input port 12 ₁ is being cross-connect process is routed to the output port 15 _1, in the present invention, when such Input port 12 without limitation
_{The same} can be applied to any cross-connect processing between ₁ to 12 _N and the output ports 151 to 15 _N.

Further, in the present embodiment, the transmission circuits 11 ₁ ...
11 each provided with an internal multiplexing control circuit 20 ₁ to 20 _N to _N, but each of the receiving circuits 14 ₁ to 14 _N internal isolation control circuit 24 ₁ to 24 _N are provided, in the present invention, such However, the internal multiplex control circuit and the internal demultiplexing control circuit may be integrated.

Further, in the present embodiment, all the transmission circuits and the reception circuits are linked via the internal bus 13. However, the present invention is not limited to such a method. Instead of 13, a ring-shaped internal bus may be used, or all transmission circuits and reception circuits may be connected via mesh-shaped links.

FIG. 3 is a diagram showing an embodiment corresponding to the invention described in claims 2 and 3. A difference between this embodiment and the embodiment shown in FIG. 1 is that transmission circuits 31 _{1 to} 31 ₃ are provided in place of the transmission circuits 11 _{1 to} 11 _N and reception circuits 32 ₁ are provided in place of the reception circuits 14 _{1 to} 14 _N. ˜32 ₃ and the transmission circuit 31 ₁ ˜
An internal bus 1 is provided between 31 ₃ and the receiving circuits 32 _{1 to} 32 _3.
In place of 3, the multiplex circuit 33, the common buffer type switch 34 and the separation circuit 35 which are connected in cascade are provided.

In the common buffer type switch 34, the output of the multiplexing circuit 33 is connected to the data input of the first-in / first-out common memory 36 and one input of the distribution circuit 37, and the data output of the common memory 36 is separated. Connected to the input of circuit 35. The first to third outputs of the distribution circuit 37 are used for address selection through the first-in / first-out type address memories 38 _{1 to} 38 ₃ provided respectively corresponding to the output ports 15 ₁ to 15 _N. Connected to the first and third inputs of circuit 39. The output of the address selection circuit 39 is connected to the read address input of the common memory. The output of the write address generation circuit 40 is connected to the write address input of the common memory 36 and the other input of the distribution circuit 37.

The transmission circuits 31 _{1 to} 31 _{3 have} the same configuration as that of the transmission circuits 31 _{1 to 3 13} except that the internal multiplexing control circuits 20 _{1 to} 20 _N are replaced by internal multiplexing control circuits (not shown) to which the functions described below are added. It has the same configuration as the circuits 11 _{1 to} 11 _N.

[0058] The reception circuit _{321 to} 323 configuration, except with an internal separation control circuit functions described below instead of the internal isolation control circuit 24 ₁ to 24 _N is added (not shown.), Received The configuration is the same as that of the circuits 14 _{1 to} 14 _N.

Regarding the correspondence relationship between the present embodiment and the invention described in claims 2 and 3, the transmission circuit 11 _k corresponds to the input means, the reception circuit 14 _k corresponds to the output means, and the multiplexing circuit. 33 corresponds to the re-multiplexing means, the common buffer type switch 34 corresponds to the ATM switch, and the separation circuit 35 corresponds to the distributing means.

The operation of this embodiment will be described below. The transmission circuits 31 _{1 to} 31 ₃ take in the time division multiplexed signals given to the input ports 12 _{1 to} 12 ₃ and separate them into internal frames as in the embodiment shown in FIG. As shown in FIG. 4, a header for identifying the output port of the destination, the frame, and the type of the frame is added to the head by the internal multiplexing control circuit provided in each of the transmission circuits 31 _{1 to} 31 ₃ .

The multiplexing circuit 33 multiplexes the internal frame having such a structure by a predetermined method and outputs it. In the common memory 36, the contents of the internal frame thus multiplexed in the storage area indicated by the write address sequentially output from the write address generation circuit 40 (see FIG. 4).
~) Is stored.

[0062] Distribution circuit 37 takes the write address as described above for each of the inner frame, in the address memory 38 _{1-38 3} is written into the address memory corresponding to the destination output port indicated in the header as described above.

The address selection circuit 39 reads out the addresses thus written in the address memories 38 _{1 to} 38 ₃ in a predetermined fixed order. Common memory 36
Reads from the storage area corresponding to the address thus read out, the contents of the internal frame stored in that area (any one of FIG. 4). The separation circuit 35 is
The contents of the internal frame read in this way are fetched and separated in a fixed order corresponding to the order of the addresses output from the address selection circuit 39.

[0064] The reception circuit _{321 to} 323 captures the contents of the inner frame provided to separate as this will be transmitted by multiplexing in the same manner as in the embodiment shown in FIG. 1, the processing of the multiplexing, Under the control of the internal separation control circuit provided in each of the receiving circuits 32 _{1 to} 32 ₃ , it is performed based on the contents of the above-mentioned header, instead of the position on the time axis which is predetermined for each internal frame.

As described above, according to this embodiment, the parts involved in high-speed processing are concentrated in the common buffer type switch 34, and the flow of internal frames is unified through the common memory 36. Since the flow of the internal frame is formed in a pipeline shape, the synchronous control between the transmission circuits 31 _{1 to} 31 ₃ and the reception circuits 32 _{1 to} 32 ₃ is reliably performed, and
Compared with the embodiment shown in (1), the length of the internal frame can be set to be large and the speed can be easily increased. Furthermore, in this embodiment,
Regarding the internal frame, when the configuration of the line to be accommodated is changed, the internal separation control circuits 24 _{1 to} 24 ₃ and the separation circuit 35 included in the reception circuits 32 _{1 to} 32 ₃ ,
By adding a processing procedure corresponding to the content of the header after the modification or providing in advance and appropriately modifying the content of the header described above, it is possible to quickly and easily adapt without changing the basic hardware configuration. It is possible to In addition, as an actual method for performing such smooth correspondence, a method of previously securing an extra header length is generally used.

Further, in the present embodiment, the transmission circuits 31 _{1 to} 3 ₁
By switching and setting the header in accordance with a predetermined algorithm in 1 ₃ , it is possible to efficiently switch the routing due to a failure of the transmission path or the like.

In this embodiment, the input ports 12 ₁ ...
12 ₃ synchronously multiplexed multiple lines (eg SDH
I explained only when the line) is given,
In the present embodiment, when ATM cells are provided in a mixed manner, the common buffer type switch 34 can be shared by matching the structure of the ATM cells with the structure of the internal frame.

As a method of accommodating such an ATM line, a method of separating the synchronously multiplexed lines in the transmission circuits 31 _{1 to} 31 _{3 from the} ATM line and accumulating them, and a common buffer type switch 34 Either a storage area corresponding to the line may be provided separately, or a method of preferentially using the ATM line for cross-connect processing may be adopted. Further, in this embodiment, although separate memory device in the address memory 38 _{1-38 3} is used, the present invention is not limited to such a configuration, for example, these address memory of a single memory May be integrated and configured.

Further, in this embodiment, the primary cross-connect process at the level of the internal frame is performed via the common buffer type switch 34, but the present invention is not limited to such a configuration, and, for example, Instead of the common buffer type switch 34, an output buffer type ATM switch circuit or other non-blocking switch may be used.

FIG. 5 corresponds to the invention described in claim 4.
It is a figure which shows an Example. In the figure, the input port 51₁₁
~ 51₁₃Circuit 52 having₁First and second out
The power is the intermediate switch circuit 53₁The first and second
Connected to the inputs of the
Receiving circuit 54₁Connected to the first and second inputs of
It Receiving circuit 54₁Is the output port 55₁₁~ 55₁₃Have
To do. Input port 51_{twenty one}~ 51_{twenty three}Circuit 52 having
₂The first and second outputs of each are intermediate switch circuits
53₁Connected to the third and fourth inputs of the
And the fourth output are respectively the receiving circuit 54₂The first and
Connected to the second input. Receiving circuit 54₂Is the output port
To 55_{twenty one}~ 55_{twenty three}Have. Input port 51₃₁~ 51 ₃₃
Circuit 52 having₃The first and second outputs of
Intermediate switch circuit 53₁To the fifth and sixth inputs of
Connected and its 5th and 6th outputs are received times
Road 54₃Connected to the first and second inputs of. Receiving times
Road 54₃Is the output port 55_{twenty one}~ 55_{twenty three}Have. Send
Circuit 52₁The third and fourth outputs of
Circuit 53₂Connected to the first and second inputs of
The first and second outputs of the₁The first
Connected to the third and fourth inputs. Transmission circuit 52₂The first
The third and fourth outputs are respectively the intermediate switch circuit 53.₂
Connected to the third and fourth inputs of the
The four outputs are the receiving circuit 54, respectively.₂The third and fourth
Connected to input. Transmission circuit 52₃The third and fourth
The output is the intermediate switch circuit 53, respectively.₂The fifth and the
Connected to the six inputs and its fifth and sixth outputs
Each receiving circuit 54₃Connected to the third and fourth inputs of
It

[0071] Further, the configuration of the transmitting circuit 52 ₁ to 52 _3, each of the plurality of input ports 51 _{11-51 13,} 51
Intermediate switch circuits 53 ₁ and 53 ₂ are provided via low-speed internal links (for example, optical fiber links) 56 ₁ which have _{21 to} 51 ₂₃ and 51 _{31 to} 51 ₃₃ and each of which outputs replace the high speed internal bus 13. 3 is different from the transmission circuits 31 _{1 to} 31 _N shown in FIG. Further, regarding the configurations of the receiving circuits 54 _{1 to} 54 _3, a plurality of output ports 55 _{11 to} 55 are provided, respectively.
_A low speed internal link 5 having ₁₃ , 55 _{21 to} 55 ₂₃ , 55 _{31 to} 55 ₃₃ and whose input replaces the high speed internal bus 13.
6 ₂ a point connected to the output of the intermediate switch circuits 53 _1, 53 ₂ via, differs from the receiver circuit _{321 to} 323 shown in FIG. 3, other basic configuration of the same.

[0072] As to the correspondence relationship between the present embodiment and the invention of claim 4, the transmitting circuit 52 ₁ to 52 ₃ in response to the input means, the internal switch circuit 53 _1, 53 ₂ corresponds to switch , The receiving circuits 54 _{1 to} 54 ₃ correspond to the output means.

The operation of this embodiment will be described below. Transmitting circuit 52 ₁ to 52 ₃ takes a division multiplexed signal when applied to the input port 51 _{11-51 33,} in the same manner as in the embodiment shown in FIG. 3, the destination of the output ports, the frame and the type of the frame It is separated into internal frames to which a header for identification is added.

The intermediate switch circuits 53 ₁ and 53 ₂ take in such internal frames via the internal links 56 ₁ and, for each internal frame, the receiving circuit (destination circuit having the output port of the destination indicated by the header of the frame). The receiving circuit 54 _{1 to} 54 ₃ is routed via the internal link 56 ₂ .

By the way, the intermediate switch circuits 53 _{1 to} 53
Regarding the configuration of ₂ , the above-described space switch circuit that operates in units of internal frames may be used, or a common buffer type switch having the same configuration as the common buffer type switch 34 shown in FIG. 3 may be used. Is the transmission circuit 52
_{1-52 3} has to sent the inner frame at a predetermined timing synchronized with the operation of the space switch, in the latter case the contrary, the adjustment of such timing is not required.

[0076] receiving circuit 54 ₁ to 54 _3, thus accepts the internal frame provided via an intermediate switching circuits 53 ₁ to 53 _2, in the same manner as in the embodiment shown in FIG. 3,
It is multiplexed based on the contents of the header of each internal frame and output to the output port of the destination.

As described above, in this embodiment, the plurality of intermediate switch circuits 5 having a small circuit scale and a low operation speed are used.
The flow of the internal frame is distributed to 3 ₁ and 53 ₂ (a plurality of paths formed by the internal links 56 ₁ and 56 ₂ ). Therefore, in the embodiment shown in FIGS. 1 and 3, a single internal bus 13 and a common buffer type switch 34 are used.
Since the flow of the internal frame is concentrated in the, the operation speed, which was limited, can be increased. Further, the length of the internal frame transmitted via the internal links 56 ₁ and 56 ₂ can be set to a large value as in the embodiment shown in FIGS. 1 and 3, and the parallel expansion degree can be increased. Since the value is set to a large value, it is possible to realize a cross-connect device having a larger capacity than those of these embodiments.

[0078] In the present embodiment, the input port 55 ₁₁ -
Although the case where a plurality of synchronously multiplexed lines are given to 55 ₃₃ has been described, in the present embodiment, for ATM cells that are given in a mixed manner, the structure of the internal frame must match the structure of the ATM cells. Can be accommodated by.

FIG. 6 is a diagram showing an embodiment corresponding to the invention described in claim 5. In FIG. The difference between this embodiment and the embodiment shown in FIG. 5 is that the transmission circuits 62 _{1 to} 62 ₃ each having a single input port 61 _{1 to} 61 ₃ are replaced with the transmission circuits 52 _{1 to} 5 3.
2 ₃ and a space switch 63 instead of the intermediate switches 53 ₁ and 53 ₂ and a single output port 64 _{1 to} 6
The receiving circuits 65 _{1 to} 65 ₃ respectively having 4 ₃ are provided in place of the receiving circuits 54 _{1 to} 54 ₃ , and the transmitting circuits 62 _{1 to} 62 ₃ are provided.
The corresponding input / output of the contention control unit 66 is connected to the control input / output.

Transmission circuit 62₁Then, the input port 61₁But
Demultiplexing circuit 67₁Connected to the input of one of the outputs
Is memory 68₁₁Connected to the data input of. Memory 68
₁₁The data output of the selection circuit 69₁Connected to one input
And its output is connected to the first input of the space switch 63.
Be done. Demultiplexing circuit 67₁The other output of the memory 68 ₁₂
Of the selection circuit 6 connected to the data input of
9₁Connected to the other input of. Memory 68₁₁Control input
Input control circuit 70 for force₁₁The output of is connected to the memory 6
8₁₂The input control circuit 70₁₂Output of is connected
Be done. Input control circuit 70₁₂I / O for control of
The corresponding control input / output of the control unit 66 is connected. In addition,
Transmission circuit 62₂, 62₃For the configuration of
Road 62₁Since the configuration is the same,
As a first subscript to the component ₂","₃Was added
The same reference numerals are given and the description thereof is omitted here.

Receiver circuit 65₁Then, of the space switch 63
The corresponding output is the separation circuit 71.₁Connected to the input of
Output is memory 72₁Connected to the data input of. memory
72 ₁The output of the output control circuit 73₁Output is connected
Memory 72₁Output port 64 for data input₁
Are connected. The receiving circuit 65₂, 65₃In the configuration of
As for both, the receiving circuit 65₁Is the same as the configuration of
As the first subscript to each corresponding component
"₂","₃The same reference number
Will not be described.

FIG. 7 is a diagram showing the configuration of the competition control unit. In the figure, the first to third inputs / outputs of the multiplexing circuit 80 are connected to the control inputs / outputs of the input controllers 70 ₁₂ , 70 ₂₂ , 70 ₃₂ , respectively. The bus terminal of the multiplexing circuit 80 is connected to the common bus 81, and the output port 64 is provided on the bus.
Contention control circuits 82 _{1 to} 82 individually corresponding to ₁ to 64 _3
3 is placed. The output of the clock circuit 83 is input to the clock bus 84 of the competition control circuits 82 _{1 to} 82 _3.
Connected via.

In the competition control circuit 82 ₁ , the common bus 81 is connected to the input of the judgment circuit 85 _{1 and} the output of the return circuit 86 ₁ , and the output of the judgment circuit 85 ₁ is connected to one count input of the counter 87 ₁ . The output of the counter 87 ₁ is connected to the address input of the conversion memory 88 ₁ , and its data output is connected to the input of the return circuit 86 ₁ and _one input of the comparison circuit 89 ₁ . The clock bus 84 is the comparison circuit 8
9 ₁ is connected to the other input of which the output is a counter 87.
Connected to the other count input of ₁ . Since the configurations of the competition control circuits 82 ₂ and 82 ₃ are the same as the configurations of the competition control circuit 82 ₁ , the same components are provided with the suffix numbers “ ₂ ” and “ ₃ ”. A reference number is given and its description is omitted here.

Regarding the correspondence relationship between this embodiment and the invention described in claim 5, the space switch 63 and the receiving circuit 65 _K correspond to the routing means, and the competition control unit 66.
Corresponds to the allocating means, the demultiplexing circuit 67 _k corresponds to the separating means, the memory 68 _k1 , the input control circuit 70 _k1 and the selecting circuit 69 _k correspond to the synchronous line relaying means, and the memory 6
8 _k2 , the input control means 70 _K2 and the selection circuit 69 _k correspond to the asynchronous line relay means.

The operation of this embodiment will be described below. In addition,
Transmitting circuit 62 ₁ to 62 _3, the reception circuit 65 ₁ to 65 ₃ and competition control circuit 82 ₁ to 82 _3, subscript each number _"1" is assigned circuit number _"2" appended to the same reference numerals, " Performs the same operation as the circuit marked with " ₃ ". Therefore, for the sake of simplicity, the operation will be described below only for the circuits to which the subscript “ ₁ ” is attached, unless a plurality of or specific circuits need to be shown.

In the transmission circuit 62 ₁ , the demultiplexing circuit 67 ₁
Sequentially takes in the frames supplied to the input port 61 ₁ and separates the individual SDH lines and ATM lines (cells) multiplexed on the frames. Further, the demultiplexing circuit 67 ₁ recyclically writes the transmission information of the SDH line thus separated into a predetermined storage area of the memory 68 ₁₁ in synchronization with the internal frame, and the transmission information of the ATM line. Similarly, the data is written in the memory 68 ₁₂ .

The input control circuit 70 ₁₁ has a space switch 63.
Of the time slots on the internal frame (hereinafter referred to as “internal slot”) that is the unit of switching performed by
Internal slot pre-allocated for SDH line (Fig. 8
), The contents of the memory 68 ₁₁ (transmission information of the SDH line) are sequentially read.

On the other hand, the input control circuit 70 ₁₂ has the memory 68.
_The information (transmission information (cell) of the ATM line) newly written in ₁₂ is sequentially read, the destination information indicating the destination is extracted from the information, and further multiplexed and sent to the competition control unit 66.

In the competition control unit 66, the demultiplexing circuit 80
Captures and separates the destination information given by multiplexing in this way, and the contention control circuit 8 via the common bus 81.
Sequentially sent to 2 _{1-82 3.}

In the competition control circuit 82 ₁ , the determination circuit 85 ₁
Is preset with a unique output port number indicating the output port 64 _1. The output port number and the above-mentioned destination information are sequentially compared with each other, and a pulse is transmitted when the two match. The counter 87 ₁ increments the count value by a predetermined value (= 1) in response to such a pulse. Therefore, such a count value (hereinafter referred to as “relative slot number”) indicates the number of empty internal slots (FIG. 8) that can be assigned to the ATM line with the head of the internal frame as a reference. The conversion memory 88 ₁ has a number (= 0, 2, .. (hereinafter referred to as "absolute slot number") are stored in advance. Such a conversion memory 88 ₁ converts the relative slot number into an absolute slot number by performing a read operation using the relative slot number given from the counter 87 ₁ as an address.

The comparing circuit 89 ₁ compares the absolute slot number given in this way with the number of the internal slots in the time series order given from the clock circuit 89 via the clock bus 84, and if they match. The count value of the counter 87 ₁ is increased by a predetermined value (= 1). Therefore, the counter 87 ₁ counts the number of ATM cells to be sent to the corresponding output port for each internal frame,
The return circuit 86 ₁ takes in the absolute slot number output from the conversion memory 88 ₁ in accordance with such a count value, and sends it to the input control units 70 ₁₂ to 70 ₃₂ via the common bus 81 and the multiplexing circuit 80. To do.

The input control circuit 70 ₁₂ sequentially takes in such absolute slot numbers, and from the memory 68 ₁₂ to the AT at the timing on the internal frame corresponding to the slot numbers.
Read the transmission information of the M line.

The selection circuit 69 ₁ is an SDH line or an AT.
The contents of the memories 68 ₁₁ and 68 ₁₂ are selected in chronological order in accordance with a predetermined allocation of internal slots to the M lines, and time-division multiplexed as shown in FIG. As shown in FIG. 9, in the internal slots S _A1 , S _A2 , ... Which can be allocated to the ATM line, the contents of the cell are arranged in a field other than the header provided at the beginning and are allocated to the SDH line. Slot S _S1 ,
In S _S2 , ..., A plurality of lines are multiplexed and accommodated after the header provided at the head.

[0094] space switch 63, thus to capture the individual internal slots given from the transmitting circuit 62 ₁ to 62 _3, individually corresponding to the output port 64 ₁ to 64 _3, which is the destination for the SDH line and the ATM line Route in parallel.

[0095] The receiving circuit 65 _1, separating circuit 71 ₁ stores the transmission information of these lines in the memory 72 ₁ separates the SDH line and the ATM line of the output ports 64 ₁ destined again, the output control circuit 73 ₁ is The contents of the memory are read based on the format of the frame to be output to the output port 64 ₁ . Therefore, the output ports 64 ₁ to 64 ₃ are provided with ATM cells ((FIG. 10) which are simultaneously applied to a plurality of input ports by any combination of the input ports 61 _{1 to} 61 ₃ .
,), (FIG. 10,), (FIG. 10,), ...) are SD
The time slots other than the time slots pre-allocated for the H line (FIGS. 10 (1) to (6), ...) Are sequentially allocated and output.

Therefore, according to the present embodiment, the cross-connect processing in the data exchange network in which the SDH line and the ATM line are mixed is performed in an integrated manner. In this embodiment, the memory memories 68 _k1 and 68 _k are used in each transmission circuit.
_{Although k2} is configured by using individual memory elements, the present invention is not limited to such a configuration, and may be configured integrally with a single memory element.

FIG. 11 is a diagram (1) showing another embodiment corresponding to the invention described in claim 5. In FIG. FIG. 12 shows claim 5.
FIG. 8 is a diagram (2) showing another embodiment corresponding to the invention described in (1). In this embodiment, like the embodiment shown in FIG. 5, a plurality of output ports 55 _{11 to} 55 ₃₃ are grouped, and a plurality of paths are individually provided to the receiving circuits 54 _{1 to} 54 ₃ that accommodate these output ports. The embodiment shown in FIG. 6 is applied to a cross-connect device configured by connecting an internal link 56 ₂ composed of. Accordingly, it features of the structure of this embodiment, provided with a place in competition control circuit 82 ₁ to 82 ₃ competition control circuit 111 ₁ (111 _2, 111 ₃₎ receiving circuit 65 ₁
~ 65 ₃ instead of the receiving circuit 121 ₁ (121 ₂ , 12
1 ₃ ). It should be noted that components having the same functions and configurations as those shown in FIGS. 5 and 6 are designated by the same reference numerals, and description thereof will be omitted below.

[0098] contention control circuit 111 _{1-111 3} each receiving circuit 121 ₁ to 121 ₃ correspond individually. In the competition control circuit 111 ₁ , the common bus 81 is connected to the determination circuit 112.
The input of _{1 and} the output of the return circuit 113 ₁ are connected, and the output of the determination circuit 112 ₁ is connected to the count input of the counter 114 ₁ . The output of the counter 114 ₁ is connected to the address input of the conversion memory 115 ₁ and its data output is connected to the input of the arithmetic circuit 116 ₁ . Arithmetic circuit 116
The output of _{1 is} the input of the return circuit 113 ₁ and the comparison circuit 11
7 ₁ connected to one input. The clock bus 84 is connected to the other input of the comparison circuit 117 ₁ and its output is connected to the input of the memory 118 ₁ . The output of the memory 118 ₁ is connected to the preset input of the counter 114 ₁ .
Since the configurations of the competition control circuits 111 ₂ and 111 ₃ are the same as the configurations of the competition control circuit 111 ₁ , the same reference numbers in which “ ₂ ” and “ ₃ ” are given to the respective corresponding components as suffix numbers A number is given and the description is omitted here.

[0099] Further, the transmission circuit, the transmission circuit 62 ₁ to 62 ₃ are used as shown in FIG. 6, for the space switch, the intermediate switching circuits 53 _1, 53 ₂ or thereto equivalent switch circuit shown in FIG. 5 Used.

The operation of this embodiment will be described below with reference to FIGS. 11 and 12. The determination circuit 112 ₁ takes in the destination of the time-division-multiplexed ATM cell from the common bus 81, compares the destination with the output port connected to the corresponding receiving circuit, and sends out a pulse when they match. The counter 114 ₁ counts the number of ATM cells addressed to the corresponding output port by counting such pulses, and obtains the relative slot number in the same manner as in the embodiment shown in FIG. The conversion memory 115 ₁ converts such a relative slot number into an absolute slot number. The absolute slot number thus obtained is shown in FIG.

[0],
As indicated by [1], [2], ..., The serial numbers are recyclically assigned to the output ports included in the same group and transmitting the processing result of the cross-connect processing in parallel. The arithmetic circuit 116 ₁ divides the absolute slot number (for example, “7”) by the number of output ports included in each group (= 3) to obtain a quotient, and the quotient (= 2).
The time information indicating the transmission timing (<0>,
<1>, ... ) As.

The comparison circuit 117 ₁ compares the time information thus obtained with the real-time time obtained via the clock bus 84, and outputs a pulse when the former is later than the latter. . The memory 118 ₁ applies such a pulse to the built-in address counter to shift the address of the storage area to be read, and further reads the contents written in advance in the storage area, thereby performing the above-mentioned transmission. The absolute slot number (= 0, 3, 6, ... (Hereinafter, referred to as “initial slot number”) at the beginning of the timing is output. Such an absolute slot number is preset in the counter 114 ₁ , and the above-mentioned time information is given to the transmission circuit via the return circuit 113 ₁ and the common bus 81.

[0102] assigned to each ATM cell an internal slot that corresponds to each transmission circuit such time information, the receiving circuit 121 ₁ to 121 _3, as shown in FIG. 12, a group of output ports, respectively the destination S separated for each
The DH line and the ATM line are multiplexed and provided.

Therefore, according to this embodiment, even in the cross-connect device constructed by grouping the output ports, by adding the above-mentioned simple additional circuit, the SDH line and the ATM line are integrated in the cross-connect. Processing is performed.

Although the common bus 81 is composed of a single bus in the embodiments shown in FIGS. 6, 7 and 11,
The present invention is not limited to such a configuration, and for example, as disclosed in Japanese Patent Application No. 4-267227, it is possible to increase the capacity while suppressing the operating speed by using a plurality of buses. You can also

[0105]

As described above, according to the present invention, the multiplexed signal supplied to the input port is divided into frames of a predetermined length, the cross-connect process is performed for each frame, and the routing between the input means and the output means is performed. Regarding the frame flow in the above, it is unified through an ATM switch and formed into a pipeline, or is dispersed into a plurality through a switch having a plurality of ports, and is further mixed and multiplexed in the above-mentioned multiplexed signal. For the ATM line, the vacant path on the output port is appropriately allocated and the cross-connect processing is performed centrally.

Therefore, as compared with the conventional example in which the minimum line multiplexed in the multiplex signal is used as the processing unit of the cross-connect processing, the parallel expansion degree can be set to a large value, and the speedup can be surely supported. In addition, sync line and AT
It is possible to perform integrated cross-connect processing on M lines, and the performance of the cross-connect device is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment corresponding to the invention described in claim 1.

FIG. 2 is a diagram for explaining the operation of this embodiment.

FIG. 3 is a diagram showing an embodiment corresponding to the invention described in claims 2 and 3.

FIG. 4 is a diagram for explaining the operation of this embodiment.

FIG. 5 is a diagram showing an embodiment corresponding to the invention described in claim 4.

FIG. 6 is a diagram showing an embodiment corresponding to the invention described in claim 5;

FIG. 7 is a diagram showing a configuration of a competition control unit.

FIG. 8 is a diagram illustrating an operation of a conversion memory.

FIG. 9 is a diagram showing a time division multiplexed signal input to a space switch.

FIG. 10 is an operation timing chart of the present embodiment.

FIG. 11 is a diagram (1) showing another embodiment corresponding to the invention described in claim 5;

FIG. 12 is a diagram (2) showing another embodiment corresponding to the invention described in claim 5;

FIG. 13 is a diagram showing a first configuration example of a conventional cross-connect device.

FIG. 14 is a diagram showing a frame structure of a new synchronous multiplex interface.

FIG. 15 is a diagram showing a second configuration example of a conventional cross-connect device.

FIG. 16 is a diagram showing a third configuration example of a conventional cross-connect device.

[Explanation of symbols]

11, 31, 52, 62 Transmitting circuit 12, 51, 61, 132, 135, 138, 152,
161 input port 13 internal bus 14, 32, 54, 65, 121 receiving circuit 15, 55, 64, 133, 136, 139, 155
163 output ports 16, 35, 71, 154, 164 separation circuit 17, 22, 68, 72, 156 memory 18 internal multiplexing circuit 19 separation control circuit 20 internal multiplexing control circuit 21 internal separation circuit 23, 33, 80, 151, 162 multiplexing circuit 24 internal separation control circuit 25 multiplexing control circuit 34 common buffer type switch 36 common memory 37 distribution circuit 38 address memory 39 address selection circuit 40 write address generation circuit 53 intermediate switch circuit 56 internal link 63 space switch 66 competition control Part 67 Demultiplexing circuit 69 Selection circuit 70 Input control circuit 73 Output control circuit 81 Common bus 82,111 Competitive control circuit 83 Clock circuit 84 Clock bus 85,112 Judgment circuit 86,113 Return circuit 87,114 Counter 88,115 Change Memory 89,117 comparator circuit 116 computing circuit 118 memory 131,134,137,153 cross-connect circuit 157 read address counter 158 write address counter 165 P converter 166 parallel-serial conversion circuit

Claims (5)

[Claims] 1. A cross-connect device which takes in a multiplexed signal in which a plurality of lines are multiplexed from a plurality of input ports and routes the signals to a plurality of output ports based on routing control information preset for these lines, Based on the structure of the multiplex signal, the separating means for separating the signal for each line, and for each line separated by the separating means,
Input means arranged to correspond to the input port, and internal multiplexing means for combining and multiplexing for each destination indicated by the routing control information and transmitting a frame individually corresponding to the output port Of the frames transmitted by the internal multiplexing means,
An internal separation unit that captures a frame corresponding to a preset specific destination and separates each line, and a configuration in which the line separated by the internal separation unit is preset to an output port corresponding to the specific destination And a output unit arranged corresponding to each of the output ports. 2. A cross-connect device that takes in a multiplexed signal in which a plurality of lines are multiplexed from a plurality of input ports and routes the signals to a plurality of output ports based on destination information added to transmission information for these lines, Separation means for separating the signal for each line based on the configuration of the multiplex signal, and individual lines separated by the separation means,
Internal multiplexing means for combining and multiplexing for each destination indicated by the destination information and sending out a frame individually corresponding to the output port, and input means individually arranged corresponding to the input port Of the frames transmitted by the internal multiplexing means,
An internal separation unit that captures a frame including preset specific destination information and separates each line, and a line separated by the internal separation unit is preset to an output port corresponding to the specific destination information. A cross-connect device, comprising: a multiplexing unit configured to multiplex and transmit the configuration, and an output unit arranged corresponding to each of the output ports. 3. The cross-connect device according to claim 2, wherein the re-multiplexing unit multiplexes the frames sent from the input unit corresponding to each input port, and the re-multiplexing unit multiplexes the frames. An ATM switch that takes in a plurality of frames and performs routing based on the destination information included in each frame, and separates the plurality of frames routed by the ATM switch for each destination indicated by the destination information and supports the destination And a distribution unit that distributes to the output unit. 4. The cross-connect device according to claim 1 or 2, wherein a frame individually sent from an input means corresponding to each input port is fetched and included in routing control information or each frame. A cross-connect device comprising a switch that faces each output means and performs routing based on a destination indicated by destination information. 5. A multiplexed signal obtained by multiplexing a plurality of lines from a plurality of input ports is fetched, and these lines are
In a cross-connect device having a routing means for routing to a plurality of output ports indicated by preset routing control information, a path which is vacant in each of the plurality of output ports is managed and a destination of the routing is managed. And a allocating means for allocating a vacant path of the output port corresponding to the destination according to the request specified by the above, and separating the ATM line and the synchronous multiplex line multiplexed into the signal based on the configuration of the multiplex signal. Demultiplexing means, a synchronous line relay means for relaying to the routing means based on the routing control information, for each synchronous multiplex line demultiplexed by the demultiplexing means, and an individual ATM line demultiplexed by the demultiplexing means. Allocating means for the destination indicated in the cell of the line And an asynchronous line relay means for relaying the path to the routing means on the basis of the routing control information corresponding to the path, and the input means arranged individually corresponding to the input port. A cross-connect device comprising: