JPH03225541A - Cache memory device - Google Patents

Abstract

PURPOSE:To speed up data access by reading other data in a cache memory when the comparison contents of a comparison part show a coincidence and data as an object of access is already read in the cache memory. CONSTITUTION:If a request to access next data is made by a central processing unit 13 during data transfer from a main storage device 7, a cache memory device 15 compares the address of a direct memory 3 with the access address and also compares the value of a mishit address register 20 with the access address. When the value of the register 20 matches the access address, it is found that the data to be accessed are being transferred from the device 7, so further flags are checked; when the data to be accessed are all read in the cache memory 4 from the device 7, other data are read in the memory 4 from the device 7 and the data to be accessed is read out of the memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory device provided for a central processing unit to access data in a main storage device at high speed.

[Conventional technology]

Figure 2 shows, for example, Re5ton Pubfishing.
Company+Inc, (Virginia, 1983)
Published by HIGH5PEED MEMORY SYSTE
This is a block diagram including a cache memory device that buffers part of the data in the main memory and reads and writes data according to data access requests from the central processing unit, as shown on page 18.19 of MJ. . In FIG. 2, 13 is a central processing unit that performs calculations and controls for processing data, 7 is a main memory that stores data necessary for data processing, and 14 is a central processing unit that stores data necessary for data processing at high speed. This is a cache memory device provided for accessing data in a computer.

The cache memory device 14 includes a # controller 2, a directory memory 3, a cache memory 4, a data switch 9, and an address switch IO. Details of each of the above components of the cache memory device 14 will be described in the operation description below. The central processing unit 13 and the cache memory device 14 are connected by an address line 1 and a data line 5.

The cache memory device 14 and the main memory device 7 are connected by a main memory address line 6 and a main memory data line 8.

Further, although not shown, there is a central processing unit 1 between the control unit 2 in the cache memory device 14 and the central processing unit 13.
Several control lines for communication such as an access request line for transmitting an access request from 3 to the control unit 2 are provided.

Next, the operation of this conventional example will be explained.

When there is a read or write access request from the central processing unit 13 to the address indicated by the address line 1, the control unit 2 of the cache memory device 14 refers to the contents of the directory memory 3 using the access address. , it is checked whether the access data corresponding to the access address is stored in the cache memory 4. When the access data is stored in the cache memory 4 (referred to as a hit), the control unit 2 controls the data switch 9, and in the case of a read request, the data is stored in the cache memory 4 according to the content of the access request from the central processing unit 13. The value of the access data is outputted to the data line 5 and taken into the central processing unit 13. In the case of a write request, the data output from the central processing unit 13 to the data line 5 is written into the cache memory 4.

If the access data is not stored in the cache memory 4 (referred to as a miss hint), the control unit 2 controls the data switch 9 and the address switch 10, outputs the access address to the main memory address line 6, and outputs the access address to the main memory address line 6. The address data in the storage device 7 is transferred from the main storage device 7 to the cache memory 4 via the main storage data line 8.
If the access request from the central processing unit 13 is a read request, the data from the main storage device 7 to the cache memory 4 is output to the data line 5, and the central processing unit 13 takes in the data. Further, in the case of a write request, the access data output from the central processing unit 13 to the data line 5 is written to the cache memory 4 instead of the data from the main memory 7 . When data is transferred from the main storage device 7 to the cache memory 4, the contents of the directory memory 3 indicating the correspondence between the data in the cache memory 4 and the data in the main storage device 7 are updated.

The main storage device 7 has a slower processing speed than the cache memory 4, and in the cache memory device 14, whether or not the main storage device 7 is accessed depends on whether or not the data to be accessed is in the cache memory 4. Although the time required for access varies depending on the case, the central processing unit 13 receives the busy signal from the cache memory 4 or r
The validity of the read data on the data line 5 and the end of the access operation can be known through communication lines indicating the state of the cache memory device 14, such as the EADY signal.

- When fishing on a boat, the contents of the cache memory 4 are divided into blocks for each number of data, and if the access data from the central processing unit 13 is not in the cache memory 4, not only the accessed data but also the block to which the data belongs ,
It is read into the cache memory 4 from the main storage device 7.

With this configuration, when there is no data accessed from the central processing unit 13 in the cache memory 4, the block containing the data accessed from the main storage 7 is transferred to the cache memory 4, and normally the central processing unit Since the data processed by the cache memory 13 exists locally to some extent within the main storage device 7, by dividing the cache memory 4 into blocks in this way, the hint rate of the cache memory 4 can be increased.

[Problem to be solved by the invention]

As mentioned above, in conventional cache memory devices, when a cache memory miss hint occurs, data is transferred from the main memory in block units, so while the data is being transferred from the main memory to the cache memory, However, there was a problem in that the next access request from the central processing unit could not be accepted.

This invention was made in order to solve the above-mentioned problems, and aims to provide a cache memory device that can receive and execute the next access request even during data transfer from the main storage device. purpose.

[Means to solve the problem]

The cache memory device according to the present invention includes a miss address register 20 for storing the address of access data to be accessed by the central processing unit 13 when the cache memory 4 does not store the access data to be accessed by the central processing unit 13; A comparison unit 22 that compares the access address of the next data access request with the value of the miss hint address register 20 while transferring data from the main storage device 7 to the cache memory 4 when no data is stored; If the contents compared by the comparison unit 22 match and the data requested for access has already been read from the main storage device 7 to the cache memory 4, other data is transferred from the main storage device 7 to the cache memory 4. The cache memory 4 is characterized in that it includes a control unit 23 that performs control to read data from the cache memory 4 as well as to read data for which access has been requested from the cache memory 4.

[Effect]

The miss address register 20 is stored in the cache memory 4.
If the access data to be accessed by the central processing unit 13 is not stored in , the address of the access data is stored. When the access data is not stored in the cache memory 4, the comparator 22 stores the access address of the next data access request in the miss address register while transferring the data from the main storage device 7 to the cache memory 4. Compare with the value of 20. The control unit 23 is
If the contents compared by the comparison unit 22 match and the data requested for access has already been read from the main storage device 7 to the cache memory 4, other data is read from the main storage device 7 to the cache memory 4. At the same time, it also performs control to read the data requested for access from the cache memory 4. Therefore, data is read from cache memory 4 simultaneously with data transfer from main storage device 7.

〔Example〕

FIG. 1 is a block diagram including a cache memory device according to an embodiment of the present invention. In FIG. 1, components corresponding to those shown in FIG. 2 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 1, 11 is a write address register that stores a write address when writing data to the cache memory 4, 12 is a read address register that stores a read address when read data from the cache memory 4, and 21 is a number. The central processing unit 13 accesses the 2°cache memory 4, which is a flag (flag group) corresponding to the data in the block divided into blocks and indicating whether or not the transfer of individual data from the main storage device 7 has been completed. A miss hint address register 22 stores the address of the access data when the access data to be accessed is not stored in the cache memory 4; During the transfer, a comparison unit compares the access address of the next data access request with the value of the mishit address register 20. A comparison unit 23 compares the access address of the next data access request with the value of the mishit address register 20. has already been read from the main storage device 7 to the cache memory 4, read other data from the main storage device 7 to the cache memory 4, and read the data for which access was requested from the cache memory 4. This is a control section that performs control. The cache memory device 15 of this embodiment includes a directory memory 3, a cache memory 4, a data switch 9, a write address register 11, a read address register 12, a miss hint address register 20,
It includes a flag 21, a comparison section 22, and a control section 23.

Next, the operation of this embodiment will be explained. A mishit address register 20 is connected to the address line 1 from the central processing unit 13 and stores the address of mishit data. A flag group 21 corresponding to data in a block and indicating whether or not individual data has been transferred from the main storage device 7
is connected to the control section 23, and the control section 23 controls its value. Mishit address register 20 value and central processing bag? The comparison unit 22 that compares the address of the access data from 1f13 is realized as a part of the control unit 23, for example. In addition, in this embodiment, addresses for accessing the cache memory 4 are stored in two parts, a write address register 11 and a read address register 12, and writing and reading are performed simultaneously to different addresses. I can do it.

The cache memory 4 having such a configuration starts reading data from the main storage device 7 when a mishint occurs, and at the same time writes the address of the mishinted data into the mishint address register 20. Further, at the same time as reading of blocks from the main storage device 7 to the cache memory 4 is executed one data at a time, the control unit 23 turns on the flag 21 corresponding to the data in the block to indicate completion of data reading. . If there is a next access request from the central processing unit 13 during data transfer from the main storage device 7, the cache memory device 15 with this configuration will access the address of the directory memory 3 in the same way as a normal cache memory device. At the same time, the value of the mishint address register 20 and the access address are compared. Miss hint address register 2
If the value of 0 and the value of the access address are different, it operates like a normal cache memory device, but if the value of the mishit address register 20 and the value of the access address match, the data requested to be accessed is Since it can be seen that the data is being transferred from the main storage device 7, the flag is further checked, and if the data requested for access has already been read from the main storage device 7 to the cache memory 4, the data is transferred from the main storage device 7. Other data is read into the cache memory 4, and data for which access has been requested is read from the cache memory 4.

As a result, even if the cache memory device f15 is in the middle of reading a block from the main storage device 7 due to a miss hint, if the immediately following access request is for data belonging to the same block, the cache memory device f15 will not be able to read the block from the main storage device 7. Since there is no need to wait for completion, access can be performed faster than in conventional cache memory devices.

In this way, in this embodiment, when a block is transferred from the main memory to the cache memory due to a miss in the cache memory, the address of the block being transferred is stored, compared with the address of the next access request, and By referring to the data transfer end flag of
Determine whether the requested data is in the next block being transferred. Furthermore, since the address register of the cache memory is divided into read and write registers, the configuration is such that reading from the cache memory can be performed even during block transfer from the main storage device to the cache memory. Therefore, cache memory misses,
Even if a block is being transferred from the main memory, if the address of the next accessed data belongs to the same block as the missed data, the next access can be executed without waiting for the block transfer to complete. Therefore, data can be accessed faster than conventional cache memory devices.

〔Effect of the invention〕

As described above, according to the present invention, there is a miss address register that stores the address of access data when the access data is not stored in the cache memory, and a miss address register that stores the address of the access data when the access data is not stored in the cache memory, and a mishit address register that stores the address of the access data when the access data is not stored in the cache memory. While data is being transferred from the device to the cache memory, a comparison section compares the access address of the next data access request with the value of the mishint address register, and if the contents compared by this comparison section match and the access request If the data that was previously accessed has already been read from the main memory to the cache memory, read the other data from the main memory to the cache memory, and read the requested data from the cache memory. Since the configuration is equipped with a control unit that performs control, even if the cache memory misses a hint and a block transfer from the main memory is in progress, the address of the next accessed data will be the same block as the miss-hinted data. , the next access can be executed without having to wait for the block transfer to be completed, resulting in the effect of further speeding up data access.

[Brief explanation of drawings]

FIG. 1 is a block diagram including a cache memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram including a conventional cache memory device. 4... Cache memory, 7... Main storage device, 13
. . . central processing unit, engineering 5 . . . cache memory device, 22 . . . comparison section, 23 . . . control section.

Claims (1)

[Claims] In a cache memory device that is connected between a central processing unit and a main storage device and includes a cache memory in which a plurality of pieces of data are stored as a block, the central processing unit accesses the cache memory. a miss address register that stores the address of the accessed data when the data is not stored; and a miss-hit address register that stores the address of the accessed data when the data is not stored; While the access address of the next data access request is compared with the value of the mishit address register mentioned above, the contents compared by this comparison section match, and the data requested to be accessed has already been stored in the main memory. If the device has read data into the cache memory, read other data from the main storage device into the cache memory, and control to read the requested data from the cache memory. A cache memory device comprising: