JPH03219650A - Probe card - Google Patents

Abstract

PURPOSE:To make a probe card itself sharply small-sized and to surely realize high-density multi-pin structure by a method wherein a group of bumps and an electricity-transmitting route are formed on a silicon substrate. CONSTITUTION:A taper part 2 is formed in the peripheral edge part of a single- crystal silicon substrate 1; the substrate is doped with p-type impurities. A group of bumps 3 which are designed so as to be situated on pad positions of a wafer chip are formed in the pad positions by an etching method. Then, in order to lower a resistance value, acceptor impurities whose valence is +3 or donor impurities whose valence is +5 are introduced into the bumps 3 formed by an etching operation. Since the p-type silicon substrate 1 is used in this case, n-type impurities whose valence is +5 are implanted into the group of bumps 3. Interconnection patterns on the silicon substrate 1 on which metal electricity-transmitting routes 5 have been vapor-deposited are formed from the group of bumps 3 up to the taper part 2 on the silicon substrate 1. In addition, compensation circuits as countermeasures for high-frequency noise are wired to the metal electricity-transmitting routes 5.

Description

[Detailed Description of the Invention] <Industrial Application Field> In order to test IC chips, which are becoming increasingly dense, the present invention utilizes a part of the IC manufacturing method to test the pads of IC chips. The present invention relates to a probe card in which a bump group corresponding to a group and a connection bump group corresponding to a tester side are formed, and an alignment window portion is provided.

<Prior Art> When manufacturing semiconductor products such as IC chips, etc., when inspecting the IC chips in the wafer state at the final stage of the pre-process, a test is performed as shown in FIGS. 10 and 11, respectively.
A probe pad d is used, which is composed of a test needle group mainly consisting of a stylus a, and a substrate C made of epoxy resin or the like mainly consisting of a group of electrical transmission paths connected thereto.

This probe card d is connected to a tester g through a substrate C, a motherboard e holding it, and a connector f connected thereto.

The center of the board C is provided with a plurality of stylus a, which protrudes downward from the board C and is fixed with an insulator such as epoxy resin. An IC chip j is placed at a predetermined position on a movable table, and is guided to a connector f and then to a tester g through an electric transmission path.
The moving stage is moved to sequentially feed the IC chip j, and electrical measurements are performed by making each stylus a correspond to each pad of the IC chip j.

<Problems to be Solved by the Invention> In recent years, there has been an increasing trend toward higher density of IC chips, and accordingly, the number of bins (multiple pads) is increasing. Correspondingly, I
To test the C-chip, it is necessary to increase the number of styli on the probe card.

Currently, efforts are being made to improve the diameter and arrangement of the stylus, but there is a limit to increasing the number of stylus, which is a bottleneck in the production of IC chips and the like.

Also, the problem with the tip of the stylus increases as the density increases. For example, due to the finer diameter of the stylus, misalignment, abrasion resistance, deformation of the stylus, shortening of the stylus length due to the adhesion of aluminum scraps, maintaining the flatness of the entire stylus, damage to the IC pad due to the stylus, and durability. , problems such as stability arise.

The biggest problem is that the assembly of these styli on the probe card is all done by hand, and the X-Y-Z position of the tip of the stylus is
It is an absolute requirement to achieve various precisions such as three-dimensional position, overall flatness, wear resistance, and maintenance of electrical characteristics, which requires a great deal of effort.

Furthermore, at the work site of an IC manufacturer, it is very difficult to align the IC chip and the probe card and to maintain card performance.

In order to solve the above-mentioned problems, the present invention uses an IC chip manufacturing method to create bump groups corresponding to pads and bumps corresponding to measurement terminals on a semiconductor chip, without using a stylus. It is an object of the present invention to provide a probe card in which a group is formed, an alignment window is provided through a semiconductor chip, and an electric transmission path and a compensation circuit are wired.

Means to solve problems〉 The above object of the present invention can be achieved by the following configuration.

In other words, the gist is that a group of bumps corresponding to the pads of a chip are formed by etching on a p-type or n-type semiconductor substrate such as silicon, which has a tapered portion formed on its peripheral portion or one end side. is formed in a protruding manner, and the bump group has a valence +
A probe characterized in that an impurity for lowering the resistance value of 3 or +5 atoms is implanted, an electric transmission path is arranged in the bump group, and the resistance value is increased by forming an oxide film or the like on the other surface of the substrate.・A wafer is formed by etching on the card and its peripheral portion, or on a p-type semiconductor substrate with a tapered portion formed on one end side, or a p-type semiconductor substrate with a tapered portion formed on one end side, or an n-type semiconductor substrate such as silicon. - Bump groups corresponding to the pads of the chip and bump groups corresponding to the tester terminals are separately formed in a protruding manner, and impurities of valence +3 or valence +5 for reducing resistance are implanted into each bump group. Furthermore, an appropriate electrical transmission path is arranged between the bump group corresponding to the wafer chip and the bump group corresponding to the tester terminal, and the resistance value is increased by oxidizing the other surface of the semiconductor substrate. 3. The probe card according to claim 1, further comprising a compensation circuit for high frequency countermeasures wired on the semiconductor substrate in the electrical transmission path.

4. The probe card according to claim 1, further comprising a positioning window provided through the semiconductor substrate substantially in the center thereof, further comprising a polarizing prism within the positioning window. 5. The 70-b card according to claim 4, further comprising a wide-angle lens such as a fisheye lens. 5. The probe card according to claim 4, further comprising an optical fiber autopsy lens mounted in the positioning window.

<Embodiments and Effects> The probe card according to the present invention will be described in detail below with reference to the drawings showing the embodiments thereof.

2 A1 Go 11 FIG. 1 ((), (υ), (c), and (d) are end views showing the manufacturing process of Example 1 of the present invention, respectively.

That is, (1) is a single crystal silicon substrate doped with a p-type impurity, on which a tapered part (21) is formed on the circumference, and on the same single crystal silicon substrate (1), a pad of a wafer chip is formed. A group of bumps (3) designed to be on the same position are formed by an etching method.There are two types of etching methods: wet etching and dry etching. The dry etching method described above uses an activated gas, and in this example, the bump groups were formed by the wet etching method. An etching method may also be used.

Next, an acceptor impurity with a valence of +3 or a donor impurity with a valence of +5 is introduced into the bump G) formed by the etching described above in order to lower the resistance value.

Typical impurities with a valence of +3 used include boron, aluminum, indium, and gallium, and impurities with a valence of +5 include arsenic, antimony, and phosphorus.

In this embodiment, by using a p-type silicon substrate (1), an n-type impurity (a) with a valence of +5 is implanted into the bump (3) group. Methods for introducing this n-type impurity (4) include a thermal diffusion method and an ion implantation method, and either method can be used.

Then, as shown in FIG. 1 (c) and FIG. 2, the silicon substrate (]
) A wiring pattern on which a metal transmission path (5) (for example, aluminum) is vapor-deposited is formed up to the tapered portion (a end) on the silicon substrate (1).

Furthermore, a compensation circuit (6) for high frequency countermeasures (noise) is wired to the metal transmission line (5), and this compensation circuit (6) eliminates the influence of high frequencies on other transmission lines (51). That is, the compensation circuit (6) is one in which an equivalent circuit is wired on the silicon substrate (1) between the electric transmission lines (5), (5) or to the electric transmission N (5).

Further, the surface of the silicon substrate (1) other than the electrical transmission path (5) and the compensation circuit (6) is constructed to have a large resistance value by an oxide film or the like.

Embodiment 2 FIGS. 3(A), 3(B), 3(C), and 3(D) are explanatory end views showing the manufacturing process of Embodiment 2 of the present invention, respectively.

That is, (1) is a single-crystal silicon substrate doped with a P-type impurity, on which a tapered part (21) is formed on the circumference, and on the lower surface of the single-crystal silicon substrate (1), a wafer chip is formed. A group of bumps (3) designed to be in the same position as the pad positions, and on the upper surface of the silicon substrate (1),
A group of bumps (3)' designed to be in the same position as the tester side terminals is formed by an etching method.

Next, in order to lower the resistance value, an acceptor impurity with a valence of +3 or an acceptor impurity with a valence of +3 is added to the bumps (3) and (3)' group.
By using a p-type silicon substrate (1) in this example, an n-type impurity (with a valence of +5) is introduced into the bumps (3) and (3)' group. 4
).

As shown in FIG. 3(d), FIG. 4, and FIG. 5, a group of bumps (3) corresponding to the pads of the wafer chip and bumps corresponding to the connection terminals on the tester side are formed by vacuum evaporation or the like. (3) An appropriate electric transmission path (51) is formed on the lower surface of the silicon substrate fil between the groups.

Furthermore, a compensation circuit (6) for preventing high frequency generation (noise) is wired to the above-mentioned transmission line, and this compensation circuit (6) eliminates the influence of high frequencies on other transmission lines (9). I can do it.

Further, on the silicon substrate (1) other than the bumps (3), (3) group and the electrical transmission line (5), impurities are introduced to increase the resistance value to increase the resistance value between the lines. do.

In addition, in the above-mentioned Example 1 and Example 2, the silicon substrate (
1) When forming the tapered part (2) on the peripheral line, when drawing a wiring circuit on the silicon substrate (1), it is easier to draw on an inclined surface than on a flat surface because the circuit is drawn with light. This is because the object to be measured is flat, so some level difference is required.Furthermore, when connecting the silicon substrate +11 to the motherboard side, it is desirable that the terminal side is formed thin. It is.

Therefore, the shapes of the silicon substrate (1) as shown in FIGS. 6(a), (b), (c), and (d) are conceivable.

Embodiment 3 FIGS. 7(a) and 7(b) respectively show a state in which the alignment window part (2) is installed at the center of the silicon substrate (1) shown in the present embodiment 1 and embodiment 2. Therefore, the bump (
21, (2)° group has the above alignment window ■ peripheral area,
The alignment window portion (7) is formed in a protruding manner.
This configuration allows the state of contact between the bump (3) and the pad (not shown) of the IC chip to be confirmed.

Next, Figure 8 (a) is the place! Figure 8 (+
1) is the place! A fisheye lens (9) is mounted inside the alignment window (7), so that the contact state can be observed over a wider area than in the small alignment window (71). An optical fiber autopsy lens 0■ is installed inside the window (7), and bumps (
3) The structure is such that the state of contact between the pad and the pad can be enlarged and observed.

In the present invention having the above configuration, the silicon substrate (1)
indirectly with the bumps (3) group facing downward and the bumps (3) group facing upwards to the connection terminals on the tester side,
Or it is directly held.

By appropriately positioning (X-Y and O angles) the movable table on which the IC chip is placed, appropriate pressure is applied between the pads of the IC chip (not shown) and the bumps (3) group. After confirming the contact by observing it from inside the alignment window (7), it becomes conductive, and it is connected directly to the tester side through the electrical transmission path (5) from the bumps (3)' group or from the electrical transmission path (51). The electrical characteristics of the IC chip are tested by conducting to the connection terminal.

<Effects of the Invention> As described above, according to the present invention, by forming bump groups and electrical transmission paths on a silicon substrate, the probe card itself can be significantly miniaturized, and
The positioning protrusion allows the state of contact with the pad to be observed, making it possible to reliably and densely create multiple bins. Also x-y
-The positioning accuracy of z is more accurate, and by forming the tapered part, the flatness of the bump group is increased, making it possible to freely attach electrical circuits to the tapered part surface without damaging the IC pad. Become.

The manufacturing of probe cards has therefore been greatly simplified and the possibility of automation has arisen to produce not only a single chip but also many chips at the same time, in some cases even multiple chips on an entire wafer in one process. It is also possible to inspect
This has various effects such as lowering manufacturing costs and increasing inspection efficiency.

[Brief explanation of drawings]

Figures 1 (a), (b), (8), and (d) are explanatory diagrams showing the manufacturing process of the glove card of Example 1 of the present invention, respectively;
FIG. 2 is an explanatory plan view of Embodiment 1 of the present invention, and FIG. 3 (A). (B), (8), and (2) are explanatory diagrams showing the manufacturing process of the glove card of Example 2 of the present invention, respectively; Explanatory plan view showing the bump group on the tester side, Figure 6 (A) 1
(B), (8), and (D) are respectively perspective views showing various shapes of silicon substrates, FIGS. ) is Example 3
Figure 8 (b) is an explanatory diagram when a single-light prism is attached to the alignment window, Figure 9 is an illustration when a fisheye lens is attached to the alignment window. FIGS. 10 and 11 are explanatory diagrams showing a case where an optical fiber autopsy lens is attached, respectively, and are explanatory diagrams showing conventional examples. In the figure (1): Silicon substrate (2): Tapered part (3+', (31: bump group 4), impurity for reducing resistance (5): electrical transmission line (6), compensation circuit (71 = alignment window part) (to); Polarizing prism (9): Fisheye lens 0■: Autopsy lens 0＼

Claims (1)

[Claims] 1. Bumps corresponding to pads of a wafer chip are formed by etching on a p-type or n-type semiconductor substrate such as silicon, which has a tapered portion formed on its peripheral portion or one end side. A group of bumps is formed in a protruding manner, an impurity with a valence of +3 or +5 for reducing resistance is implanted into the bump group, an electric transmission path is provided in the bump group, and the other surface of the substrate is coated with an oxide film, etc. A probe card characterized by a large resistance value. 2. On a semiconductor substrate such as p-type or n-type silicon, which has a tapered portion formed on its peripheral portion or one end side, bump groups corresponding to the pads of the wafer chip and tester terminals are formed by etching. Each bump group is formed in a protruding manner, and each bump group is provided with a valence +
3 or a valence of +5 for reducing the resistance value, and furthermore, an appropriate electrical transmission path is arranged between the bump group corresponding to the wafer chip and the bump group corresponding to the tester terminal, and other than that. A probe card characterized in that the resistance value is increased by an oxide film or the like on the upper surface of a semiconductor substrate. 3. The probe card according to claim 1 or 2, wherein a compensation circuit for high frequency countermeasures is wired on the semiconductor substrate in the electric transmission path. 4. The probe card according to any one of claims 1, 2 and 3, characterized in that an alignment window portion is provided through the semiconductor substrate substantially at the center thereof. 5. The probe card according to claim 4, wherein a polarizing prism or a wide-angle lens such as a fisheye lens is mounted within the alignment window. 6. The probe card according to claim 4, further comprising an optical fiber autopsy lens mounted within the alignment window.