JPH03219644A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To reduce the interface-level density between a polycrystalline Si layer and a gate insulating layer, the interface fixed charge density and the like and to enhance the characteristics of a thin-film transistor comprising a polycrystalline Si thin film by a method wherein a gate insulating film is formed on the polycrystalline Si thin film without exposing the formed polycrystalline Si thin film to the air. CONSTITUTION:A polycrystalline Si layer 21, a gate insulating layer 22 and a gate electrode 23 are formed on a Pyrex glass substrate 110 by a patterning operation. In addition, phosphorus is implanted into the polycrystalline Si layer 21 by making use of the gate electrode 23 as a mask; a heat treatment is executed to activate its implanted region; after that, an interlayer insulating film 24 composed of SiO2 is formed by a CVD method. Contact holes 26 are made in the interlayer insulating layer 24 and the gate insulating layer 22; Al interconnections 25 are connected to the implanted region; a source electrode and a drain electrode are formed; the contact holes 26 are made in the interlayer insulating layer 24; an Al interconnection 25 is connected to the gate electrode 23.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to thin film transistors used in liquid crystal displays, image sensors, etc., and relates to a method for manufacturing thin film transistors using a low temperature process.

<Prior Art> A process similar to a conventional IC process has been used to manufacture thin film transistors that drive liquid crystal displays, image sensors, and the like. In this method, crystallization, formation of an insulating film, and activation of impurities are performed at a high temperature of nearly 1000° C., so the substrate material is limited to, for example, a quartz substrate, making it difficult to form a large area. In recent years, methods for lowering the process temperature have been proposed, and methods of forming an amorphous film or a polycrystalline film and using this as a starting material for crystallization by low-temperature solid phase growth, laser annealing, etc. are being considered.

By the way, since thin film transistors are generally field effect transistors, their characteristics are greatly influenced by the state of the interface between the gate insulating layer and the semiconductor layer. For this reason, in conventional high-temperature processes, the interface between the gate insulating layer and the semiconductor layer is created inside the semiconductor layer by thermal oxidation to maintain a good interface state.

On the other hand, in a low-temperature process, the gate insulating layer must also be formed at a low temperature, so the above thermal oxidation method cannot be used. Therefore, a method is used in which after processing a semiconductor film into a predetermined shape, surface treatment is performed using hydrofluoric acid, etc., and then a gate insulating film is formed on the semiconductor film using sputtering, CVD, etc. .

<Problems to be Solved by the Invention> In order to improve the characteristics of the thin film transistor manufactured by the above-mentioned low-temperature process, it is necessary to keep the surface of the semiconductor film clean and form an insulating film thereon. However, in the conventional method of surface treatment using hydrofluoric acid, etc., even if careful attention is paid to the hydrofluoric acid, water, etc.
It was difficult to avoid the contamination of ions such as A. In particular, when glass is used as the substrate, the ions in the glass may be dissolved into water. For these reasons, conventional methods have not been able to sufficiently reduce the interface state density, interface fixed charge density, etc.

In view of the above, an object of the present invention is to provide a method for manufacturing a thin film transistor with a good interface state between a semiconductor layer and a gate insulating layer.

Means for Solving the Problems> In order to achieve the above object, the present invention forms a polycrystalline Si thin film on a substrate, and forms a polycrystalline Si thin film on the polycrystalline Si thin film without exposing the polycrystalline Si thin film to the atmosphere. Provided is a method for manufacturing a thin film transistor, comprising forming a gate insulating film, further forming a gate electrode on the gate insulating film, and then patterning the polycrystalline Si thin film and the gate insulating film into a predetermined shape. .

<Function> When a gate insulating film is formed on the polycrystalline Si thin film without exposing the formed polycrystalline Si thin film to the atmosphere, the gate insulating film is formed on the surface of the polycrystalline Si thin film that remains in a clean state immediately after formation. can do. Therefore, in the present invention, "without exposure to the atmosphere" means without breaking the controlled atmosphere that can maintain the cleanliness of the surface of the polycrystalline Si thin film immediately after formation, such as in an inert gas atmosphere or vacuum. be.

Furthermore, at the stage of forming the gate insulating film, the polycrystalline Si thin film and the gate insulating film are patterned into a predetermined shape, and then,
When forming a gate electrode to form a gate electrode,
As shown in FIG. 5, there is a possibility that the gate electrode 23 and the polycrystalline Si layer 21 are short-circuited at the edge part of the polycrystalline Si layer 2I, but as in the present invention, after forming the gate electrode,
Since the i-thin film and the gate insulating film are patterned, the above-mentioned short circuit does not occur.

Furthermore, a mask is used to pattern the polycrystalline Si thin film and gate insulating film, and even if the position of this mask is slightly shifted, the previously formed gate electrode becomes self-aligned, and the gate electrode is always formed on the gate insulating film. It is located at the top, making the manufacturing process easier.

Furthermore, if short wavelength light such as ultraviolet light is irradiated immediately before the formation of the insulating layer, trace amounts of impurities adsorbed on the surface of the semiconductor film can be removed, resulting in a cleaner semiconductor film surface. A film can be formed.

<Example> An example of the present invention will be described in detail using FIGS. 1 to 4.

FIG. 1 shows the manufacturing apparatus used in this example. This device is located in the load lock chamber 101° on the board entrance side.
2. Annealing room! 03. It consists of a snow < ivy chamber 104 and a load lock chamber 105 on the substrate outlet side, and a gate pulp 109 is placed between each chamber, and a PECVD chamber 102 and an upper chamber 106
and RF power supply 107 and PECVD electrode +08, annealing chamber 103 has heater +06, sputtering chamber +04 has heater +06, RF power supply 107 and spa sota target)
A low-pressure mercury lamp +12 is provided, and a substrate +10 is moved through each chamber. Incidentally, each chamber is composed of a quartz tube.

First, a Pyrex glass substrate +10 is carried in from the load lock chamber 101, and then moved to a PECVD chamber +02. Then, P E CV D under the conditions shown in Table 1 below.
An a-5i film is formed by a (plasma enhanced CVD) method.

Subsequently, the substrate +10 is moved to the annealing chamber 101, and the a-5i film is annealed under the conditions shown in Table 2 below to cause in-phase crystal growth and form a polycrystalline film.

Subsequently, the substrate 110 is moved to a sputtering chamber 1-5, and a 5i02 film to be a gate insulating film is formed under the conditions shown in Table 3 below.

As described above, in this example, the semiconductor film formation, crystallization, and gate insulating film formation were performed in an inert gas atmosphere or without breaking the vacuum.

Next, an At film is formed on the 5i02 film by sputter deposition, and this is patterned by photolithography to form a gate electrode in a predetermined shape.

Thereafter, the 5i02 film and the polycrystalline Si film are patterned into a predetermined shape using photolithography in the same manner as described above. At this time, even if the position of the mask shifts, the gate electrode itself plays the role of a mask below the gate electrode, so the gate electrode is always on the 5i02 film and the relative position between the gate electrode and the 8102 film is There is no possibility that the gate electrode and the polycrystalline Si film come into contact with each other due to misalignment.
It is easy to match each position when patterning the i02 film and the polycrystalline Si film.

FIG. 2 shows the structure of the thin film transistor of this example. FIG. 2(a) is a plan view, and FIG. 2(b) is a sectional view.

By the above patterning, Pyrex glass substrate +
A polycrystalline Si layer 2+, a gate insulating layer 22, and a gate electrode 23 are formed on the layer 10.

Furthermore, using the gate electrode 23 as a mask, the polycrystalline Si layer 2
After injecting phosphorus into 1 and performing activation heat treatment on the implanted region, an interlayer insulating film 24 made of 5i02 is formed by CVD. A contact hole 26 is formed in the glabella insulating layer 24 and the gate insulating layer 22, and the implanted region VCA4 wiring 25 is connected to form source and drain electrodes.A contact hole 26 is formed in the glabella insulating layer 24 and the gate'
The H-pole 23VCAt wiring 25 is connected. Note that the channel portion was 20 μm in length and 10 μm in length.

AtWl to 5i02/polycrystalline 5iljlJ shown above
Figure 3 shows the CV characteristics when the poles are attached. The solid line is a graph of the sample of this example, and the broken line is a graph of a sample that was crystallized, exposed to air, and then treated with hydrofluoric acid based on a conventional process. It was found that in the conventional process, the flat band voltage VFB shifted to the negative side compared to the process of the present invention. This indicates that positive fixed charges exist at the interface between the semiconductor film and the insulating film, and it can be seen that almost no fixed charges exist in the sample of this example.

Figure 4 shows the drain current I of the thin film transistor of this example.
D5-gate voltage VQ characteristic (solid line) is shown.

The broken line indicates the characteristics of a thin film transistor produced by a conventional process similar to that shown in FIG. From a comparison of these characteristics, it was found that the thin film transistor manufactured by the process of the present invention has higher ION current and lower VT)l, and has better characteristics.

Note that the characteristics of the thin film transistor were further improved by irradiating the polycrystalline S1 film with a low-pressure mercury lamp provided in the sputtering chamber before forming the 5i02 film serving as the gate insulating film.

<Effects of the Invention> According to the manufacturing method of the present invention, the interface state density, interface fixed charge density, etc. between the polycrystalline St layer and the gate insulating layer can be reduced,
Furthermore, short circuits between the gate electrode and the polycrystalline Si layer can be easily prevented, thereby improving the characteristics of the thin film transistor using the polycrystalline Si thin film.

Furthermore, this makes it possible to provide high performance thin film transistors at low cost.

4

[Brief explanation of drawings]

FIG. 1 is a diagram of a manufacturing apparatus according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a thin film transistor according to an embodiment of the present invention, and FIG. 3 is a CV characteristic diagram shown in an embodiment of the present invention. Figure 4 shows ID5-v of the thin film transistor shown in Figure 2.
The Q characteristic diagram, FIG. 5, is a diagram illustrating a short circuit between the gate electrode and the polycrystalline Si layer. 21... Polycrystalline S1 layer 22... Gate insulating layer 23... Gate electrode

Claims (1)

[Claims] 1. Forming a polycrystalline Si thin film on a substrate, forming a gate insulating film on the polycrystalline Si thin film without exposing the polycrystalline Si thin film to the atmosphere, and further forming a gate electrode on the gate insulating film. . A method for manufacturing a thin film transistor, comprising: thereafter patterning the polycrystalline Si thin film and the gate insulating film into a predetermined shape.