JPH03219636A - Multilayer interconnection structure - Google Patents

Multilayer interconnection structure

Info

Publication number
JPH03219636A
JPH03219636A JP1520690A JP1520690A JPH03219636A JP H03219636 A JPH03219636 A JP H03219636A JP 1520690 A JP1520690 A JP 1520690A JP 1520690 A JP1520690 A JP 1520690A JP H03219636 A JPH03219636 A JP H03219636A
Authority
JP
Japan
Prior art keywords
signal patterns
density
dummy pattern
multilayer wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1520690A
Other languages
Japanese (ja)
Inventor
Yoko Kato
加藤　洋子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1520690A priority Critical patent/JPH03219636A/en
Publication of JPH03219636A publication Critical patent/JPH03219636A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Abstract

PURPOSE:To make the thickness of a plated part and an insulation layer uniform, to eliminate a defect such as a short circuit or the like and to enhance the yield of a multilayer-interconnection substrate by a method wherein a dummy pattern is added to a part where the density of signal patterns is low. CONSTITUTION:Signal patterns 2 and a dummy pattern 3 are wired on a multilayer-interconnection substrate 1; an insulation layer 4 is formed on them. When the density of the signal patterns 2 is not balanced on the multilayer- interconnection substrate 1 in a state that the signal patterns 2 have been wired on it, the dummy pattern 3 is added to a part where the density of the signal patterns 2 is low. Thereby, the density of the signal patterns 2 and the dummy pattern 3 on the multilayer interconnection substrate 1 becomes uniform. When a plating operation is executed in this state, the plated thickness of the signal patterns 2 and the dummy pattern 3 and the thickness of the insulation layer 4 become nearly uniform.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層配線基板に関し、特に多層配線基板の構
造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring board, and particularly to the structure of a multilayer wiring board.

〔従来の技術〕[Conventional technology]

従来、この種の多層配線基板は、第３図および第４図に
示すように、信号パターンの密度が偏っている場合、信
号パターン２の密度が高い部分ではメツキが薄く、信号
パターン２の密度が低い部分ではメツキが厚くつく。こ
の上に絶縁４を形成するとメツキの薄い部分では絶縁４
が厚く、メツキの厚い部分では絶縁４が薄くなる。Conventionally, in this type of multilayer wiring board, as shown in FIGS. 3 and 4, when the density of the signal pattern is uneven, the plating is thin in the part where the density of the signal pattern 2 is high, and the density of the signal pattern 2 is uneven. The metal is thicker in areas where the surface is lower. When insulation 4 is formed on top of this, the thin part of the plating has insulation 4.
is thick, and the insulation 4 becomes thinner in the thicker plating parts.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の多層配線基板は、信号パターンの密度の
偏りによって、メツキの厚さ及び絶縁の厚かが不均一と
なり、絶縁の薄い部分においては短絡をおこすという欠
点がある。The above-mentioned conventional multilayer wiring board has the disadvantage that the thickness of the plating and the thickness of the insulation become uneven due to the unevenness of the density of the signal pattern, and short circuits occur in the thin insulation parts.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の多層配線基板は、信号パターンの存在しないエ
リア内に設けた電気的機能を有さないダミーパターンを
有している。The multilayer wiring board of the present invention has a dummy pattern that has no electrical function and is provided in an area where no signal pattern exists.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例である多層配線基板の平面図
である。第２図は本実施例の多層配線基板の断面拡大図
である。第１図と第２図に於て、本発明の一実施例は多
層配線基板１の上に信号パラメータ２とダミーパターン
３が配線されており、その上に絶縁４を形成している。FIG. 1 is a plan view of a multilayer wiring board which is an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of the multilayer wiring board of this embodiment. 1 and 2, in one embodiment of the present invention, signal parameters 2 and dummy patterns 3 are wired on a multilayer wiring board 1, and an insulator 4 is formed thereon.

多層配線基板１はその上に信号パターン２が配線されて
いる状態で、信号パターン２の密度に偏りがある場合、
信号パターン２の密度の低い部分にダミーパターン３を
追加することにより多層配線基板１の上の信号パターン
２及びダミーパターン３の密度が均一となる。この状態
でメツキを行った場合、第２図に示す通り信号パターン
２とダミーパターン３のメッキ厚及び絶縁４の厚さはほ
ぼ均一となる。When the signal pattern 2 is wired on the multilayer wiring board 1 and the density of the signal pattern 2 is uneven,
By adding the dummy pattern 3 to the low-density portion of the signal pattern 2, the density of the signal pattern 2 and the dummy pattern 3 on the multilayer wiring board 1 becomes uniform. When plating is performed in this state, the plating thickness of the signal pattern 2 and the dummy pattern 3 and the thickness of the insulation 4 become almost uniform as shown in FIG.

第３図に示す従来の多層配線基板１はその上に信号パタ
ーン２が配線されているが図に示すように信号パターン
２の偏りがある状態でメツキを行った場合第４図に示す
通り信号パターン２のメッキ厚は信号パターン２の密度
が高い部分では薄くなるが信号パターン２の密度が低い
部分では厚くなる。それに伴って絶縁４の厚さは不均一
となる。The conventional multilayer wiring board 1 shown in FIG. 3 has a signal pattern 2 wired thereon, but if plating is performed with the signal pattern 2 being biased as shown in the figure, the signal pattern 2 will appear as shown in FIG. 4. The plating thickness of the pattern 2 is thinner in areas where the density of the signal pattern 2 is high, but thicker in areas where the density of the signal pattern 2 is low. Accordingly, the thickness of the insulation 4 becomes non-uniform.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、信号パターンの密度の低
い部分にダミーパターンを追加するととにり、メツキ及
び絶縁の厚さを均一にし短絡等の不良をなくシ、多層配
線基板の歩留りを向上させる効果がある。As explained above, the present invention adds a dummy pattern to the low-density part of the signal pattern, makes the plating and insulation thickness uniform, eliminates defects such as short circuits, and improves the yield of multilayer wiring boards. It has the effect of

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例である多層配線基板を示す平
面図、第２図は本実施例の多層配線基板を示す断面拡大
図、第３図は従来の多層配線基板を示す平面図、第４図
は従来の多層配線基板を示す断面拡大図である。 １・・・多層配線基板、２・・・信号パターン、３・・
・ダミーパターン、４・・・絶縁。FIG. 1 is a plan view showing a multilayer wiring board according to an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view showing the multilayer wiring board according to this embodiment, and FIG. 3 is a plan view showing a conventional multilayer wiring board. , FIG. 4 is an enlarged cross-sectional view showing a conventional multilayer wiring board. 1...Multilayer wiring board, 2...Signal pattern, 3...
・Dummy pattern, 4...Insulation.

Claims (1)

【特許請求の範囲】[Claims] 信号パターンの密度に偏りのある多層配線基板において
、信号パターンの存在しないエリア内に電気的機能を有
さないダミーパターンを配置した事を特徴とする多層配
線基板。A multilayer wiring board with uneven density of signal patterns, characterized in that dummy patterns having no electrical function are arranged in areas where no signal patterns exist.
JP1520690A 1990-01-24 1990-01-24 Multilayer interconnection structure Pending JPH03219636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1520690A JPH03219636A (en) 1990-01-24 1990-01-24 Multilayer interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1520690A JPH03219636A (en) 1990-01-24 1990-01-24 Multilayer interconnection structure

Publications (1)

Publication Number Publication Date
JPH03219636A true JPH03219636A (en) 1991-09-27

Family

ID=11882396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1520690A Pending JPH03219636A (en) 1990-01-24 1990-01-24 Multilayer interconnection structure

Country Status (1)

Country Link
JP (1) JPH03219636A (en)

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