JPH03219370A - Dummy pattern generation system - Google Patents
Dummy pattern generation systemInfo
- Publication number
- JPH03219370A JPH03219370A JP2015205A JP1520590A JPH03219370A JP H03219370 A JPH03219370 A JP H03219370A JP 2015205 A JP2015205 A JP 2015205A JP 1520590 A JP1520590 A JP 1520590A JP H03219370 A JPH03219370 A JP H03219370A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- density
- area
- divided
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims description 8
- 238000004364 calculation method Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
C産業上の利用分野〕
本発明は、ダミーパターン発生方式に関し、特に配線基
板の配線設計におけるダミーパターン発生方式に関する
。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a dummy pattern generation method, and particularly to a dummy pattern generation method in wiring design of a wiring board.
従来、この種の配線基板は配線に使用されている部分と
配線に使用されていない部分を比較的分離される傾向に
あり、配線に使用されている部分の配線パターン密度の
配線に使用されていない配線パターン密度には大きな差
がある。Conventionally, in this type of wiring board, the part used for wiring and the part not used for wiring tend to be relatively separated, and the part used for wiring has a high wiring pattern density. There is a large difference in wiring pattern density.
配線基板上で配線パターンの密度に大きな差がある場合
には、製造のメツキ工程でメツキの厚さが極端に異なり
配線パターン上に形成する絶縁の厚さが不均一となる。If there is a large difference in the density of the wiring patterns on the wiring board, the thickness of the plating during the manufacturing plating process will be extremely different, and the thickness of the insulation formed on the wiring pattern will be non-uniform.
このため製造不良が発生しやすくなり製造歩留りが著し
く低下する。For this reason, manufacturing defects are likely to occur, resulting in a significant decrease in manufacturing yield.
製造歩留りを確保するための従来の技術としては、ダミ
ーパターンを人手で作成し配線基板上の配線パターンの
密度を均一化する方式がある。As a conventional technique for ensuring manufacturing yield, there is a method in which dummy patterns are created manually to equalize the density of wiring patterns on a wiring board.
上述した従来のダミーパターン作成方法は人手でダミー
パターンの設計を行うため
(1)配線パターンの密度の均一化が難しい。In the conventional dummy pattern creation method described above, the dummy patterns are designed manually, so (1) it is difficult to make the density of the wiring pattern uniform;
(2)設計の品質確保が難しい。(2) It is difficult to ensure the quality of the design.
(3)設計に時間がかかる。(3) It takes time to design.
等の欠点がある。There are drawbacks such as.
本発明のダミーパターン発生方式は、配線基板上の配線
パターンの密度を算出する手段と、配線パターンの密度
の低い領域の配線情報を発生する手段と、発生された配
線情報に基きダミーパターンを発生する手段とを有して
いる。The dummy pattern generation method of the present invention includes means for calculating the density of wiring patterns on a wiring board, means for generating wiring information in areas with low wiring pattern density, and generating a dummy pattern based on the generated wiring information. and the means to do so.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例によるダミーパターン発生方
式の処理動作を示す流れ図である。第1図において、本
発明の一実施例は処理ボックス1の配線パターン密度算
出部と、処理ボックス2の接続情報発生部と、処理ボッ
クス3のダミーパターン発生部とからなるダミーパター
ン発生方式を構成している。FIG. 1 is a flowchart showing the processing operation of a dummy pattern generation method according to an embodiment of the present invention. In FIG. 1, one embodiment of the present invention has a dummy pattern generation system consisting of a wiring pattern density calculation section in a processing box 1, a connection information generation section in a processing box 2, and a dummy pattern generation section in a processing box 3. are doing.
第2図は本発明の一実施例によるダミーパターン発生前
のイメージ図である。この実施例は配線鞄4の上に配線
領域5が設けられており、配線領域5は仮想分割線10
により分割配線領域6に分割されている。配線パターン
7は配線領域5の領域内で配線が行われており、座8に
接続されている。FIG. 2 is an image diagram before dummy pattern generation according to an embodiment of the present invention. In this embodiment, a wiring area 5 is provided on a wiring bag 4, and the wiring area 5 is formed by a virtual dividing line 10.
It is divided into divided wiring regions 6 by. The wiring pattern 7 is wired within the wiring area 5 and is connected to the seat 8.
第3図は本発明の一実施例によるダミーパターン発生後
のイメージ図である。配線基板4の上には配線領域5が
設けられており、配線領域5は仮想分割線10により分
割配線領域6に分割されている。配線パターン7および
ダミーパターン9は配線領域5の領域内で配線が行われ
ており、何れも座8に接続されている。FIG. 3 is an image diagram after the dummy pattern is generated according to an embodiment of the present invention. A wiring region 5 is provided on the wiring board 4 , and the wiring region 5 is divided into divided wiring regions 6 by virtual dividing lines 10 . The wiring pattern 7 and the dummy pattern 9 are wired within the wiring region 5, and both are connected to the seat 8.
第1図から第3図を用いて本発明の一実施例の処理動作
について説明する。The processing operation of an embodiment of the present invention will be explained using FIGS. 1 to 3.
まず第2図において、配線領域5内の配線パターン7の
配線長を分割線領域6毎に計算し、分割配線領域6の面
積で商をとり、分割配線領域6毎に配線密度を算出する
。第2図では分割配線領域6は9つの領域に分割を行っ
ているが、分割配線領域6の数を増やし分割の領域を細
かくすることにより、配線密度の算出精度を向上するこ
とができる。(第1図処理ボックス1)
次に配線密度の一番高い分割配線領域6と同程度の配線
密度となるよう各々の分割配線領域6内の未使用の座8
を使用しビンペア数と平均ピンペア長を計算し接続情報
を自動発生する。(第1図処理ボックス2)
次に第3図において、自動発生した接続情報に基づいて
各々の分割配線領域6内の座を接続しダミーパターン9
を発生する。(第1図処理ボックス3)
〔発明の効果〕
以上説明したように本発明は、配線パターンの密度を算
出する手段と、配線パターンの密度の低い領域の配線情
報を発生する手段と、発生された配線情報に基きダミー
パターンを発生する手段を有することにより、配線基板
上の配線パターンの密度の均一化をはかり製造時の歩留
りを確保することができる効果がある。First, in FIG. 2, the wiring length of the wiring pattern 7 in the wiring area 5 is calculated for each dividing line area 6, the quotient is taken by the area of the dividing wiring area 6, and the wiring density is calculated for each dividing wiring area 6. In FIG. 2, the divided wiring region 6 is divided into nine regions, but by increasing the number of divided wiring regions 6 and making the divided regions finer, the precision in calculating the wiring density can be improved. (Processing Box 1 in Figure 1) Next, fill in the unused seats 8 in each divided wiring area 6 so that the wiring density is the same as that of the divided wiring area 6 with the highest wiring density.
The number of bin pairs and average pin pair length are calculated using , and connection information is automatically generated. (Processing box 2 in FIG. 1) Next, in FIG. 3, the seats in each divided wiring area 6 are connected based on the automatically generated connection information to form a dummy pattern 9.
occurs. (Processing Box 3 in Figure 1) [Effects of the Invention] As explained above, the present invention provides a means for calculating the density of a wiring pattern, a means for generating wiring information of a region with a low density of wiring patterns, and a means for calculating the density of a wiring pattern. By having a means for generating a dummy pattern based on the wiring information, it is possible to equalize the density of the wiring pattern on the wiring board and to ensure the yield during manufacturing.
メージを示す図、第3図は本発明の一実施例によるダミ
ーパーターン発生後のイメージを示す図である。FIG. 3 is a diagram showing an image after a dummy pattern is generated according to an embodiment of the present invention.
1〜3・・・処理ボックス、4・・・配線基板、5・・
・配線領域、6・・・分割配線領域、7・・・配線パタ
ーン、8・・・座、9・・・ダミーパターン、10・・
・仮想分割線。1-3... Processing box, 4... Wiring board, 5...
・Wiring area, 6... Divided wiring area, 7... Wiring pattern, 8... Seat, 9... Dummy pattern, 10...
・Virtual dividing line.
Claims (1)
配線パターンの密度の低い領域の配線情報を発生する手
段と、発生された配線情報に基きダミーパターンを発生
する手段とを有することを特徴とするダミーパターン発
生方式。means for calculating the density of a wiring pattern on a wiring board;
A dummy pattern generation method comprising: means for generating wiring information for a region with low wiring pattern density; and means for generating a dummy pattern based on the generated wiring information.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015205A JP2867533B2 (en) | 1990-01-24 | 1990-01-24 | Dummy pattern generation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015205A JP2867533B2 (en) | 1990-01-24 | 1990-01-24 | Dummy pattern generation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03219370A true JPH03219370A (en) | 1991-09-26 |
JP2867533B2 JP2867533B2 (en) | 1999-03-08 |
Family
ID=11882368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015205A Expired - Fee Related JP2867533B2 (en) | 1990-01-24 | 1990-01-24 | Dummy pattern generation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2867533B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7226634B2 (en) | 2002-02-01 | 2007-06-05 | Fujitsu Limited | Designing a plated pattern in printed writing board |
-
1990
- 1990-01-24 JP JP2015205A patent/JP2867533B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7226634B2 (en) | 2002-02-01 | 2007-06-05 | Fujitsu Limited | Designing a plated pattern in printed writing board |
Also Published As
Publication number | Publication date |
---|---|
JP2867533B2 (en) | 1999-03-08 |
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