JPH03217953A - Address conversion system - Google Patents

Abstract

PURPOSE:To improve the address conversion efficiency by storing plural continuous page table entries into a real address register RAR at one time and then using successively and selectively these stored entries every time a page cross occurs. CONSTITUTION:A translator 8 loads successively the three fetched page entries, for example, into the #0RAR 13-#2RAR 15. At the same time, a real address selector 16 selects the #0RAR 13 when '0' is set to a selection counter SCNT 17. Under such conditions, the translator 8 checks the validity of the fetched page table entries and requests a program interruption exceptional to the conversion when the first page entry is invalid. Then the translator 8 loads the number of valid page entries into an RCNT 18 when the second and subsequent page entries are invalid. Then '3' is loaded to the RCNT 18 when all page entries are valid.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application 1 The present invention relates to an address translation method, and particularly to an address translation method suitable for fetching instructions in a data processing device.

[Prior Art] FIG. 3 is a diagram showing a conventional address conversion method. In this figure, (1) is the operand address register (abbreviated as OPR), (2) is OPR (abbreviated as OPR), and (2) is OPR (abbreviated as OPR).
(1) is the in-page address part, (3) is the virtual page address part of OPR (1), (4) is the instruction counter (abbreviated as IC), (5) is the in-page address part of IC (4), (6)
) is the virtual page address part of IC (4), (7) is the address translation buffer (abbreviated as TLB), (8) is the translator for performing address translation, and (ku) is the IC (
4) is an adder for counting up, (10) is a real operand address register (abbreviated as R O P R) for holding the real operand address after address conversion, and (11) is a page of ROPR (10). Internal address part, (12) is the real page address part of ROPR (10),
(20) is an operand cache, (21) is an operand buffer that temporarily stores data read from the operand cache (20), (22) is an instruction cache, and (23) is a read from the instruction cache (22). An instruction buffer that temporarily stores data (2
5) is a real instruction address register (abbreviated as RIAR) that stores the result of address conversion in C(4), and (26) is R.
In-page address part of IAR (25), (27) is RI
This is the real page address part of AR (25).

Next, the operation of the conventional example having the above configuration will be explained.

When trying to translate the address of a virtual instruction in IC (4), first, T L B (7') is subtracted, and it is checked whether the corresponding entry exists in this T L B (7). As a result of this investigation, if it is found that a corresponding entry exists in TLB (7), the corresponding real address is immediately sought and the RIAR
(25) is stored in the real page address field (27).

In addition, the in-page address part of R I AR (2 5) (
26) stores the contents of the intra-page address field (5) of the IC (4) as is, and reads instructions from the instruction cache (22>) to the instruction buffer (23).

On the other hand, the corresponding entry is T L B (7
), the translator (8) performs the required address translation and transfers the resulting real page address to the real page address section (27) of the TLB (7) and RIAR (25). Store in.

After this address conversion is once completed, the RIAR (25
) is used as is for accessing the instruction cache (22), and the real page address part (27) of T
No address translation is performed by L B (7) or translator (8). Then, when a page cross is detected by counting up the virtual page address section (6) in the IC (4), address conversion is executed again by the virtual page address section (6) in the IC (4).

For operand access, unlike instruction access, there is no continuity in addresses, so OPR (
From the virtual page address part (3) of 1), T L B
(7') and translator (8) and ROP the resulting real address.
It is stored in the real page address field (12) of R(to). Here, the in-page address field (11) of ROPR (10) stores the contents of the in-page address field (2) of OPR (1) as is, and together with the contents of the real page address field (12), Operand data from the operand cache (20) is read out into the operand buffer (21).

[Problem to be solved by the invention 1 The address conversion method in the conventional data processing device is configured as described above, and when a page cross occurs based on the address of an instruction fetch request, the address conversion method in the conventional data processing device is had the problem that instruction fetching had to wait.

Furthermore, since the TLB is shared with operand requests, there are also problems in that address translation during instruction fetching is forced to wait, and operand requests are interfered with.

This invention was made in order to solve the above-mentioned problems, and its purpose is to obtain an address translation method that is capable of translating addresses for multiple pages in one address translation process. .

[Means for Solving the Problems] The address conversion method according to the present invention is configured to simultaneously store a plurality of consecutive page table entries in a real address register, and to select and use them sequentially every time a page cross occurs. This is what is being done.

[Effect 1] In the present invention, the number of address conversions for instruction fetch is reduced by using a plurality of real address registers, and the conflict between instruction fetch and operand requests is reduced.

Embodiment 1 FIG. 1 is a block diagram showing an address translation method which is an embodiment of the present invention. In this FIG. 1, (1)
is the operand address register (abbreviated as OPR), (2
) is the in-page address part of OPR (1), (3) is OP
Virtual page address part of R (1), (4) is the instruction counter (abbreviated as IC), (5) is the in-page address part of ■C (4>), (6) is the virtual page address part of IC (4) ,
(7) is an address translation buffer (abbreviated as TLB),
(8) is a translator for address translation, (
9) is an adder for counting up IC (4);
(10) is the real operand address register (ROPR) for holding the real operand address after address conversion.
(11) is the in-page address part of ROPR (10), (12) is the real page address part of ROPR<10), (13) is the #0 real address register (abbreviated as RARO), (14) is #1 real address register (RARI)
), (15) is #2 real address register (RAR
(abbreviated as 2), (16) is a real address selector,
RARO (13> to RAR2 (15)) is used to select one of them for instruction cache access. (abbreviated as T), (18) is a register counter (RCNT) for holding information regarding the number of valid real address registers.
), (19》 is a comparator, and SCNT (abbreviated as 1.
7> and RCNT (1 8) to detect that they match, (2
0) is the operand cache, (21》) is the operand buffer that temporarily stores the data read from the operand cache (20), (22) is the instruction cache, and (23) is the data read from the instruction cache (22). An instruction buffer that temporarily stores (24)
is an address conversion request signal line, and SCNT (1 7
) and RCNT (18) match, and also serves to transmit a signal requesting the start of address translation.

FIG. 2 is an explanatory diagram regarding the execution of required address translation in the address translation method of the present invention.Next, regarding the operation of the embodiment having the above configuration,
While referring to FIGS. 1 and 2 as appropriate, we will now discuss the IC (4
) is converted into a corresponding real address by sending it to the translator (8). Since an instruction fetch is being performed here, the translator (8)
In this case, two more entries are fetched starting from the target entry on the page table 33).

The translator (8) learns the start address of the segment table (32) from the segment table origin (31), and updates the segment table (32) by the value shown in the segment index field (35) of the page address field (34). ) Determine the start address of the page table (33) from the segment entry at the address advanced above.

Next, from the start address of the page table (33) mentioned above, the page table (
33) The 11th entry in the address above is 7
、． 9-move male-to-do Since this page entry fetch is from the main memory (not shown), it is possible to fetch as many pages as the number of bytes in the cache block at once. Therefore, the translator (8} can easily extract pageantry portions corresponding to a plurality of pages (three pages in this embodiment) from among these byte numbers.

Then, in this translator (8), the three fetched pageantries are sequentially R
It is loaded from ARO (13) to RAR2 (15). On the other hand, by setting SCNT (17) to ``0'', the real address selector (16)
O(13) is selected. At this time, the translator (8) checks the validity of the fetched page table entry. For example, when the first pageantry is invalid, a program interrupt called a conversion exception is requested. Furthermore, when the second and subsequent page entries are invalid, the number of valid page entries is loaded into RCNT (18). Then, when all the pageantries are valid, the RCNT (1
8) will be loaded with 3. The following is R.C.N.
The case where 3 is loaded into T(18) will be explained.

First, the target real address part is output from the real address selector (16), and the in-page address part (
5), the instruction indicated by IC (4) is transferred from the instruction cache (22) to the instruction buffer (23).
is read out.

As the execution of the instruction progresses, the IC (4) counts up, but as a result, the virtual page address field (6) of the IC (4) is incremented, and a page cross may be detected. Then, SCNT (17) is incremented by a predetermined signal based on this detection. Then, the real address of the next page stored in RAR[14] is selected by the real address selector (16), thus without performing any address translation.
Instruction fetches from the next page are executed continuously.

Furthermore, when RAR2 (15) is used and a page cross occurs, the increment value of SCNT (17) becomes 3, which matches the value of RCNT (18). The comparator (19) detects this match and outputs an address translation request to the address translation request signal line (24). In response to this, address conversion is executed in the page address section (5) of the IC (4), and
RARO (13) ~ RARI (15), SCNT (17)
) and RCNT (18).

[Effects of the Invention] As explained above, according to the present invention, continuous page entries can be stored in a plurality of real address registers with only one address conversion. Therefore, the effect of more efficient address translation can be achieved. Furthermore, since the sharing of TLBs can be avoided, the independence between instruction fetch and operand request is increased, and the effect can be achieved whenever the usability of both is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an address conversion method according to an embodiment of the present invention, FIG.
The figure is a block diagram showing a conventional address translation method. (13) is #0 real address register, (14) is #1 real address register, (15) is #2 real address register, (16) is real address selector, (17) is select counter, (18) is register Counter, <19) is a comparator. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In an address translation method for a data processing device having an instruction cache and an operand cache: a plurality of real address registers holding consecutive page table entries; a real access selector that selects a real address for accessing the instruction cache; a select counter that holds selection information of the real address; a register counter that holds the number of valid registers of the real address register; A comparator is provided to detect when the value in the counter reaches the value in the register counter. When address translation is being performed by instruction fetch, the contents of consecutive page table entries are Store in the address register, reset the select counter, and set the number of valid page table entries in the register counter; Increment the select counter when a page cross is detected by counting up the instruction counter; Select counter An address conversion method characterized by: starting address conversion based on detection of a match between an increment value of and a value of a register counter.