JPH03215959A - Ic test system - Google Patents

Abstract

PURPOSE:To enable a trouble to be easily located and obviated by a method wherein a switching means is provided between the signal wires of a test device and operated at a terminal. CONSTITUTION:When a boards possessed of a same function are provided, the signal wire of a board 22 supposed to be in trouble and the signal wire of a board 23 supposed to be normal are exchange with each other by a switch 24 to replace the board 22 with the board 23. Therefore, a signal 26 (a) and a signal 27 (a) are transmitted through the same path and a signal 26 (b) and a signal 28 (b) travel the same route, so that the normal signal 26 (a) is inputted once into the board 22 which is supposed to be in trouble, and the output signal of the board 22 is outputted to an output terminal 30. The outputted signal concerned is compared with data which is outputted to the terminal 30 through the normal board 23 to which the signal 26 (a) is inputted, whereby a self- diagonis is made to locate a trouble basing on the comparison of data, and a test is made to start again. By this setup, a trouble can easily be located and obviated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC test system, and particularly to one that is designed to improve its reliability and operating time.

：Prior Art] FIGS. 3 to 5 are diagrams showing a test processing state, a system processing state, and a failure state in a conventional IC test system, respectively, where 1 indicates a failure occurrence, 2 indicates a processing state, and 3
is the processing result, 4 is the method of finding the fault location, 5 is the cause of a single fault, 6 is the state of multiple fault causes, and 7 is the state where one fault at multiple fault locations affects other boards. Represents the state of being. Generally, in an IC test system, the clock driver, comparator, channel card, etc. are each configured on one board, and these are connected by commands from the CPU or connected to each other with signal lines.
Configured to function.

Next, the operation will be explained.

In the test processing state of FIG. 3, due to failure occurrence 1, the tester performs self-diagnosis or incorrect processing in processing state 2, and stops the test or outputs an incorrect data result in processing result 3. In the case of I stem processing state M6 in the figure: * vi
How to find faults in P student 1 and D's G co'raster 4.1
Along these lines, 7 self-diagnosis will be performed to discover the location of the failure, and as a result of the processing, repairs will be carried out.

In the types of failure states shown in Figure 5, (a) represents the case where the failure occurs at a single location, (b) represents the case where there are multiple failure causes, and (C) represents the case where the failure is caused by a single failure location. Indicates the state where the area is affected.

[Problem to be solved by the invention]

Conventional IC test systems are configured as described above, and because they perform the processing shown in Figure 4 in the event of a failure, they have the problem that they become unusable in the event of a failure. When there is a single cause of failure (Fig. 5 (a)), it is easy to discover and deal with the cause of the failure; however, when there are multiple causes of failure (Fig. 5 (b)). ) and in a state where one faulty part is affecting other boards (Figure 5 (C)), it is not easy to discover the cause of the fault, and in this case too, there is a problem that the operation time of the tester is reduced. .

This invention was made to solve the above-mentioned problems, and even in cases where there are multiple causes of failure, or where a single failure location is causing multiple failures, it is possible to identify the cause of failure. The object of the present invention is to obtain an IC test system that facilitates the discovery and treatment of problems.

[Means to solve the problem]

The IC test system according to the present invention is provided with switching means between the signal lines of the test device, and the switching operation is performed on the terminal.

[Effect]

In this invention, a switching means is provided between the signal lines, and the switching operation is performed on the terminal, so that the test signal can freely move between the signal lines, and a normal test signal can always be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining the configuration and operation of an IC test system according to an embodiment of the present invention.
21 is a CPU, 22 is a board that seems to be broken, 23 is a board with the same function, 24 is a changeover switch that is a switching means, 25 is a signal line, 26 is a signal during normal operation, 27.2
8 is a signal at the time of failure, and 29.30 is an output terminal.

Next, the operation will be explained.

If there are multiple boards with the same function within the system,
Board 22 that seems to be broken and board 23 that seems to be normal
The signal line is switched with the switch 24. As a result, the board that seems to be in trouble is replaced with a normal board.

Therefore, the output of the board 22 that is considered to be faulty is switched to the output of a normal, unused board with the same function, and a normal signal 26 is output to the output terminal 30. In addition, the normal signal 26 is first input to the board 22 that is considered to be faulty, and the signal is output to the output terminal 30, and self-diagnosis is performed by comparing it with the previously output signal 26. Based on this data comparison, Find the location of the failure. The test will then resume immediately. Although FIG. 1 shows only one board with the same function, there is actually a plurality of boards.

FIG. 2 is a diagram for explaining the configuration and operation of an IC test system according to another embodiment of the present invention. In this embodiment, there is one board with the same function, and there is also one normally used board. In the figure, 31 is CP
U, 32 is a spare board, 33 is a board that seems to be broken,
34 is a changeover switch, 35 is a signal line, 36 is a signal during normal operation, 37 is a signal during failure, and 38 is an output terminal.

In this case, a spare board with the same function is built into the system and is not normally used, but when a failure occurs, the signal line between the board that is considered to be in failure and the spare board with the same function is switched. Therefore, the board that is considered to be defective is replaced with a spare board. Therefore, after the signal is switched, the normal spare board performs self-diagnosis again, and from the results, a fault in the board is discovered. Testing can also be resumed immediately by using the spare board as normal.

In this way, according to this embodiment, the signal line 25 of the test equipment
Since a changeover switch 24 is provided between the two and the switching operation is performed on the terminal, a normal signal can always be obtained even in the event of a failure, and the test can be restarted immediately. In addition, by comparing the faulty board and the normal board at the time of a fault, the fault location can be easily found and the reliability of the device can be improved.

〔Effect of the invention〕

As described above, according to the IC test system according to the present invention, a changeover switch is provided between the signal lines and the switching operation is performed on the terminal, so that the failure location can be detected early, and even in the event of a failure, it can be immediately detected. This has the effect of allowing tests to be restarted and improving system uptime.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the configuration and operation of an IC test system according to one embodiment of the present invention, and FIG. 2 is a diagram for explaining the configuration and operation of an IC test system according to another embodiment of the present invention. . FIGS. 3 to 5 are diagrams showing a test processing state, a system processing state, and a failure state, respectively, in a conventional IC test system. In the figure, 21 is a CPU, 22 is a board that seems to be faulty, 23 is a normal board with the same function, and 24 is a changeover switch.

Claims (1)

[Claims] (1) An IC test system consisting of a plurality of boards and used to test whether an IC is good or bad, characterized by having switching means for switching signals between each signal line. .