JPH03214907A - Waveform generating method - Google Patents

Abstract

PURPOSE:To prevent the occurrence of clock leakage or glitch to a waveform of a prescribed constant output by controlling a reference clock with an output data of a clock memory so as to stop the access of a waveform memory and DA-conversion of a D/A converter for the waveform of a prescribed constant output in a waveform data. CONSTITUTION:An arithmetic and control circuit 4a sets a data change point number 10 to an address generator and, data change point data is stored in a waveform memory 3 and data of a low level when a same data is consecutive and data of a high level when data is not consecutive is stored in a clock memory 12. Waveform data of 80H, FFH, 80H, 00H,... is outputted from the waveform memory 3. A D/A converter 5 DA-converts the data and outputs an analog waveform. Thus, a waveform in which no clock leakage or glitch superimposition takes place is generated to a part of a data without waveform change.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an improvement in a waveform generation method of a waveform generator using a waveform memory and a digital-to-analog converter (hereinafter referred to as a DA converter).

<Conventional technology> The waveform data stored in the waveform memory is read out sequentially, and the D
There is a waveform generator that generates an arbitrary analog waveform by converting it into an analog signal using an A converter. FIG. 7 is a block diagram showing an example of a conventional waveform generator of this type. In the figure, 1 is a clock generator that generates a reference clock.

2 is an address generator that generates an address for accessing the waveform memory 3; The waveform memory 3 has an arithmetic/control circuit 4
The desired waveform data is stored from the address generator 2, and its contents (waveform data =
n-bit data) is read out and given to the DA converter 5. The DA converter 5 performs analog conversion based on the clock from the clock generator 1.

The arithmetic/control circuit 4 calculates waveform data (digital data) based on the definition formula, stores each waveform data obtained in this way in the waveform memory 3, and also processes control signals necessary for each part. It also has the ability to generate

Problems to be Solved by the Invention> By the way, in the waveform generator having such a configuration, the eighth
When outputting a waveform like the one shown in Figure (a), during DA conversion, clock leaks and noise components called glitches are mixed into the part where the constant output continues, resulting in a waveform like the one shown in Figure (b). It had the disadvantage of being

SUMMARY OF THE INVENTION An object of the present invention is to provide a waveform generation method capable of generating a waveform in which no clock or glitch occurs in a waveform portion where a constant output continues.

Means to solve problems〉 FIG. 1 is a diagram showing the principle flow of the present invention.

The waveform memory stores only data at waveform data change points, and the clock memory stores data that goes low when the same data continues in the original waveform data, and goes high when the data changes. The contents of the clock memory are read out using the reference clock generated by the clock generator, and the contents of the clock memory are set to H.
The method is characterized by a step of outputting a reference clock only when the signal is IGH, reading out the contents of the waveform memory using an address from an address generator updated by this output clock, and performing DA conversion using the output clock. shall be.

Function> By controlling the reference clock with the output data of the clock memory, access to the waveform memory and DA conversion by the DA converter are stopped in the waveform portion where a constant output continues in the waveform data.

Through such control, it is possible to generate a waveform in which clocks and glitches are not superimposed in the waveform portion of the DA conversion output waveform where a constant output continues.

Embodiment> FIG. 2 is a block diagram showing an embodiment of an apparatus for carrying out the method of the present invention. In the figure, 1 is a clock generator that generates a reference clock, and 11 is an address counter, which has the function of receiving a clock signal from the clock generator 1 and converting it into an address access signal for the clock memory 12. In relation to the waveform data stored in the waveform memory 3, the clock memory 12 receives a LOW level signal (logical 0 signal) when the output waveform data is a series of the same data, and a LOW level signal (logical 0 signal) when the waveform data changes. Data that becomes a HIGH level signal (logical 1 signal) is stored.

13 is an AND gate, into which the output of the clock memory 12 and the clock via the first delay circuit 15 are input. The first delay circuit 15 is for adjusting the phase of the signal output from the clock memory 12 and the clock from the clock generator 1 (matching the phases).

A switch 14 selects either the output of the AND gate 13 or the output of the clock generator 1. The selected output is input to the address generator 2 and the second delay circuit 16. The address generator 2 receives a clock from the waveform memory 3 provided via the switch 16.
Generate an address to access.

4a is an arithmetic/control circuit which generates control signals necessary for each part and has the following functions.

That is, waveform data is obtained by calculation based on a definition formula, and data in a compressed form of the waveform data, that is, so-called data change point data that is constructed by extracting only points where data changes from the calculation data, is stored in the waveform memory 3. Store in. Further, the clock memory 12 is provided with data converted into the format described above.

The second delay circuit 16 is for time-delaying the signal in order to match the phase of the data output from the waveform memory 3 and the clock applied to the DA converter 5.

The operation in such a configuration will be explained next.

As an example, assume that the DA converter 5 outputs a waveform as shown in FIG. 3(a), and the address generator 2 starts from address 00 and returns to address 00 from the final address 15. explain.

(1) When the clock from the clock generator 1 is selected by the switch 14 (same operation as in the conventional case) ① The arithmetic/control circuit 4a sets the final address 15 in the address generator 2.

(2) The arithmetic/control circuit 4a stores data corresponding to the output of the DA converter shown in FIG. 3(a) at addresses 00 to 15 of the waveform memory 3.

■The address generator 2 receives the input clock (Fig. 3(b)
)) accesses the address of the waveform memory 3.

The read data ((C) in the same figure) is converted into analog by the DA converter 5, and the waveform shown in (a) in the same figure is output.

(2) When the output of the AND gate 13 is selected by the switch 14 In this case, the clock input to the waveform memory 3 is stopped when the same output continues, and the data output is not updated. method and follow these steps:

(2) The arithmetic/control circuit 4a sets the number of data change points to 10 in the address generator 2.

(2) The arithmetic/control circuit 4a stores data change point data, ie, data as shown in FIG. 3(d), in the waveform memory 3.

(2) The arithmetic/control circuit 4a stores data in the clock memory 12, as shown in FIG. 3(e), which is set to LOW level when the same data continues, and set to HIGH level when it changes.

(2) The output of the AND gate 13 becomes a gated clock as shown in FIG. 3(f), and an address for accessing the waveform memory 3 is output from the address generator 2 using this clock.

(2) The values shown in FIG. 3(g) are sequentially output from the waveform memory 3. That is, 80H (H is a code indicating that the value is a hexadecimal number), FFH, 80H. OOH, ,
, ． waveform data is output.

(2) The DA converter 5 performs DA conversion on this and outputs an analog waveform as shown in FIG. 3(h).

In the manner described above, it is possible to generate a waveform in which no clock leak or glitch is superimposed in a portion where the waveform does not change.

In the embodiment shown in FIG. 2, the access time of the clock memory 12 is faster than the clock, but FIG. 4 shows a configuration example in which the memory access time is slower than the clock. This case is an example where the access time of the clock memory is eight times slower than the reference clock.

The difference between FIG. 4 and FIG. 2 is the address generator clock generation means 20. In FIG. The details of this ADSIS generator clock generation means 20 are shown in FIG. 21 is a frequency divider that divides the clock from clock generator 1 by 8; 22
30 is an address counter group consisting of eight address counters, 40 is a clock memory group consisting of eight clock memories, and 23 is a shift register.

The frequency divider 21 divides the reference clock by eight (this clock is called a divided clock), and the clock driver 22 manually inputs this divided clock to eight address counters in parallel.

Each output of the address counter reads out the contents of the corresponding clock memory, and the eight outputs are simultaneously input to the shift register 23. The shift register 23 uses the reference clock as a shift clock to shift the eight inputs taken in and sequentially output them.

In such a configuration, when the switch 14 is set to the reference clock selection side, a waveform output can be obtained by the conventional operation. When the switch 14 is set to the AND gate side, the following operation occurs. Note that only operations that are different from the explanation in FIG. 2 will be explained. The contents of the clock memory (D1 to D8, D9 to D9 shown in FIG. 6) are determined by the timing of the clock distributed from the frequency divider 21 to eight clock memories.
D16,. ．． ．． ) enter inputs 1 to 8 of the shift register 23. From the shift register 23, as shown in FIG. 6(d), DI, D2, D3, . ．． ．． are output in this order. This output is input to the AND gate 13 as in the case of FIG. 2, and is ANDed with the reference clock to obtain a gated clock.

<Effects of the Invention> As explained in detail above, according to the present invention, when the output data does not change, the waveform memory is not accessed and DA conversion is not performed (data is not updated).
It is possible to obtain a high-quality waveform without superimposing digital noise or glitches in the waveform portion where the output does not change.

[Brief explanation of drawings]

Figure 1 is the principle flow of the waveform generation method according to the present invention. Figure 2 is a block diagram showing an embodiment of a device for carrying out the present invention. Figure 3 is a diagram of data and waveforms of each part to explain the operation. , FIG. 4 and FIG. 5 are configuration diagrams of other embodiments of the apparatus for carrying out the present invention, FIG. 6 is a time chart for explaining the operation of the apparatus of FIG. 4, and FIG. 7 is a diagram of the conventional apparatus. A configuration diagram showing an example of a waveform generator. FIG. 8 is an explanatory diagram showing waveforms of various parts in a conventional device. 1... Clock generator 2... Address generator 3... Waveform memory 4a... Arithmetic/control circuit 5... DA converter 11... Address counter 12... Clock memory 13...・And gate 14...Switch 1
5.16...Delay circuit Fig. 6 (0) Basic single clock (b) Memory 1 Output 01 09 5 Fig. 7 Fig. 8

Claims (1)

[Claims] Sequentially reading waveform data stored in a waveform memory,
In a waveform generator that generates an arbitrary analog waveform by converting it into an analog signal with an A converter, the waveform memory stores only data at waveform data change points, and the clock memory stores the original waveform. When the same data continues, the level is LOW,
For data at changing points, there is a process of storing data that becomes HIGH level, and a process of reading out the contents of the clock memory using the reference clock generated by the clock generator, and ensuring that the contents of the clock memory are HIGH.
The DA conversion consists of the steps of outputting the reference clock only when the signal is IGH, reading out the contents of the waveform memory using the address from the address generator updated by this output clock, and performing DA conversion using the output clock. A waveform generation method characterized in that clocks and glitches are not superimposed on a waveform portion of an output waveform where a constant output continues.