JPH03274915A - Function generator - Google Patents

Abstract

PURPOSE:To reduce jitter by forming a required variable frequency clock by a direct digital synthesizer(DDS), accessing a digital waveform memory and executing D/A conversion and high frequency component removal or the like. CONSTITUTION:A digital waveform is read out from the first waveform memory 2 with the output of an adder 1, which adds an output to be operated synchro nously with the master clock of the DDS and a frequency value, as an address and passed through a first D/A converter 3 and first LPF 4 and a binary signal is outputted from a comparator 6 which compares the read waveform with the level '0' of a required threshold value. This output of the DDS is defined as the address and divided with a designated frequency dividing ratio. Then, an address generator 7 generates the address of a frequency with a double span to the frequency of the master clock, and the second waveform memory 8 is accessed. Afterwards, the read digital waveform is outputted through a second D/A converter 9 and second LPF 10. Thus, the memory 8 is read our from the same point of each waveform memory 8 over all frequency ranges, and the waveform is obtained while suppressing the jitter at a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a digital function generator, and more particularly to an improvement for reducing jitter.

<Prior Art> A digital function generator outputs an analog waveform by sequentially reading out waveform data stored in a waveform memory in advance and converting the data into analog data at the same time. FIG. 4 shows an example of the configuration of a conventional general function generator. The adder 1 provides an address for reading out waveform data from the waveform memory 2 (for example, waveform data as shown in FIG. 5(a)). Adder 1 has one input as a frequency value (
This is a value that specifies the increment amount of the address when reading.As shown in Figure 5 (b) and (c), the increment amount is small when outputting at a low frequency, and large when outputting at a high frequency. The other input is the output of the adder 1 itself.

The addition operation is performed every time the clock from the master clock generator 5 is input, and therefore the waveform memory 2
The initial value is 0, and each time a clock is applied, a frequency value is added to the address. When the clock from the master clock generator 5 is input to the waveform memory 2 (input as a read signal), the contents (waveform data) of the designated address are read. The read waveform data is converted into analog by a digital-to-analog converter (hereinafter referred to as DAC) 3. The DAC 3 operates by clock input from the master clock generator 5.

A signal obtained by sequentially reading waveform data and converting it into an analog signal has harmonic components removed by a low-pass filter 4, is shaped into a smooth waveform, and is sent out.

In this way, an analog signal of a desired frequency can be output from the waveform data stored in the waveform memory 2.

<Problems to be Solved by the Invention> However, such a function generator has the following problems. When reading waveform data from the waveform memory 2, it normally passes through different points (addresses) in the waveform memory 2 every cycle (when the address of the waveform memory changes cyclically, the second and subsequent times are the same as the first address). Therefore, this amount appears as jitter (frequency jitter). The magnitude of jitter in this case is at most one period of the master clock.

The present invention has been made in view of these points, and its purpose is to realize a function generator with less jitter by making the frequency of the master clock variable.

Means for Solving the Problems> The present invention to achieve such objects comprises: a master clock generator (5) that generates a master clock; an adder (1) that outputs a value incremented by a frequency value related to the frequency of the adder (1); and a first waveform memory (1) in which waveform data of a sine wave is stored and from which waveform data at an address given from the adder is read out. 2), a first digital-to-analog converter (3) that converts the output of this first waveform memory (2) into analog, and a harmonic component from the output of this first digital-to-analog converter (3). A comparator (4) that compares the output of the first low-pass filter (4) with the 0 level and generates a rectangular waveform clock that becomes a binary signal depending on the magnitude 6), an address generator (7) that divides the output of this comparator (6) at a set frequency division ratio, and the output waveform data is stored, and the output of the address generator (7) is used as an address. a second waveform memory (8) from which the waveform data at that address is read; and a second digital-to-analog converter (9) which converts the output of the second waveform memory (8) into analog. , and a second low-pass filter (10) that removes harmonic components of the output of the second digital-to-analog converter (9).

Effects> In the present invention, the DDS unit generates a variable frequency clock over twice the frequency span, and the address generator (7) divides this clock appropriately to obtain an address. Access the waveform memory (8) using this address,
Read the waveform data.

The read waveform data is transferred to a digital-to-analog converter (9
), and then the harmonic components are removed using a low-pass filter (10).

The output waveform thus obtained is a waveform read from the same address point of the waveform memory (8) every cycle over the entire frequency range, resulting in a waveform with minimal jitter.

<Example> The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a function generator according to the present invention. In the figure, adder 1,
First waveform memory 2 (waveform memory for clock), first
The components up to the DAC 3, first low-pass filter 4, and clock master clock generator 5 are the same as the configuration of the conventional example shown in FIG. However, in this case, the waveform memory 2 stores sine wave waveform data.

6 is a comparator that compares the output of the low-pass filter 4 with the 0 level, and when it is larger than that, the output goes to HIGH level;
When it is small, a LOW level signal is output. Therefore, the comparator 6 outputs a rectangular wave having a frequency related to the frequency value given to the adder 1. This rectangular wave is given as a clock to the subsequent circuit.

Reference numeral 7 denotes an address generator that generates an address to be given to the second waveform memory 8, and obtains an address to the waveform memory 8 by dividing the number of clocks output from the comparator 6 according to a frequency division ratio given from the outside. Waveform data to be output is stored in advance in the waveform memory 8. 9 is a second DAC, which converts the waveform data read from the waveform memory 8 into a DA.
Convert. 10 is a second low-pass filter;
This is for removing harmonic components of the output of the DAC 9.

FIG. 2 is a detailed configuration diagram of a specific example of the address generator 7. As shown in FIG. This address generator is composed of a binary counter 71, and the digit position to which the clock (output of the comparator 6) is input is switched by a switch 72 according to the value of the frequency division ratio.

The operation in such a configuration will be explained. The section consisting of the adder 1, first waveform memory 2, first DAC 3, first low-pass filter 4, master clock generator 5 (generates a fixed frequency clock), and comparator 6 is a so-called direct digital Synthesizer (D
This is the part called DS). It is sufficient for the frequency of the clock generated here to have a span twice the clock frequency span. As a result, even if the cutoff frequency of the second low-pass filter 10 at the subsequent stage is fixed, harmonic components can be sufficiently cut, and a high-quality (low jitter) clock can be obtained.

The address generator 7, the second waveform memory 8, and the second DAC 9 are operated by the clock obtained from the comparator 6. In the address generator 7, a wide range of frequencies can be determined by the combination of this clock and the frequency division ratio. Table 1 shows an example. In this case, the size of the second waveform memory 8 was set to 256 points.

FIG. 3 is a diagram illustrating the relationships in Table 1 using a triangular wave as an example. As is clear from the figure, when the frequency is high,
Skip the data in the second waveform memory 8 and read more detailed data if it is low. This is the same as in the conventional case, but the location (address) read from the waveform memory 8 every cycle is constant. You can see that it doesn't shift. Therefore, there will be no occurrence of Jeddah.

Note that it is also clear that continuous setting of frequencies between frequency division ratios can be performed in the DDS section.

Table 1 <Effects of the Invention> As explained in detail above, according to the present invention, the generated waveform generates the same point in each cycle over the entire frequency range, thereby minimizing the jitter. 0 that enables waveform generation

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a function generator according to the present invention, FIG. 2 is a specific block diagram of an address generator, and FIG. 3 is a diagram showing an example of readout points in the case of triangular wave generation. FIG. 4 is a block diagram showing an example of a conventional general function generator, and FIG. 5 is a diagram showing the relationship between addresses and data of the waveform memory in FIG. 4. 1... Adder 2... First waveform memory 3... First DAC 4... First low-pass filter 5... Clock master clock generator 6... Comparator 7...・Address generator 8...second
Waveform memory 9...Second DAC 10...Second low-pass filter 71...Binary counter 72...Switch

Claims (1)

[Claims] A master clock generator (
5); an adder (1) that outputs a value incremented by a frequency value related to the frequency of the clock to be generated each time the master clock is input; and an adder (1) in which sine wave waveform data is stored; a first waveform memory (2) from which waveform data at an address given from the adder is read; a first digital-to-analog converter (3) that converts the output of the first waveform memory (2) into analog; A first low-pass filter (4) removes harmonic components from the output of this first digital-to-analog converter (3), and the output of this first low-pass filter (4) is compared with the 0 level. A comparator (6) that generates a rectangular waveform clock that becomes a binary signal depending on the magnitude, an address generator (7) that divides the output of this comparator (6) at a set frequency division ratio, and an output a second waveform memory (8) in which waveform data is stored, and when the output of the address generator (7) is given as an address, the waveform data at that address is read out; a second digital-analog converter (9) that converts the output of the second digital-analog converter (9) into analog; a second low-pass filter (10) that removes harmonic components of the output of the second digital-analog converter (9); A function generator characterized in that the frequency jitter of the output obtained from the second low-pass filter (10) is reduced.